dma/ipu/ipu_irq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2008
0004  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
0005  */
0006
0007 #include <linux/init.h>
0008 #include <linux/err.h>
0009 #include <linux/spinlock.h>
0010 #include <linux/delay.h>
0011 #include <linux/clk.h>
0012 #include <linux/irq.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/dma/ipu-dma.h>
0016
0017 #include "ipu_intern.h"
0018
0019 /*
0020  * Register read / write - shall be inlined by the compiler
0021  */
0022 static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg)
0023 {
0024     return __raw_readl(ipu->reg_ipu + reg);
0025 }
0026
0027 static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg)
0028 {
0029     __raw_writel(value, ipu->reg_ipu + reg);
0030 }
0031
0032
0033 /*
0034  * IPU IRQ chip driver
0035  */
0036
0037 #define IPU_IRQ_NR_FN_BANKS 3
0038 #define IPU_IRQ_NR_ERR_BANKS 2
0039 #define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS)
0040
0041 struct ipu_irq_bank {
0042     unsigned int    control;
0043     unsigned int    status;
0044     struct ipu  *ipu;
0045 };
0046
0047 static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = {
0048     /* 3 groups of functional interrupts */
0049     {
0050         .control    = IPU_INT_CTRL_1,
0051         .status     = IPU_INT_STAT_1,
0052     }, {
0053         .control    = IPU_INT_CTRL_2,
0054         .status     = IPU_INT_STAT_2,
0055     }, {
0056         .control    = IPU_INT_CTRL_3,
0057         .status     = IPU_INT_STAT_3,
0058     },
0059     /* 2 groups of error interrupts */
0060     {
0061         .control    = IPU_INT_CTRL_4,
0062         .status     = IPU_INT_STAT_4,
0063     }, {
0064         .control    = IPU_INT_CTRL_5,
0065         .status     = IPU_INT_STAT_5,
0066     },
0067 };
0068
0069 struct ipu_irq_map {
0070     unsigned int        irq;
0071     int         source;
0072     struct ipu_irq_bank *bank;
0073     struct ipu      *ipu;
0074 };
0075
0076 static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
0077 /* Protects allocations from the above array of maps */
0078 static DEFINE_MUTEX(map_lock);
0079 /* Protects register accesses and individual mappings */
0080 static DEFINE_RAW_SPINLOCK(bank_lock);
0081
0082 static struct ipu_irq_map *src2map(unsigned int src)
0083 {
0084     int i;
0085
0086     for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++)
0087         if (irq_map[i].source == src)
0088             return irq_map + i;
0089
0090     return NULL;
0091 }
0092
0093 static void ipu_irq_unmask(struct irq_data *d)
0094 {
0095     struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
0096     struct ipu_irq_bank *bank;
0097     uint32_t reg;
0098     unsigned long lock_flags;
0099
0100     raw_spin_lock_irqsave(&bank_lock, lock_flags);
0101
0102     bank = map->bank;
0103     if (!bank) {
0104         raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0105         pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
0106         return;
0107     }
0108
0109     reg = ipu_read_reg(bank->ipu, bank->control);
0110     reg |= (1UL << (map->source & 31));
0111     ipu_write_reg(bank->ipu, reg, bank->control);
0112
0113     raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0114 }
0115
0116 static void ipu_irq_mask(struct irq_data *d)
0117 {
0118     struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
0119     struct ipu_irq_bank *bank;
0120     uint32_t reg;
0121     unsigned long lock_flags;
0122
0123     raw_spin_lock_irqsave(&bank_lock, lock_flags);
0124
0125     bank = map->bank;
0126     if (!bank) {
0127         raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0128         pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
0129         return;
0130     }
0131
0132     reg = ipu_read_reg(bank->ipu, bank->control);
0133     reg &= ~(1UL << (map->source & 31));
0134     ipu_write_reg(bank->ipu, reg, bank->control);
0135
0136     raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0137 }
0138
0139 static void ipu_irq_ack(struct irq_data *d)
0140 {
0141     struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
0142     struct ipu_irq_bank *bank;
0143     unsigned long lock_flags;
0144
0145     raw_spin_lock_irqsave(&bank_lock, lock_flags);
0146
0147     bank = map->bank;
0148     if (!bank) {
0149         raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0150         pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
0151         return;
0152     }
0153
0154     ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
0155     raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0156 }
0157
0158 /**
0159  * ipu_irq_status() - returns the current interrupt status of the specified IRQ.
0160  * @irq:    interrupt line to get status for.
0161  * @return: true if the interrupt is pending/asserted or false if the
0162  *      interrupt is not pending.
0163  */
0164 bool ipu_irq_status(unsigned int irq)
0165 {
0166     struct ipu_irq_map *map = irq_get_chip_data(irq);
0167     struct ipu_irq_bank *bank;
0168     unsigned long lock_flags;
0169     bool ret;
0170
0171     raw_spin_lock_irqsave(&bank_lock, lock_flags);
0172     bank = map->bank;
0173     ret = bank && ipu_read_reg(bank->ipu, bank->status) &
0174         (1UL << (map->source & 31));
0175     raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0176
0177     return ret;
0178 }
0179
0180 /**
0181  * ipu_irq_map() - map an IPU interrupt source to an IRQ number
0182  * @source: interrupt source bit position (see below)
0183  * @return: mapped IRQ number or negative error code
0184  *
0185  * The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ
0186  * sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17.
0187  * However, the source argument of this function is not the sequence number of
0188  * the possible IRQ, but rather its bit position. So, first interrupt in fourth
0189  * register has source number 96, and not 88. This makes calculations easier,
0190  * and also provides forward compatibility with any future IPU implementations
0191  * with any interrupt bit assignments.
0192  */
0193 int ipu_irq_map(unsigned int source)
0194 {
0195     int i, ret = -ENOMEM;
0196     struct ipu_irq_map *map;
0197
0198     might_sleep();
0199
0200     mutex_lock(&map_lock);
0201     map = src2map(source);
0202     if (map) {
0203         pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq);
0204         ret = -EBUSY;
0205         goto out;
0206     }
0207
0208     for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
0209         if (irq_map[i].source < 0) {
0210             unsigned long lock_flags;
0211
0212             raw_spin_lock_irqsave(&bank_lock, lock_flags);
0213             irq_map[i].source = source;
0214             irq_map[i].bank = irq_bank + source / 32;
0215             raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0216
0217             ret = irq_map[i].irq;
0218             pr_debug("IPU: mapped source %u to IRQ %u\n",
0219                  source, ret);
0220             break;
0221         }
0222     }
0223 out:
0224     mutex_unlock(&map_lock);
0225
0226     if (ret < 0)
0227         pr_err("IPU: couldn't map source %u: %d\n", source, ret);
0228
0229     return ret;
0230 }
0231
0232 /**
0233  * ipu_irq_unmap() - unmap an IPU interrupt source
0234  * @source: interrupt source bit position (see ipu_irq_map())
0235  * @return: 0 or negative error code
0236  */
0237 int ipu_irq_unmap(unsigned int source)
0238 {
0239     int i, ret = -EINVAL;
0240
0241     might_sleep();
0242
0243     mutex_lock(&map_lock);
0244     for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
0245         if (irq_map[i].source == source) {
0246             unsigned long lock_flags;
0247
0248             pr_debug("IPU: unmapped source %u from IRQ %u\n",
0249                  source, irq_map[i].irq);
0250
0251             raw_spin_lock_irqsave(&bank_lock, lock_flags);
0252             irq_map[i].source = -EINVAL;
0253             irq_map[i].bank = NULL;
0254             raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
0255
0256             ret = 0;
0257             break;
0258         }
0259     }
0260     mutex_unlock(&map_lock);
0261
0262     return ret;
0263 }
0264
0265 /* Chained IRQ handler for IPU function and error interrupt */
0266 static void ipu_irq_handler(struct irq_desc *desc)
0267 {
0268     struct ipu *ipu = irq_desc_get_handler_data(desc);
0269     u32 status;
0270     int i, line;
0271
0272     for (i = 0; i < IPU_IRQ_NR_BANKS; i++) {
0273         struct ipu_irq_bank *bank = irq_bank + i;
0274
0275         raw_spin_lock(&bank_lock);
0276         status = ipu_read_reg(ipu, bank->status);
0277         /*
0278          * Don't think we have to clear all interrupts here, they will
0279          * be acked by ->handle_irq() (handle_level_irq). However, we
0280          * might want to clear unhandled interrupts after the loop...
0281          */
0282         status &= ipu_read_reg(ipu, bank->control);
0283         raw_spin_unlock(&bank_lock);
0284         while ((line = ffs(status))) {
0285             struct ipu_irq_map *map;
0286             unsigned int irq;
0287
0288             line--;
0289             status &= ~(1UL << line);
0290
0291             raw_spin_lock(&bank_lock);
0292             map = src2map(32 * i + line);
0293             if (!map) {
0294                 raw_spin_unlock(&bank_lock);
0295                 pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
0296                        line, i);
0297                 continue;
0298             }
0299             irq = map->irq;
0300             raw_spin_unlock(&bank_lock);
0301             generic_handle_irq(irq);
0302         }
0303     }
0304 }
0305
0306 static struct irq_chip ipu_irq_chip = {
0307     .name       = "ipu_irq",
0308     .irq_ack    = ipu_irq_ack,
0309     .irq_mask   = ipu_irq_mask,
0310     .irq_unmask = ipu_irq_unmask,
0311 };
0312
0313 /* Install the IRQ handler */
0314 int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
0315 {
0316     unsigned int irq, i;
0317     int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
0318                        numa_node_id());
0319
0320     if (irq_base < 0)
0321         return irq_base;
0322
0323     for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
0324         irq_bank[i].ipu = ipu;
0325
0326     for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
0327         int ret;
0328
0329         irq = irq_base + i;
0330         ret = irq_set_chip(irq, &ipu_irq_chip);
0331         if (ret < 0)
0332             return ret;
0333         ret = irq_set_chip_data(irq, irq_map + i);
0334         if (ret < 0)
0335             return ret;
0336         irq_map[i].ipu = ipu;
0337         irq_map[i].irq = irq;
0338         irq_map[i].source = -EINVAL;
0339         irq_set_handler(irq, handle_level_irq);
0340         irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
0341     }
0342
0343     irq_set_chained_handler_and_data(ipu->irq_fn, ipu_irq_handler, ipu);
0344
0345     irq_set_chained_handler_and_data(ipu->irq_err, ipu_irq_handler, ipu);
0346
0347     ipu->irq_base = irq_base;
0348
0349     return 0;
0350 }
0351
0352 void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
0353 {
0354     unsigned int irq, irq_base;
0355
0356     irq_base = ipu->irq_base;
0357
0358     irq_set_chained_handler_and_data(ipu->irq_fn, NULL, NULL);
0359
0360     irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
0361
0362     for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) {
0363         irq_set_status_flags(irq, IRQ_NOREQUEST);
0364         irq_set_chip(irq, NULL);
0365         irq_set_chip_data(irq, NULL);
0366     }
0367 }