dma/ipu/ipu_intern.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2008
0004  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
0005  *
0006  * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
0007  */
0008
0009 #ifndef _IPU_INTERN_H_
0010 #define _IPU_INTERN_H_
0011
0012 #include <linux/dmaengine.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/interrupt.h>
0015
0016 /* IPU Common registers */
0017 #define IPU_CONF        0x00
0018 #define IPU_CHA_BUF0_RDY    0x04
0019 #define IPU_CHA_BUF1_RDY    0x08
0020 #define IPU_CHA_DB_MODE_SEL 0x0C
0021 #define IPU_CHA_CUR_BUF     0x10
0022 #define IPU_FS_PROC_FLOW    0x14
0023 #define IPU_FS_DISP_FLOW    0x18
0024 #define IPU_TASKS_STAT      0x1C
0025 #define IPU_IMA_ADDR        0x20
0026 #define IPU_IMA_DATA        0x24
0027 #define IPU_INT_CTRL_1      0x28
0028 #define IPU_INT_CTRL_2      0x2C
0029 #define IPU_INT_CTRL_3      0x30
0030 #define IPU_INT_CTRL_4      0x34
0031 #define IPU_INT_CTRL_5      0x38
0032 #define IPU_INT_STAT_1      0x3C
0033 #define IPU_INT_STAT_2      0x40
0034 #define IPU_INT_STAT_3      0x44
0035 #define IPU_INT_STAT_4      0x48
0036 #define IPU_INT_STAT_5      0x4C
0037 #define IPU_BRK_CTRL_1      0x50
0038 #define IPU_BRK_CTRL_2      0x54
0039 #define IPU_BRK_STAT        0x58
0040 #define IPU_DIAGB_CTRL      0x5C
0041
0042 /* IPU_CONF Register bits */
0043 #define IPU_CONF_CSI_EN     0x00000001
0044 #define IPU_CONF_IC_EN      0x00000002
0045 #define IPU_CONF_ROT_EN     0x00000004
0046 #define IPU_CONF_PF_EN      0x00000008
0047 #define IPU_CONF_SDC_EN     0x00000010
0048 #define IPU_CONF_ADC_EN     0x00000020
0049 #define IPU_CONF_DI_EN      0x00000040
0050 #define IPU_CONF_DU_EN      0x00000080
0051 #define IPU_CONF_PXL_ENDIAN 0x00000100
0052
0053 /* Image Converter Registers */
0054 #define IC_CONF         0x88
0055 #define IC_PRP_ENC_RSC      0x8C
0056 #define IC_PRP_VF_RSC       0x90
0057 #define IC_PP_RSC       0x94
0058 #define IC_CMBP_1       0x98
0059 #define IC_CMBP_2       0x9C
0060 #define PF_CONF         0xA0
0061 #define IDMAC_CONF      0xA4
0062 #define IDMAC_CHA_EN        0xA8
0063 #define IDMAC_CHA_PRI       0xAC
0064 #define IDMAC_CHA_BUSY      0xB0
0065
0066 /* Image Converter Register bits */
0067 #define IC_CONF_PRPENC_EN   0x00000001
0068 #define IC_CONF_PRPENC_CSC1 0x00000002
0069 #define IC_CONF_PRPENC_ROT_EN   0x00000004
0070 #define IC_CONF_PRPVF_EN    0x00000100
0071 #define IC_CONF_PRPVF_CSC1  0x00000200
0072 #define IC_CONF_PRPVF_CSC2  0x00000400
0073 #define IC_CONF_PRPVF_CMB   0x00000800
0074 #define IC_CONF_PRPVF_ROT_EN    0x00001000
0075 #define IC_CONF_PP_EN       0x00010000
0076 #define IC_CONF_PP_CSC1     0x00020000
0077 #define IC_CONF_PP_CSC2     0x00040000
0078 #define IC_CONF_PP_CMB      0x00080000
0079 #define IC_CONF_PP_ROT_EN   0x00100000
0080 #define IC_CONF_IC_GLB_LOC_A    0x10000000
0081 #define IC_CONF_KEY_COLOR_EN    0x20000000
0082 #define IC_CONF_RWS_EN      0x40000000
0083 #define IC_CONF_CSI_MEM_WR_EN   0x80000000
0084
0085 #define IDMA_CHAN_INVALID   0x000000FF
0086 #define IDMA_IC_0       0x00000001
0087 #define IDMA_IC_1       0x00000002
0088 #define IDMA_IC_2       0x00000004
0089 #define IDMA_IC_3       0x00000008
0090 #define IDMA_IC_4       0x00000010
0091 #define IDMA_IC_5       0x00000020
0092 #define IDMA_IC_6       0x00000040
0093 #define IDMA_IC_7       0x00000080
0094 #define IDMA_IC_8       0x00000100
0095 #define IDMA_IC_9       0x00000200
0096 #define IDMA_IC_10      0x00000400
0097 #define IDMA_IC_11      0x00000800
0098 #define IDMA_IC_12      0x00001000
0099 #define IDMA_IC_13      0x00002000
0100 #define IDMA_SDC_BG     0x00004000
0101 #define IDMA_SDC_FG     0x00008000
0102 #define IDMA_SDC_MASK       0x00010000
0103 #define IDMA_SDC_PARTIAL    0x00020000
0104 #define IDMA_ADC_SYS1_WR    0x00040000
0105 #define IDMA_ADC_SYS2_WR    0x00080000
0106 #define IDMA_ADC_SYS1_CMD   0x00100000
0107 #define IDMA_ADC_SYS2_CMD   0x00200000
0108 #define IDMA_ADC_SYS1_RD    0x00400000
0109 #define IDMA_ADC_SYS2_RD    0x00800000
0110 #define IDMA_PF_QP      0x01000000
0111 #define IDMA_PF_BSP     0x02000000
0112 #define IDMA_PF_Y_IN        0x04000000
0113 #define IDMA_PF_U_IN        0x08000000
0114 #define IDMA_PF_V_IN        0x10000000
0115 #define IDMA_PF_Y_OUT       0x20000000
0116 #define IDMA_PF_U_OUT       0x40000000
0117 #define IDMA_PF_V_OUT       0x80000000
0118
0119 #define TSTAT_PF_H264_PAUSE 0x00000001
0120 #define TSTAT_CSI2MEM_MASK  0x0000000C
0121 #define TSTAT_CSI2MEM_OFFSET    2
0122 #define TSTAT_VF_MASK       0x00000600
0123 #define TSTAT_VF_OFFSET     9
0124 #define TSTAT_VF_ROT_MASK   0x000C0000
0125 #define TSTAT_VF_ROT_OFFSET 18
0126 #define TSTAT_ENC_MASK      0x00000180
0127 #define TSTAT_ENC_OFFSET    7
0128 #define TSTAT_ENC_ROT_MASK  0x00030000
0129 #define TSTAT_ENC_ROT_OFFSET    16
0130 #define TSTAT_PP_MASK       0x00001800
0131 #define TSTAT_PP_OFFSET     11
0132 #define TSTAT_PP_ROT_MASK   0x00300000
0133 #define TSTAT_PP_ROT_OFFSET 20
0134 #define TSTAT_PF_MASK       0x00C00000
0135 #define TSTAT_PF_OFFSET     22
0136 #define TSTAT_ADCSYS1_MASK  0x03000000
0137 #define TSTAT_ADCSYS1_OFFSET    24
0138 #define TSTAT_ADCSYS2_MASK  0x0C000000
0139 #define TSTAT_ADCSYS2_OFFSET    26
0140
0141 #define TASK_STAT_IDLE      0
0142 #define TASK_STAT_ACTIVE    1
0143 #define TASK_STAT_WAIT4READY    2
0144
0145 struct idmac {
0146     struct dma_device   dma;
0147 };
0148
0149 struct ipu {
0150     void __iomem        *reg_ipu;
0151     void __iomem        *reg_ic;
0152     unsigned int        irq_fn;     /* IPU Function IRQ to the CPU */
0153     unsigned int        irq_err;    /* IPU Error IRQ to the CPU */
0154     unsigned int        irq_base;   /* Beginning of the IPU IRQ range */
0155     unsigned long       channel_init_mask;
0156     spinlock_t      lock;
0157     struct clk      *ipu_clk;
0158     struct device       *dev;
0159     struct idmac        idmac;
0160     struct idmac_channel    channel[IPU_CHANNELS_NUM];
0161     struct tasklet_struct   tasklet;
0162 };
0163
0164 #define to_idmac(d) container_of(d, struct idmac, dma)
0165
0166 extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev);
0167 extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev);
0168
0169 extern bool ipu_irq_status(uint32_t irq);
0170 extern int ipu_irq_map(unsigned int source);
0171 extern int ipu_irq_unmap(unsigned int source);
0172
0173 #endif