dma/ioat/hw.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
0004  */
0005 #ifndef _IOAT_HW_H_
0006 #define _IOAT_HW_H_
0007
0008 /* PCI Configuration Space Values */
0009 #define IOAT_MMIO_BAR       0
0010
0011 /* CB device ID's */
0012 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
0013 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
0014 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
0015 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
0016 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
0017 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
0018 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
0019 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
0020 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
0021 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
0022
0023 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0   0x2f20
0024 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1   0x2f21
0025 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2   0x2f22
0026 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3   0x2f23
0027 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4   0x2f24
0028 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5   0x2f25
0029 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6   0x2f26
0030 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7   0x2f27
0031 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8   0x2f2e
0032 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9   0x2f2f
0033
0034 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0   0x0C50
0035 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1   0x0C51
0036 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2   0x0C52
0037 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3   0x0C53
0038
0039 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
0040 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
0041 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
0042 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
0043
0044 #define PCI_DEVICE_ID_INTEL_IOAT_BDX0   0x6f20
0045 #define PCI_DEVICE_ID_INTEL_IOAT_BDX1   0x6f21
0046 #define PCI_DEVICE_ID_INTEL_IOAT_BDX2   0x6f22
0047 #define PCI_DEVICE_ID_INTEL_IOAT_BDX3   0x6f23
0048 #define PCI_DEVICE_ID_INTEL_IOAT_BDX4   0x6f24
0049 #define PCI_DEVICE_ID_INTEL_IOAT_BDX5   0x6f25
0050 #define PCI_DEVICE_ID_INTEL_IOAT_BDX6   0x6f26
0051 #define PCI_DEVICE_ID_INTEL_IOAT_BDX7   0x6f27
0052 #define PCI_DEVICE_ID_INTEL_IOAT_BDX8   0x6f2e
0053 #define PCI_DEVICE_ID_INTEL_IOAT_BDX9   0x6f2f
0054
0055 #define PCI_DEVICE_ID_INTEL_IOAT_SKX    0x2021
0056
0057 #define PCI_DEVICE_ID_INTEL_IOAT_ICX    0x0b00
0058
0059 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
0060 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
0061 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
0062 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
0063 #define IOAT_VER_3_3            0x33    /* Version 3.3 */
0064 #define IOAT_VER_3_4        0x34    /* Version 3.4 */
0065
0066
0067 int system_has_dca_enabled(struct pci_dev *pdev);
0068
0069 #define IOAT_DESC_SZ    64
0070
0071 struct ioat_dma_descriptor {
0072     uint32_t    size;
0073     union {
0074         uint32_t ctl;
0075         struct {
0076             unsigned int int_en:1;
0077             unsigned int src_snoop_dis:1;
0078             unsigned int dest_snoop_dis:1;
0079             unsigned int compl_write:1;
0080             unsigned int fence:1;
0081             unsigned int null:1;
0082             unsigned int src_brk:1;
0083             unsigned int dest_brk:1;
0084             unsigned int bundle:1;
0085             unsigned int dest_dca:1;
0086             unsigned int hint:1;
0087             unsigned int rsvd2:13;
0088             #define IOAT_OP_COPY 0x00
0089             unsigned int op:8;
0090         } ctl_f;
0091     };
0092     uint64_t    src_addr;
0093     uint64_t    dst_addr;
0094     uint64_t    next;
0095     uint64_t    rsv1;
0096     uint64_t    rsv2;
0097     /* store some driver data in an unused portion of the descriptor */
0098     union {
0099         uint64_t    user1;
0100         uint64_t    tx_cnt;
0101     };
0102     uint64_t    user2;
0103 };
0104
0105 struct ioat_xor_descriptor {
0106     uint32_t    size;
0107     union {
0108         uint32_t ctl;
0109         struct {
0110             unsigned int int_en:1;
0111             unsigned int src_snoop_dis:1;
0112             unsigned int dest_snoop_dis:1;
0113             unsigned int compl_write:1;
0114             unsigned int fence:1;
0115             unsigned int src_cnt:3;
0116             unsigned int bundle:1;
0117             unsigned int dest_dca:1;
0118             unsigned int hint:1;
0119             unsigned int rsvd:13;
0120             #define IOAT_OP_XOR 0x87
0121             #define IOAT_OP_XOR_VAL 0x88
0122             unsigned int op:8;
0123         } ctl_f;
0124     };
0125     uint64_t    src_addr;
0126     uint64_t    dst_addr;
0127     uint64_t    next;
0128     uint64_t    src_addr2;
0129     uint64_t    src_addr3;
0130     uint64_t    src_addr4;
0131     uint64_t    src_addr5;
0132 };
0133
0134 struct ioat_xor_ext_descriptor {
0135     uint64_t    src_addr6;
0136     uint64_t    src_addr7;
0137     uint64_t    src_addr8;
0138     uint64_t    next;
0139     uint64_t    rsvd[4];
0140 };
0141
0142 struct ioat_pq_descriptor {
0143     union {
0144         uint32_t    size;
0145         uint32_t    dwbes;
0146         struct {
0147             unsigned int rsvd:25;
0148             unsigned int p_val_err:1;
0149             unsigned int q_val_err:1;
0150             unsigned int rsvd1:4;
0151             unsigned int wbes:1;
0152         } dwbes_f;
0153     };
0154     union {
0155         uint32_t ctl;
0156         struct {
0157             unsigned int int_en:1;
0158             unsigned int src_snoop_dis:1;
0159             unsigned int dest_snoop_dis:1;
0160             unsigned int compl_write:1;
0161             unsigned int fence:1;
0162             unsigned int src_cnt:3;
0163             unsigned int bundle:1;
0164             unsigned int dest_dca:1;
0165             unsigned int hint:1;
0166             unsigned int p_disable:1;
0167             unsigned int q_disable:1;
0168             unsigned int rsvd2:2;
0169             unsigned int wb_en:1;
0170             unsigned int prl_en:1;
0171             unsigned int rsvd3:7;
0172             #define IOAT_OP_PQ 0x89
0173             #define IOAT_OP_PQ_VAL 0x8a
0174             #define IOAT_OP_PQ_16S 0xa0
0175             #define IOAT_OP_PQ_VAL_16S 0xa1
0176             unsigned int op:8;
0177         } ctl_f;
0178     };
0179     uint64_t    src_addr;
0180     uint64_t    p_addr;
0181     uint64_t    next;
0182     uint64_t    src_addr2;
0183     union {
0184         uint64_t    src_addr3;
0185         uint64_t    sed_addr;
0186     };
0187     uint8_t     coef[8];
0188     uint64_t    q_addr;
0189 };
0190
0191 struct ioat_pq_ext_descriptor {
0192     uint64_t    src_addr4;
0193     uint64_t    src_addr5;
0194     uint64_t    src_addr6;
0195     uint64_t    next;
0196     uint64_t    src_addr7;
0197     uint64_t    src_addr8;
0198     uint64_t    rsvd[2];
0199 };
0200
0201 struct ioat_pq_update_descriptor {
0202     uint32_t    size;
0203     union {
0204         uint32_t ctl;
0205         struct {
0206             unsigned int int_en:1;
0207             unsigned int src_snoop_dis:1;
0208             unsigned int dest_snoop_dis:1;
0209             unsigned int compl_write:1;
0210             unsigned int fence:1;
0211             unsigned int src_cnt:3;
0212             unsigned int bundle:1;
0213             unsigned int dest_dca:1;
0214             unsigned int hint:1;
0215             unsigned int p_disable:1;
0216             unsigned int q_disable:1;
0217             unsigned int rsvd:3;
0218             unsigned int coef:8;
0219             #define IOAT_OP_PQ_UP 0x8b
0220             unsigned int op:8;
0221         } ctl_f;
0222     };
0223     uint64_t    src_addr;
0224     uint64_t    p_addr;
0225     uint64_t    next;
0226     uint64_t    src_addr2;
0227     uint64_t    p_src;
0228     uint64_t    q_src;
0229     uint64_t    q_addr;
0230 };
0231
0232 struct ioat_raw_descriptor {
0233     uint64_t    field[8];
0234 };
0235
0236 struct ioat_pq16a_descriptor {
0237     uint8_t coef[8];
0238     uint64_t src_addr3;
0239     uint64_t src_addr4;
0240     uint64_t src_addr5;
0241     uint64_t src_addr6;
0242     uint64_t src_addr7;
0243     uint64_t src_addr8;
0244     uint64_t src_addr9;
0245 };
0246
0247 struct ioat_pq16b_descriptor {
0248     uint64_t src_addr10;
0249     uint64_t src_addr11;
0250     uint64_t src_addr12;
0251     uint64_t src_addr13;
0252     uint64_t src_addr14;
0253     uint64_t src_addr15;
0254     uint64_t src_addr16;
0255     uint64_t rsvd;
0256 };
0257
0258 union ioat_sed_pq_descriptor {
0259     struct ioat_pq16a_descriptor a;
0260     struct ioat_pq16b_descriptor b;
0261 };
0262
0263 #define SED_SIZE    64
0264
0265 struct ioat_sed_raw_descriptor {
0266     uint64_t    a[8];
0267     uint64_t    b[8];
0268     uint64_t    c[8];
0269 };
0270
0271 #endif