drivers/dma/idma64.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Core driver for the Intel integrated DMA 64-bit
0004  *
0005  * Copyright (C) 2015 Intel Corporation
0006  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/delay.h>
0011 #include <linux/dmaengine.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/dmapool.h>
0014 #include <linux/init.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/slab.h>
0018
0019 #include <linux/dma/idma64.h>
0020
0021 #include "idma64.h"
0022
0023 /* For now we support only two channels */
0024 #define IDMA64_NR_CHAN      2
0025
0026 /* ---------------------------------------------------------------------- */
0027
0028 static struct device *chan2dev(struct dma_chan *chan)
0029 {
0030     return &chan->dev->device;
0031 }
0032
0033 /* ---------------------------------------------------------------------- */
0034
0035 static void idma64_off(struct idma64 *idma64)
0036 {
0037     unsigned short count = 100;
0038
0039     dma_writel(idma64, CFG, 0);
0040
0041     channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
0042     channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
0043     channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
0044     channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
0045     channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
0046
0047     do {
0048         cpu_relax();
0049     } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
0050 }
0051
0052 static void idma64_on(struct idma64 *idma64)
0053 {
0054     dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
0055 }
0056
0057 /* ---------------------------------------------------------------------- */
0058
0059 static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
0060 {
0061     u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
0062     u32 cfglo = 0;
0063
0064     /* Set default burst alignment */
0065     cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
0066
0067     channel_writel(idma64c, CFG_LO, cfglo);
0068     channel_writel(idma64c, CFG_HI, cfghi);
0069
0070     /* Enable interrupts */
0071     channel_set_bit(idma64, MASK(XFER), idma64c->mask);
0072     channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
0073
0074     /*
0075      * Enforce the controller to be turned on.
0076      *
0077      * The iDMA is turned off in ->probe() and looses context during system
0078      * suspend / resume cycle. That's why we have to enable it each time we
0079      * use it.
0080      */
0081     idma64_on(idma64);
0082 }
0083
0084 static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
0085 {
0086     channel_clear_bit(idma64, CH_EN, idma64c->mask);
0087 }
0088
0089 static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
0090 {
0091     struct idma64_desc *desc = idma64c->desc;
0092     struct idma64_hw_desc *hw = &desc->hw[0];
0093
0094     channel_writeq(idma64c, SAR, 0);
0095     channel_writeq(idma64c, DAR, 0);
0096
0097     channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
0098     channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
0099
0100     channel_writeq(idma64c, LLP, hw->llp);
0101
0102     channel_set_bit(idma64, CH_EN, idma64c->mask);
0103 }
0104
0105 static void idma64_stop_transfer(struct idma64_chan *idma64c)
0106 {
0107     struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
0108
0109     idma64_chan_stop(idma64, idma64c);
0110 }
0111
0112 static void idma64_start_transfer(struct idma64_chan *idma64c)
0113 {
0114     struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
0115     struct virt_dma_desc *vdesc;
0116
0117     /* Get the next descriptor */
0118     vdesc = vchan_next_desc(&idma64c->vchan);
0119     if (!vdesc) {
0120         idma64c->desc = NULL;
0121         return;
0122     }
0123
0124     list_del(&vdesc->node);
0125     idma64c->desc = to_idma64_desc(vdesc);
0126
0127     /* Configure the channel */
0128     idma64_chan_init(idma64, idma64c);
0129
0130     /* Start the channel with a new descriptor */
0131     idma64_chan_start(idma64, idma64c);
0132 }
0133
0134 /* ---------------------------------------------------------------------- */
0135
0136 static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
0137         u32 status_err, u32 status_xfer)
0138 {
0139     struct idma64_chan *idma64c = &idma64->chan[c];
0140     struct idma64_desc *desc;
0141
0142     spin_lock(&idma64c->vchan.lock);
0143     desc = idma64c->desc;
0144     if (desc) {
0145         if (status_err & (1 << c)) {
0146             dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
0147             desc->status = DMA_ERROR;
0148         } else if (status_xfer & (1 << c)) {
0149             dma_writel(idma64, CLEAR(XFER), idma64c->mask);
0150             desc->status = DMA_COMPLETE;
0151             vchan_cookie_complete(&desc->vdesc);
0152             idma64_start_transfer(idma64c);
0153         }
0154
0155         /* idma64_start_transfer() updates idma64c->desc */
0156         if (idma64c->desc == NULL || desc->status == DMA_ERROR)
0157             idma64_stop_transfer(idma64c);
0158     }
0159     spin_unlock(&idma64c->vchan.lock);
0160 }
0161
0162 static irqreturn_t idma64_irq(int irq, void *dev)
0163 {
0164     struct idma64 *idma64 = dev;
0165     u32 status = dma_readl(idma64, STATUS_INT);
0166     u32 status_xfer;
0167     u32 status_err;
0168     unsigned short i;
0169
0170     dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
0171
0172     /* Check if we have any interrupt from the DMA controller */
0173     if (!status)
0174         return IRQ_NONE;
0175
0176     status_xfer = dma_readl(idma64, RAW(XFER));
0177     status_err = dma_readl(idma64, RAW(ERROR));
0178
0179     for (i = 0; i < idma64->dma.chancnt; i++)
0180         idma64_chan_irq(idma64, i, status_err, status_xfer);
0181
0182     return IRQ_HANDLED;
0183 }
0184
0185 /* ---------------------------------------------------------------------- */
0186
0187 static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
0188 {
0189     struct idma64_desc *desc;
0190
0191     desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
0192     if (!desc)
0193         return NULL;
0194
0195     desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
0196     if (!desc->hw) {
0197         kfree(desc);
0198         return NULL;
0199     }
0200
0201     return desc;
0202 }
0203
0204 static void idma64_desc_free(struct idma64_chan *idma64c,
0205         struct idma64_desc *desc)
0206 {
0207     struct idma64_hw_desc *hw;
0208
0209     if (desc->ndesc) {
0210         unsigned int i = desc->ndesc;
0211
0212         do {
0213             hw = &desc->hw[--i];
0214             dma_pool_free(idma64c->pool, hw->lli, hw->llp);
0215         } while (i);
0216     }
0217
0218     kfree(desc->hw);
0219     kfree(desc);
0220 }
0221
0222 static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
0223 {
0224     struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
0225
0226     idma64_desc_free(idma64c, to_idma64_desc(vdesc));
0227 }
0228
0229 static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
0230         struct dma_slave_config *config,
0231         enum dma_transfer_direction direction, u64 llp)
0232 {
0233     struct idma64_lli *lli = hw->lli;
0234     u64 sar, dar;
0235     u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
0236     u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
0237     u32 src_width, dst_width;
0238
0239     if (direction == DMA_MEM_TO_DEV) {
0240         sar = hw->phys;
0241         dar = config->dst_addr;
0242         ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
0243              IDMA64C_CTLL_FC_M2P;
0244         src_width = __ffs(sar | hw->len | 4);
0245         dst_width = __ffs(config->dst_addr_width);
0246     } else {    /* DMA_DEV_TO_MEM */
0247         sar = config->src_addr;
0248         dar = hw->phys;
0249         ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
0250              IDMA64C_CTLL_FC_P2M;
0251         src_width = __ffs(config->src_addr_width);
0252         dst_width = __ffs(dar | hw->len | 4);
0253     }
0254
0255     lli->sar = sar;
0256     lli->dar = dar;
0257
0258     lli->ctlhi = ctlhi;
0259     lli->ctllo = ctllo |
0260              IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
0261              IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
0262              IDMA64C_CTLL_DST_WIDTH(dst_width) |
0263              IDMA64C_CTLL_SRC_WIDTH(src_width);
0264
0265     lli->llp = llp;
0266 }
0267
0268 static void idma64_desc_fill(struct idma64_chan *idma64c,
0269         struct idma64_desc *desc)
0270 {
0271     struct dma_slave_config *config = &idma64c->config;
0272     unsigned int i = desc->ndesc;
0273     struct idma64_hw_desc *hw = &desc->hw[i - 1];
0274     struct idma64_lli *lli = hw->lli;
0275     u64 llp = 0;
0276
0277     /* Fill the hardware descriptors and link them to a list */
0278     do {
0279         hw = &desc->hw[--i];
0280         idma64_hw_desc_fill(hw, config, desc->direction, llp);
0281         llp = hw->llp;
0282         desc->length += hw->len;
0283     } while (i);
0284
0285     /* Trigger an interrupt after the last block is transfered */
0286     lli->ctllo |= IDMA64C_CTLL_INT_EN;
0287
0288     /* Disable LLP transfer in the last block */
0289     lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
0290 }
0291
0292 static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
0293         struct dma_chan *chan, struct scatterlist *sgl,
0294         unsigned int sg_len, enum dma_transfer_direction direction,
0295         unsigned long flags, void *context)
0296 {
0297     struct idma64_chan *idma64c = to_idma64_chan(chan);
0298     struct idma64_desc *desc;
0299     struct scatterlist *sg;
0300     unsigned int i;
0301
0302     desc = idma64_alloc_desc(sg_len);
0303     if (!desc)
0304         return NULL;
0305
0306     for_each_sg(sgl, sg, sg_len, i) {
0307         struct idma64_hw_desc *hw = &desc->hw[i];
0308
0309         /* Allocate DMA capable memory for hardware descriptor */
0310         hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
0311         if (!hw->lli) {
0312             desc->ndesc = i;
0313             idma64_desc_free(idma64c, desc);
0314             return NULL;
0315         }
0316
0317         hw->phys = sg_dma_address(sg);
0318         hw->len = sg_dma_len(sg);
0319     }
0320
0321     desc->ndesc = sg_len;
0322     desc->direction = direction;
0323     desc->status = DMA_IN_PROGRESS;
0324
0325     idma64_desc_fill(idma64c, desc);
0326     return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
0327 }
0328
0329 static void idma64_issue_pending(struct dma_chan *chan)
0330 {
0331     struct idma64_chan *idma64c = to_idma64_chan(chan);
0332     unsigned long flags;
0333
0334     spin_lock_irqsave(&idma64c->vchan.lock, flags);
0335     if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
0336         idma64_start_transfer(idma64c);
0337     spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
0338 }
0339
0340 static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
0341 {
0342     struct idma64_desc *desc = idma64c->desc;
0343     struct idma64_hw_desc *hw;
0344     size_t bytes = desc->length;
0345     u64 llp = channel_readq(idma64c, LLP);
0346     u32 ctlhi = channel_readl(idma64c, CTL_HI);
0347     unsigned int i = 0;
0348
0349     do {
0350         hw = &desc->hw[i];
0351         if (hw->llp == llp)
0352             break;
0353         bytes -= hw->len;
0354     } while (++i < desc->ndesc);
0355
0356     if (!i)
0357         return bytes;
0358
0359     /* The current chunk is not fully transfered yet */
0360     bytes += desc->hw[--i].len;
0361
0362     return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
0363 }
0364
0365 static enum dma_status idma64_tx_status(struct dma_chan *chan,
0366         dma_cookie_t cookie, struct dma_tx_state *state)
0367 {
0368     struct idma64_chan *idma64c = to_idma64_chan(chan);
0369     struct virt_dma_desc *vdesc;
0370     enum dma_status status;
0371     size_t bytes;
0372     unsigned long flags;
0373
0374     status = dma_cookie_status(chan, cookie, state);
0375     if (status == DMA_COMPLETE)
0376         return status;
0377
0378     spin_lock_irqsave(&idma64c->vchan.lock, flags);
0379     vdesc = vchan_find_desc(&idma64c->vchan, cookie);
0380     if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
0381         bytes = idma64_active_desc_size(idma64c);
0382         dma_set_residue(state, bytes);
0383         status = idma64c->desc->status;
0384     } else if (vdesc) {
0385         bytes = to_idma64_desc(vdesc)->length;
0386         dma_set_residue(state, bytes);
0387     }
0388     spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
0389
0390     return status;
0391 }
0392
0393 static void convert_burst(u32 *maxburst)
0394 {
0395     if (*maxburst)
0396         *maxburst = __fls(*maxburst);
0397     else
0398         *maxburst = 0;
0399 }
0400
0401 static int idma64_slave_config(struct dma_chan *chan,
0402         struct dma_slave_config *config)
0403 {
0404     struct idma64_chan *idma64c = to_idma64_chan(chan);
0405
0406     memcpy(&idma64c->config, config, sizeof(idma64c->config));
0407
0408     convert_burst(&idma64c->config.src_maxburst);
0409     convert_burst(&idma64c->config.dst_maxburst);
0410
0411     return 0;
0412 }
0413
0414 static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
0415 {
0416     unsigned short count = 100;
0417     u32 cfglo;
0418
0419     cfglo = channel_readl(idma64c, CFG_LO);
0420     if (drain)
0421         cfglo |= IDMA64C_CFGL_CH_DRAIN;
0422     else
0423         cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
0424
0425     channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
0426     do {
0427         udelay(1);
0428         cfglo = channel_readl(idma64c, CFG_LO);
0429     } while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
0430 }
0431
0432 static void idma64_chan_activate(struct idma64_chan *idma64c)
0433 {
0434     u32 cfglo;
0435
0436     cfglo = channel_readl(idma64c, CFG_LO);
0437     channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
0438 }
0439
0440 static int idma64_pause(struct dma_chan *chan)
0441 {
0442     struct idma64_chan *idma64c = to_idma64_chan(chan);
0443     unsigned long flags;
0444
0445     spin_lock_irqsave(&idma64c->vchan.lock, flags);
0446     if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
0447         idma64_chan_deactivate(idma64c, false);
0448         idma64c->desc->status = DMA_PAUSED;
0449     }
0450     spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
0451
0452     return 0;
0453 }
0454
0455 static int idma64_resume(struct dma_chan *chan)
0456 {
0457     struct idma64_chan *idma64c = to_idma64_chan(chan);
0458     unsigned long flags;
0459
0460     spin_lock_irqsave(&idma64c->vchan.lock, flags);
0461     if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
0462         idma64c->desc->status = DMA_IN_PROGRESS;
0463         idma64_chan_activate(idma64c);
0464     }
0465     spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
0466
0467     return 0;
0468 }
0469
0470 static int idma64_terminate_all(struct dma_chan *chan)
0471 {
0472     struct idma64_chan *idma64c = to_idma64_chan(chan);
0473     unsigned long flags;
0474     LIST_HEAD(head);
0475
0476     spin_lock_irqsave(&idma64c->vchan.lock, flags);
0477     idma64_chan_deactivate(idma64c, true);
0478     idma64_stop_transfer(idma64c);
0479     if (idma64c->desc) {
0480         idma64_vdesc_free(&idma64c->desc->vdesc);
0481         idma64c->desc = NULL;
0482     }
0483     vchan_get_all_descriptors(&idma64c->vchan, &head);
0484     spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
0485
0486     vchan_dma_desc_free_list(&idma64c->vchan, &head);
0487     return 0;
0488 }
0489
0490 static void idma64_synchronize(struct dma_chan *chan)
0491 {
0492     struct idma64_chan *idma64c = to_idma64_chan(chan);
0493
0494     vchan_synchronize(&idma64c->vchan);
0495 }
0496
0497 static int idma64_alloc_chan_resources(struct dma_chan *chan)
0498 {
0499     struct idma64_chan *idma64c = to_idma64_chan(chan);
0500
0501     /* Create a pool of consistent memory blocks for hardware descriptors */
0502     idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
0503                     chan->device->dev,
0504                     sizeof(struct idma64_lli), 8, 0);
0505     if (!idma64c->pool) {
0506         dev_err(chan2dev(chan), "No memory for descriptors\n");
0507         return -ENOMEM;
0508     }
0509
0510     return 0;
0511 }
0512
0513 static void idma64_free_chan_resources(struct dma_chan *chan)
0514 {
0515     struct idma64_chan *idma64c = to_idma64_chan(chan);
0516
0517     vchan_free_chan_resources(to_virt_chan(chan));
0518     dma_pool_destroy(idma64c->pool);
0519     idma64c->pool = NULL;
0520 }
0521
0522 /* ---------------------------------------------------------------------- */
0523
0524 #define IDMA64_BUSWIDTHS                \
0525     BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)      |   \
0526     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)     |   \
0527     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
0528
0529 static int idma64_probe(struct idma64_chip *chip)
0530 {
0531     struct idma64 *idma64;
0532     unsigned short nr_chan = IDMA64_NR_CHAN;
0533     unsigned short i;
0534     int ret;
0535
0536     idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
0537     if (!idma64)
0538         return -ENOMEM;
0539
0540     idma64->regs = chip->regs;
0541     chip->idma64 = idma64;
0542
0543     idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
0544                     GFP_KERNEL);
0545     if (!idma64->chan)
0546         return -ENOMEM;
0547
0548     idma64->all_chan_mask = (1 << nr_chan) - 1;
0549
0550     /* Turn off iDMA controller */
0551     idma64_off(idma64);
0552
0553     ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
0554                    dev_name(chip->dev), idma64);
0555     if (ret)
0556         return ret;
0557
0558     INIT_LIST_HEAD(&idma64->dma.channels);
0559     for (i = 0; i < nr_chan; i++) {
0560         struct idma64_chan *idma64c = &idma64->chan[i];
0561
0562         idma64c->vchan.desc_free = idma64_vdesc_free;
0563         vchan_init(&idma64c->vchan, &idma64->dma);
0564
0565         idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
0566         idma64c->mask = BIT(i);
0567     }
0568
0569     dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
0570     dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
0571
0572     idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
0573     idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
0574
0575     idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
0576
0577     idma64->dma.device_issue_pending = idma64_issue_pending;
0578     idma64->dma.device_tx_status = idma64_tx_status;
0579
0580     idma64->dma.device_config = idma64_slave_config;
0581     idma64->dma.device_pause = idma64_pause;
0582     idma64->dma.device_resume = idma64_resume;
0583     idma64->dma.device_terminate_all = idma64_terminate_all;
0584     idma64->dma.device_synchronize = idma64_synchronize;
0585
0586     idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
0587     idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
0588     idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
0589     idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
0590
0591     idma64->dma.dev = chip->sysdev;
0592
0593     dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
0594
0595     ret = dma_async_device_register(&idma64->dma);
0596     if (ret)
0597         return ret;
0598
0599     dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
0600     return 0;
0601 }
0602
0603 static int idma64_remove(struct idma64_chip *chip)
0604 {
0605     struct idma64 *idma64 = chip->idma64;
0606     unsigned short i;
0607
0608     dma_async_device_unregister(&idma64->dma);
0609
0610     /*
0611      * Explicitly call devm_request_irq() to avoid the side effects with
0612      * the scheduled tasklets.
0613      */
0614     devm_free_irq(chip->dev, chip->irq, idma64);
0615
0616     for (i = 0; i < idma64->dma.chancnt; i++) {
0617         struct idma64_chan *idma64c = &idma64->chan[i];
0618
0619         tasklet_kill(&idma64c->vchan.task);
0620     }
0621
0622     return 0;
0623 }
0624
0625 /* ---------------------------------------------------------------------- */
0626
0627 static int idma64_platform_probe(struct platform_device *pdev)
0628 {
0629     struct idma64_chip *chip;
0630     struct device *dev = &pdev->dev;
0631     struct device *sysdev = dev->parent;
0632     struct resource *mem;
0633     int ret;
0634
0635     chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
0636     if (!chip)
0637         return -ENOMEM;
0638
0639     chip->irq = platform_get_irq(pdev, 0);
0640     if (chip->irq < 0)
0641         return chip->irq;
0642
0643     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0644     chip->regs = devm_ioremap_resource(dev, mem);
0645     if (IS_ERR(chip->regs))
0646         return PTR_ERR(chip->regs);
0647
0648     ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64));
0649     if (ret)
0650         return ret;
0651
0652     chip->dev = dev;
0653     chip->sysdev = sysdev;
0654
0655     ret = idma64_probe(chip);
0656     if (ret)
0657         return ret;
0658
0659     platform_set_drvdata(pdev, chip);
0660     return 0;
0661 }
0662
0663 static int idma64_platform_remove(struct platform_device *pdev)
0664 {
0665     struct idma64_chip *chip = platform_get_drvdata(pdev);
0666
0667     return idma64_remove(chip);
0668 }
0669
0670 static int __maybe_unused idma64_pm_suspend(struct device *dev)
0671 {
0672     struct idma64_chip *chip = dev_get_drvdata(dev);
0673
0674     idma64_off(chip->idma64);
0675     return 0;
0676 }
0677
0678 static int __maybe_unused idma64_pm_resume(struct device *dev)
0679 {
0680     struct idma64_chip *chip = dev_get_drvdata(dev);
0681
0682     idma64_on(chip->idma64);
0683     return 0;
0684 }
0685
0686 static const struct dev_pm_ops idma64_dev_pm_ops = {
0687     SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
0688 };
0689
0690 static struct platform_driver idma64_platform_driver = {
0691     .probe      = idma64_platform_probe,
0692     .remove     = idma64_platform_remove,
0693     .driver = {
0694         .name   = LPSS_IDMA64_DRIVER_NAME,
0695         .pm = &idma64_dev_pm_ops,
0696     },
0697 };
0698
0699 module_platform_driver(idma64_platform_driver);
0700
0701 MODULE_LICENSE("GPL v2");
0702 MODULE_DESCRIPTION("iDMA64 core driver");
0703 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
0704 MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME);