dma/hsu/hsu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Driver for the High Speed UART DMA
0004  *
0005  * Copyright (C) 2015 Intel Corporation
0006  *
0007  * Partially based on the bits found in drivers/tty/serial/mfd.c.
0008  */
0009
0010 #ifndef __DMA_HSU_H__
0011 #define __DMA_HSU_H__
0012
0013 #include <linux/spinlock.h>
0014 #include <linux/dma/hsu.h>
0015
0016 #include "../virt-dma.h"
0017
0018 #define HSU_CH_SR       0x00            /* channel status */
0019 #define HSU_CH_CR       0x04            /* channel control */
0020 #define HSU_CH_DCR      0x08            /* descriptor control */
0021 #define HSU_CH_BSR      0x10            /* FIFO buffer size */
0022 #define HSU_CH_MTSR     0x14            /* minimum transfer size */
0023 #define HSU_CH_DxSAR(x)     (0x20 + 8 * (x))    /* desc start addr */
0024 #define HSU_CH_DxTSR(x)     (0x24 + 8 * (x))    /* desc transfer size */
0025 #define HSU_CH_D0SAR        0x20            /* desc 0 start addr */
0026 #define HSU_CH_D0TSR        0x24            /* desc 0 transfer size */
0027 #define HSU_CH_D1SAR        0x28
0028 #define HSU_CH_D1TSR        0x2c
0029 #define HSU_CH_D2SAR        0x30
0030 #define HSU_CH_D2TSR        0x34
0031 #define HSU_CH_D3SAR        0x38
0032 #define HSU_CH_D3TSR        0x3c
0033
0034 #define HSU_DMA_CHAN_NR_DESC    4
0035 #define HSU_DMA_CHAN_LENGTH 0x40
0036
0037 /* Bits in HSU_CH_SR */
0038 #define HSU_CH_SR_DESCTO(x) BIT(8 + (x))
0039 #define HSU_CH_SR_DESCTO_ANY    (BIT(11) | BIT(10) | BIT(9) | BIT(8))
0040 #define HSU_CH_SR_CHE       BIT(15)
0041 #define HSU_CH_SR_DESCE(x)  BIT(16 + (x))
0042 #define HSU_CH_SR_DESCE_ANY (BIT(19) | BIT(18) | BIT(17) | BIT(16))
0043 #define HSU_CH_SR_CDESC_ANY (BIT(31) | BIT(30))
0044
0045 /* Bits in HSU_CH_CR */
0046 #define HSU_CH_CR_CHA       BIT(0)
0047 #define HSU_CH_CR_CHD       BIT(1)
0048
0049 /* Bits in HSU_CH_DCR */
0050 #define HSU_CH_DCR_DESCA(x) BIT(0 + (x))
0051 #define HSU_CH_DCR_CHSOD(x) BIT(8 + (x))
0052 #define HSU_CH_DCR_CHSOTO   BIT(14)
0053 #define HSU_CH_DCR_CHSOE    BIT(15)
0054 #define HSU_CH_DCR_CHDI(x)  BIT(16 + (x))
0055 #define HSU_CH_DCR_CHEI     BIT(23)
0056 #define HSU_CH_DCR_CHTOI(x) BIT(24 + (x))
0057
0058 /* Bits in HSU_CH_DxTSR */
0059 #define HSU_CH_DxTSR_MASK   GENMASK(15, 0)
0060 #define HSU_CH_DxTSR_TSR(x) ((x) & HSU_CH_DxTSR_MASK)
0061
0062 struct hsu_dma_sg {
0063     dma_addr_t addr;
0064     unsigned int len;
0065 };
0066
0067 struct hsu_dma_desc {
0068     struct virt_dma_desc vdesc;
0069     enum dma_transfer_direction direction;
0070     struct hsu_dma_sg *sg;
0071     unsigned int nents;
0072     size_t length;
0073     unsigned int active;
0074     enum dma_status status;
0075 };
0076
0077 static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc)
0078 {
0079     return container_of(vdesc, struct hsu_dma_desc, vdesc);
0080 }
0081
0082 struct hsu_dma_chan {
0083     struct virt_dma_chan vchan;
0084
0085     void __iomem *reg;
0086
0087     /* hardware configuration */
0088     enum dma_transfer_direction direction;
0089     struct dma_slave_config config;
0090
0091     struct hsu_dma_desc *desc;
0092 };
0093
0094 static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan)
0095 {
0096     return container_of(chan, struct hsu_dma_chan, vchan.chan);
0097 }
0098
0099 static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset)
0100 {
0101     return readl(hsuc->reg + offset);
0102 }
0103
0104 static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset,
0105                    u32 value)
0106 {
0107     writel(value, hsuc->reg + offset);
0108 }
0109
0110 struct hsu_dma {
0111     struct dma_device       dma;
0112
0113     /* channels */
0114     struct hsu_dma_chan     *chan;
0115     unsigned short          nr_channels;
0116 };
0117
0118 static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev)
0119 {
0120     return container_of(ddev, struct hsu_dma, dma);
0121 }
0122
0123 #endif /* __DMA_HSU_H__ */