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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright(c) 2019 HiSilicon Limited. */
0003 #include <linux/bitfield.h>
0004 #include <linux/dmaengine.h>
0005 #include <linux/init.h>
0006 #include <linux/iopoll.h>
0007 #include <linux/module.h>
0008 #include <linux/pci.h>
0009 #include <linux/spinlock.h>
0010 #include "virt-dma.h"
0011 
0012 #define HISI_DMA_SQ_BASE_L      0x0
0013 #define HISI_DMA_SQ_BASE_H      0x4
0014 #define HISI_DMA_SQ_DEPTH       0x8
0015 #define HISI_DMA_SQ_TAIL_PTR        0xc
0016 #define HISI_DMA_CQ_BASE_L      0x10
0017 #define HISI_DMA_CQ_BASE_H      0x14
0018 #define HISI_DMA_CQ_DEPTH       0x18
0019 #define HISI_DMA_CQ_HEAD_PTR        0x1c
0020 #define HISI_DMA_CTRL0          0x20
0021 #define HISI_DMA_CTRL0_QUEUE_EN_S   0
0022 #define HISI_DMA_CTRL0_QUEUE_PAUSE_S    4
0023 #define HISI_DMA_CTRL1          0x24
0024 #define HISI_DMA_CTRL1_QUEUE_RESET_S    0
0025 #define HISI_DMA_Q_FSM_STS      0x30
0026 #define HISI_DMA_FSM_STS_MASK       GENMASK(3, 0)
0027 #define HISI_DMA_INT_STS        0x40
0028 #define HISI_DMA_INT_STS_MASK       GENMASK(12, 0)
0029 #define HISI_DMA_INT_MSK        0x44
0030 #define HISI_DMA_MODE           0x217c
0031 #define HISI_DMA_OFFSET         0x100
0032 
0033 #define HISI_DMA_MSI_NUM        32
0034 #define HISI_DMA_CHAN_NUM       30
0035 #define HISI_DMA_Q_DEPTH_VAL        1024
0036 
0037 #define PCI_BAR_2           2
0038 
0039 enum hisi_dma_mode {
0040     EP = 0,
0041     RC,
0042 };
0043 
0044 enum hisi_dma_chan_status {
0045     DISABLE = -1,
0046     IDLE = 0,
0047     RUN,
0048     CPL,
0049     PAUSE,
0050     HALT,
0051     ABORT,
0052     WAIT,
0053     BUFFCLR,
0054 };
0055 
0056 struct hisi_dma_sqe {
0057     __le32 dw0;
0058 #define OPCODE_MASK         GENMASK(3, 0)
0059 #define OPCODE_SMALL_PACKAGE        0x1
0060 #define OPCODE_M2M          0x4
0061 #define LOCAL_IRQ_EN            BIT(8)
0062 #define ATTR_SRC_MASK           GENMASK(14, 12)
0063     __le32 dw1;
0064     __le32 dw2;
0065 #define ATTR_DST_MASK           GENMASK(26, 24)
0066     __le32 length;
0067     __le64 src_addr;
0068     __le64 dst_addr;
0069 };
0070 
0071 struct hisi_dma_cqe {
0072     __le32 rsv0;
0073     __le32 rsv1;
0074     __le16 sq_head;
0075     __le16 rsv2;
0076     __le16 rsv3;
0077     __le16 w0;
0078 #define STATUS_MASK         GENMASK(15, 1)
0079 #define STATUS_SUCC         0x0
0080 #define VALID_BIT           BIT(0)
0081 };
0082 
0083 struct hisi_dma_desc {
0084     struct virt_dma_desc vd;
0085     struct hisi_dma_sqe sqe;
0086 };
0087 
0088 struct hisi_dma_chan {
0089     struct virt_dma_chan vc;
0090     struct hisi_dma_dev *hdma_dev;
0091     struct hisi_dma_sqe *sq;
0092     struct hisi_dma_cqe *cq;
0093     dma_addr_t sq_dma;
0094     dma_addr_t cq_dma;
0095     u32 sq_tail;
0096     u32 cq_head;
0097     u32 qp_num;
0098     enum hisi_dma_chan_status status;
0099     struct hisi_dma_desc *desc;
0100 };
0101 
0102 struct hisi_dma_dev {
0103     struct pci_dev *pdev;
0104     void __iomem *base;
0105     struct dma_device dma_dev;
0106     u32 chan_num;
0107     u32 chan_depth;
0108     struct hisi_dma_chan chan[];
0109 };
0110 
0111 static inline struct hisi_dma_chan *to_hisi_dma_chan(struct dma_chan *c)
0112 {
0113     return container_of(c, struct hisi_dma_chan, vc.chan);
0114 }
0115 
0116 static inline struct hisi_dma_desc *to_hisi_dma_desc(struct virt_dma_desc *vd)
0117 {
0118     return container_of(vd, struct hisi_dma_desc, vd);
0119 }
0120 
0121 static inline void hisi_dma_chan_write(void __iomem *base, u32 reg, u32 index,
0122                        u32 val)
0123 {
0124     writel_relaxed(val, base + reg + index * HISI_DMA_OFFSET);
0125 }
0126 
0127 static inline void hisi_dma_update_bit(void __iomem *addr, u32 pos, bool val)
0128 {
0129     u32 tmp;
0130 
0131     tmp = readl_relaxed(addr);
0132     tmp = val ? tmp | BIT(pos) : tmp & ~BIT(pos);
0133     writel_relaxed(tmp, addr);
0134 }
0135 
0136 static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index,
0137                    bool pause)
0138 {
0139     void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
0140                  HISI_DMA_OFFSET;
0141 
0142     hisi_dma_update_bit(addr, HISI_DMA_CTRL0_QUEUE_PAUSE_S, pause);
0143 }
0144 
0145 static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index,
0146                 bool enable)
0147 {
0148     void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
0149                  HISI_DMA_OFFSET;
0150 
0151     hisi_dma_update_bit(addr, HISI_DMA_CTRL0_QUEUE_EN_S, enable);
0152 }
0153 
0154 static void hisi_dma_mask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
0155 {
0156     hisi_dma_chan_write(hdma_dev->base, HISI_DMA_INT_MSK, qp_index,
0157                 HISI_DMA_INT_STS_MASK);
0158 }
0159 
0160 static void hisi_dma_unmask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
0161 {
0162     void __iomem *base = hdma_dev->base;
0163 
0164     hisi_dma_chan_write(base, HISI_DMA_INT_STS, qp_index,
0165                 HISI_DMA_INT_STS_MASK);
0166     hisi_dma_chan_write(base, HISI_DMA_INT_MSK, qp_index, 0);
0167 }
0168 
0169 static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index)
0170 {
0171     void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL1 + index *
0172                  HISI_DMA_OFFSET;
0173 
0174     hisi_dma_update_bit(addr, HISI_DMA_CTRL1_QUEUE_RESET_S, 1);
0175 }
0176 
0177 static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index)
0178 {
0179     hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, index, 0);
0180     hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0);
0181 }
0182 
0183 static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan)
0184 {
0185     struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
0186     u32 index = chan->qp_num, tmp;
0187     int ret;
0188 
0189     hisi_dma_pause_dma(hdma_dev, index, true);
0190     hisi_dma_enable_dma(hdma_dev, index, false);
0191     hisi_dma_mask_irq(hdma_dev, index);
0192 
0193     ret = readl_relaxed_poll_timeout(hdma_dev->base +
0194         HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
0195         FIELD_GET(HISI_DMA_FSM_STS_MASK, tmp) != RUN, 10, 1000);
0196     if (ret) {
0197         dev_err(&hdma_dev->pdev->dev, "disable channel timeout!\n");
0198         WARN_ON(1);
0199     }
0200 
0201     hisi_dma_do_reset(hdma_dev, index);
0202     hisi_dma_reset_qp_point(hdma_dev, index);
0203     hisi_dma_pause_dma(hdma_dev, index, false);
0204     hisi_dma_enable_dma(hdma_dev, index, true);
0205     hisi_dma_unmask_irq(hdma_dev, index);
0206 
0207     ret = readl_relaxed_poll_timeout(hdma_dev->base +
0208         HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
0209         FIELD_GET(HISI_DMA_FSM_STS_MASK, tmp) == IDLE, 10, 1000);
0210     if (ret) {
0211         dev_err(&hdma_dev->pdev->dev, "reset channel timeout!\n");
0212         WARN_ON(1);
0213     }
0214 }
0215 
0216 static void hisi_dma_free_chan_resources(struct dma_chan *c)
0217 {
0218     struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
0219     struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
0220 
0221     hisi_dma_reset_hw_chan(chan);
0222     vchan_free_chan_resources(&chan->vc);
0223 
0224     memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth);
0225     memset(chan->cq, 0, sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth);
0226     chan->sq_tail = 0;
0227     chan->cq_head = 0;
0228     chan->status = DISABLE;
0229 }
0230 
0231 static void hisi_dma_desc_free(struct virt_dma_desc *vd)
0232 {
0233     kfree(to_hisi_dma_desc(vd));
0234 }
0235 
0236 static struct dma_async_tx_descriptor *
0237 hisi_dma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dst, dma_addr_t src,
0238              size_t len, unsigned long flags)
0239 {
0240     struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
0241     struct hisi_dma_desc *desc;
0242 
0243     desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
0244     if (!desc)
0245         return NULL;
0246 
0247     desc->sqe.length = cpu_to_le32(len);
0248     desc->sqe.src_addr = cpu_to_le64(src);
0249     desc->sqe.dst_addr = cpu_to_le64(dst);
0250 
0251     return vchan_tx_prep(&chan->vc, &desc->vd, flags);
0252 }
0253 
0254 static enum dma_status
0255 hisi_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
0256            struct dma_tx_state *txstate)
0257 {
0258     return dma_cookie_status(c, cookie, txstate);
0259 }
0260 
0261 static void hisi_dma_start_transfer(struct hisi_dma_chan *chan)
0262 {
0263     struct hisi_dma_sqe *sqe = chan->sq + chan->sq_tail;
0264     struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
0265     struct hisi_dma_desc *desc;
0266     struct virt_dma_desc *vd;
0267 
0268     vd = vchan_next_desc(&chan->vc);
0269     if (!vd) {
0270         dev_err(&hdma_dev->pdev->dev, "no issued task!\n");
0271         chan->desc = NULL;
0272         return;
0273     }
0274     list_del(&vd->node);
0275     desc = to_hisi_dma_desc(vd);
0276     chan->desc = desc;
0277 
0278     memcpy(sqe, &desc->sqe, sizeof(struct hisi_dma_sqe));
0279 
0280     /* update other field in sqe */
0281     sqe->dw0 = cpu_to_le32(FIELD_PREP(OPCODE_MASK, OPCODE_M2M));
0282     sqe->dw0 |= cpu_to_le32(LOCAL_IRQ_EN);
0283 
0284     /* make sure data has been updated in sqe */
0285     wmb();
0286 
0287     /* update sq tail, point to new sqe position */
0288     chan->sq_tail = (chan->sq_tail + 1) % hdma_dev->chan_depth;
0289 
0290     /* update sq_tail to trigger a new task */
0291     hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, chan->qp_num,
0292                 chan->sq_tail);
0293 }
0294 
0295 static void hisi_dma_issue_pending(struct dma_chan *c)
0296 {
0297     struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
0298     unsigned long flags;
0299 
0300     spin_lock_irqsave(&chan->vc.lock, flags);
0301 
0302     if (vchan_issue_pending(&chan->vc))
0303         hisi_dma_start_transfer(chan);
0304 
0305     spin_unlock_irqrestore(&chan->vc.lock, flags);
0306 }
0307 
0308 static int hisi_dma_terminate_all(struct dma_chan *c)
0309 {
0310     struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
0311     unsigned long flags;
0312     LIST_HEAD(head);
0313 
0314     spin_lock_irqsave(&chan->vc.lock, flags);
0315 
0316     hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, true);
0317     if (chan->desc) {
0318         vchan_terminate_vdesc(&chan->desc->vd);
0319         chan->desc = NULL;
0320     }
0321 
0322     vchan_get_all_descriptors(&chan->vc, &head);
0323 
0324     spin_unlock_irqrestore(&chan->vc.lock, flags);
0325 
0326     vchan_dma_desc_free_list(&chan->vc, &head);
0327     hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, false);
0328 
0329     return 0;
0330 }
0331 
0332 static void hisi_dma_synchronize(struct dma_chan *c)
0333 {
0334     struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
0335 
0336     vchan_synchronize(&chan->vc);
0337 }
0338 
0339 static int hisi_dma_alloc_qps_mem(struct hisi_dma_dev *hdma_dev)
0340 {
0341     size_t sq_size = sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth;
0342     size_t cq_size = sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth;
0343     struct device *dev = &hdma_dev->pdev->dev;
0344     struct hisi_dma_chan *chan;
0345     int i;
0346 
0347     for (i = 0; i < hdma_dev->chan_num; i++) {
0348         chan = &hdma_dev->chan[i];
0349         chan->sq = dmam_alloc_coherent(dev, sq_size, &chan->sq_dma,
0350                            GFP_KERNEL);
0351         if (!chan->sq)
0352             return -ENOMEM;
0353 
0354         chan->cq = dmam_alloc_coherent(dev, cq_size, &chan->cq_dma,
0355                            GFP_KERNEL);
0356         if (!chan->cq)
0357             return -ENOMEM;
0358     }
0359 
0360     return 0;
0361 }
0362 
0363 static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index)
0364 {
0365     struct hisi_dma_chan *chan = &hdma_dev->chan[index];
0366     u32 hw_depth = hdma_dev->chan_depth - 1;
0367     void __iomem *base = hdma_dev->base;
0368 
0369     /* set sq, cq base */
0370     hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_L, index,
0371                 lower_32_bits(chan->sq_dma));
0372     hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_H, index,
0373                 upper_32_bits(chan->sq_dma));
0374     hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_L, index,
0375                 lower_32_bits(chan->cq_dma));
0376     hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_H, index,
0377                 upper_32_bits(chan->cq_dma));
0378 
0379     /* set sq, cq depth */
0380     hisi_dma_chan_write(base, HISI_DMA_SQ_DEPTH, index, hw_depth);
0381     hisi_dma_chan_write(base, HISI_DMA_CQ_DEPTH, index, hw_depth);
0382 
0383     /* init sq tail and cq head */
0384     hisi_dma_chan_write(base, HISI_DMA_SQ_TAIL_PTR, index, 0);
0385     hisi_dma_chan_write(base, HISI_DMA_CQ_HEAD_PTR, index, 0);
0386 }
0387 
0388 static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
0389 {
0390     hisi_dma_init_hw_qp(hdma_dev, qp_index);
0391     hisi_dma_unmask_irq(hdma_dev, qp_index);
0392     hisi_dma_enable_dma(hdma_dev, qp_index, true);
0393 }
0394 
0395 static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
0396 {
0397     hisi_dma_reset_hw_chan(&hdma_dev->chan[qp_index]);
0398 }
0399 
0400 static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev)
0401 {
0402     int i;
0403 
0404     for (i = 0; i < hdma_dev->chan_num; i++) {
0405         hdma_dev->chan[i].qp_num = i;
0406         hdma_dev->chan[i].hdma_dev = hdma_dev;
0407         hdma_dev->chan[i].vc.desc_free = hisi_dma_desc_free;
0408         vchan_init(&hdma_dev->chan[i].vc, &hdma_dev->dma_dev);
0409         hisi_dma_enable_qp(hdma_dev, i);
0410     }
0411 }
0412 
0413 static void hisi_dma_disable_qps(struct hisi_dma_dev *hdma_dev)
0414 {
0415     int i;
0416 
0417     for (i = 0; i < hdma_dev->chan_num; i++) {
0418         hisi_dma_disable_qp(hdma_dev, i);
0419         tasklet_kill(&hdma_dev->chan[i].vc.task);
0420     }
0421 }
0422 
0423 static irqreturn_t hisi_dma_irq(int irq, void *data)
0424 {
0425     struct hisi_dma_chan *chan = data;
0426     struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
0427     struct hisi_dma_desc *desc;
0428     struct hisi_dma_cqe *cqe;
0429 
0430     spin_lock(&chan->vc.lock);
0431 
0432     desc = chan->desc;
0433     cqe = chan->cq + chan->cq_head;
0434     if (desc) {
0435         if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) {
0436             chan->cq_head = (chan->cq_head + 1) %
0437                     hdma_dev->chan_depth;
0438             hisi_dma_chan_write(hdma_dev->base,
0439                         HISI_DMA_CQ_HEAD_PTR, chan->qp_num,
0440                         chan->cq_head);
0441             vchan_cookie_complete(&desc->vd);
0442         } else {
0443             dev_err(&hdma_dev->pdev->dev, "task error!\n");
0444         }
0445 
0446         chan->desc = NULL;
0447     }
0448 
0449     spin_unlock(&chan->vc.lock);
0450 
0451     return IRQ_HANDLED;
0452 }
0453 
0454 static int hisi_dma_request_qps_irq(struct hisi_dma_dev *hdma_dev)
0455 {
0456     struct pci_dev *pdev = hdma_dev->pdev;
0457     int i, ret;
0458 
0459     for (i = 0; i < hdma_dev->chan_num; i++) {
0460         ret = devm_request_irq(&pdev->dev, pci_irq_vector(pdev, i),
0461                        hisi_dma_irq, IRQF_SHARED, "hisi_dma",
0462                        &hdma_dev->chan[i]);
0463         if (ret)
0464             return ret;
0465     }
0466 
0467     return 0;
0468 }
0469 
0470 /* This function enables all hw channels in a device */
0471 static int hisi_dma_enable_hw_channels(struct hisi_dma_dev *hdma_dev)
0472 {
0473     int ret;
0474 
0475     ret = hisi_dma_alloc_qps_mem(hdma_dev);
0476     if (ret) {
0477         dev_err(&hdma_dev->pdev->dev, "fail to allocate qp memory!\n");
0478         return ret;
0479     }
0480 
0481     ret = hisi_dma_request_qps_irq(hdma_dev);
0482     if (ret) {
0483         dev_err(&hdma_dev->pdev->dev, "fail to request qp irq!\n");
0484         return ret;
0485     }
0486 
0487     hisi_dma_enable_qps(hdma_dev);
0488 
0489     return 0;
0490 }
0491 
0492 static void hisi_dma_disable_hw_channels(void *data)
0493 {
0494     hisi_dma_disable_qps(data);
0495 }
0496 
0497 static void hisi_dma_set_mode(struct hisi_dma_dev *hdma_dev,
0498                   enum hisi_dma_mode mode)
0499 {
0500     writel_relaxed(mode == RC ? 1 : 0, hdma_dev->base + HISI_DMA_MODE);
0501 }
0502 
0503 static int hisi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id)
0504 {
0505     struct device *dev = &pdev->dev;
0506     struct hisi_dma_dev *hdma_dev;
0507     struct dma_device *dma_dev;
0508     int ret;
0509 
0510     ret = pcim_enable_device(pdev);
0511     if (ret) {
0512         dev_err(dev, "failed to enable device mem!\n");
0513         return ret;
0514     }
0515 
0516     ret = pcim_iomap_regions(pdev, 1 << PCI_BAR_2, pci_name(pdev));
0517     if (ret) {
0518         dev_err(dev, "failed to remap I/O region!\n");
0519         return ret;
0520     }
0521 
0522     ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0523     if (ret)
0524         return ret;
0525 
0526     hdma_dev = devm_kzalloc(dev, struct_size(hdma_dev, chan, HISI_DMA_CHAN_NUM), GFP_KERNEL);
0527     if (!hdma_dev)
0528         return -EINVAL;
0529 
0530     hdma_dev->base = pcim_iomap_table(pdev)[PCI_BAR_2];
0531     hdma_dev->pdev = pdev;
0532     hdma_dev->chan_num = HISI_DMA_CHAN_NUM;
0533     hdma_dev->chan_depth = HISI_DMA_Q_DEPTH_VAL;
0534 
0535     pci_set_drvdata(pdev, hdma_dev);
0536     pci_set_master(pdev);
0537 
0538     /* This will be freed by 'pcim_release()'. See 'pcim_enable_device()' */
0539     ret = pci_alloc_irq_vectors(pdev, HISI_DMA_MSI_NUM, HISI_DMA_MSI_NUM,
0540                     PCI_IRQ_MSI);
0541     if (ret < 0) {
0542         dev_err(dev, "Failed to allocate MSI vectors!\n");
0543         return ret;
0544     }
0545 
0546     dma_dev = &hdma_dev->dma_dev;
0547     dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
0548     dma_dev->device_free_chan_resources = hisi_dma_free_chan_resources;
0549     dma_dev->device_prep_dma_memcpy = hisi_dma_prep_dma_memcpy;
0550     dma_dev->device_tx_status = hisi_dma_tx_status;
0551     dma_dev->device_issue_pending = hisi_dma_issue_pending;
0552     dma_dev->device_terminate_all = hisi_dma_terminate_all;
0553     dma_dev->device_synchronize = hisi_dma_synchronize;
0554     dma_dev->directions = BIT(DMA_MEM_TO_MEM);
0555     dma_dev->dev = dev;
0556     INIT_LIST_HEAD(&dma_dev->channels);
0557 
0558     hisi_dma_set_mode(hdma_dev, RC);
0559 
0560     ret = hisi_dma_enable_hw_channels(hdma_dev);
0561     if (ret < 0) {
0562         dev_err(dev, "failed to enable hw channel!\n");
0563         return ret;
0564     }
0565 
0566     ret = devm_add_action_or_reset(dev, hisi_dma_disable_hw_channels,
0567                        hdma_dev);
0568     if (ret)
0569         return ret;
0570 
0571     ret = dmaenginem_async_device_register(dma_dev);
0572     if (ret < 0)
0573         dev_err(dev, "failed to register device!\n");
0574 
0575     return ret;
0576 }
0577 
0578 static const struct pci_device_id hisi_dma_pci_tbl[] = {
0579     { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa122) },
0580     { 0, }
0581 };
0582 
0583 static struct pci_driver hisi_dma_pci_driver = {
0584     .name       = "hisi_dma",
0585     .id_table   = hisi_dma_pci_tbl,
0586     .probe      = hisi_dma_probe,
0587 };
0588 
0589 module_pci_driver(hisi_dma_pci_driver);
0590 
0591 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
0592 MODULE_AUTHOR("Zhenfa Qiu <qiuzhenfa@hisilicon.com>");
0593 MODULE_DESCRIPTION("HiSilicon Kunpeng DMA controller driver");
0594 MODULE_LICENSE("GPL v2");
0595 MODULE_DEVICE_TABLE(pci, hisi_dma_pci_tbl);
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