drivers/dma/fsldma.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
0004  *
0005  * Author:
0006  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
0007  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
0008  */
0009 #ifndef __DMA_FSLDMA_H
0010 #define __DMA_FSLDMA_H
0011
0012 #include <linux/device.h>
0013 #include <linux/dmapool.h>
0014 #include <linux/dmaengine.h>
0015
0016 /* Define data structures needed by Freescale
0017  * MPC8540 and MPC8349 DMA controller.
0018  */
0019 #define FSL_DMA_MR_CS       0x00000001
0020 #define FSL_DMA_MR_CC       0x00000002
0021 #define FSL_DMA_MR_CA       0x00000008
0022 #define FSL_DMA_MR_EIE      0x00000040
0023 #define FSL_DMA_MR_XFE      0x00000020
0024 #define FSL_DMA_MR_EOLNIE   0x00000100
0025 #define FSL_DMA_MR_EOLSIE   0x00000080
0026 #define FSL_DMA_MR_EOSIE    0x00000200
0027 #define FSL_DMA_MR_CDSM     0x00000010
0028 #define FSL_DMA_MR_CTM      0x00000004
0029 #define FSL_DMA_MR_EMP_EN   0x00200000
0030 #define FSL_DMA_MR_EMS_EN   0x00040000
0031 #define FSL_DMA_MR_DAHE     0x00002000
0032 #define FSL_DMA_MR_SAHE     0x00001000
0033
0034 #define FSL_DMA_MR_SAHTS_MASK   0x0000C000
0035 #define FSL_DMA_MR_DAHTS_MASK   0x00030000
0036 #define FSL_DMA_MR_BWC_MASK 0x0f000000
0037
0038 /*
0039  * Bandwidth/pause control determines how many bytes a given
0040  * channel is allowed to transfer before the DMA engine pauses
0041  * the current channel and switches to the next channel
0042  */
0043 #define FSL_DMA_MR_BWC         0x0A000000
0044
0045 /* Special MR definition for MPC8349 */
0046 #define FSL_DMA_MR_EOTIE    0x00000080
0047 #define FSL_DMA_MR_PRC_RM   0x00000800
0048
0049 #define FSL_DMA_SR_CH       0x00000020
0050 #define FSL_DMA_SR_PE       0x00000010
0051 #define FSL_DMA_SR_CB       0x00000004
0052 #define FSL_DMA_SR_TE       0x00000080
0053 #define FSL_DMA_SR_EOSI     0x00000002
0054 #define FSL_DMA_SR_EOLSI    0x00000001
0055 #define FSL_DMA_SR_EOCDI    0x00000001
0056 #define FSL_DMA_SR_EOLNI    0x00000008
0057
0058 #define FSL_DMA_SATR_SBPATMU            0x20000000
0059 #define FSL_DMA_SATR_STRANSINT_RIO      0x00c00000
0060 #define FSL_DMA_SATR_SREADTYPE_SNOOP_READ   0x00050000
0061 #define FSL_DMA_SATR_SREADTYPE_BP_IORH      0x00020000
0062 #define FSL_DMA_SATR_SREADTYPE_BP_NREAD     0x00040000
0063 #define FSL_DMA_SATR_SREADTYPE_BP_MREAD     0x00070000
0064
0065 #define FSL_DMA_DATR_DBPATMU            0x20000000
0066 #define FSL_DMA_DATR_DTRANSINT_RIO      0x00c00000
0067 #define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
0068 #define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH    0x00010000
0069
0070 #define FSL_DMA_EOL     ((u64)0x1)
0071 #define FSL_DMA_SNEN        ((u64)0x10)
0072 #define FSL_DMA_EOSIE       0x8
0073 #define FSL_DMA_NLDA_MASK   (~(u64)0x1f)
0074
0075 #define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
0076
0077 #define FSL_DMA_DGSR_TE     0x80
0078 #define FSL_DMA_DGSR_CH     0x20
0079 #define FSL_DMA_DGSR_PE     0x10
0080 #define FSL_DMA_DGSR_EOLNI  0x08
0081 #define FSL_DMA_DGSR_CB     0x04
0082 #define FSL_DMA_DGSR_EOSI   0x02
0083 #define FSL_DMA_DGSR_EOLSI  0x01
0084
0085 #define FSL_DMA_BUSWIDTHS   (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
0086                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
0087                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
0088                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
0089 typedef u64 __bitwise v64;
0090 typedef u32 __bitwise v32;
0091
0092 struct fsl_dma_ld_hw {
0093     v64 src_addr;
0094     v64 dst_addr;
0095     v64 next_ln_addr;
0096     v32 count;
0097     v32 reserve;
0098 } __attribute__((aligned(32)));
0099
0100 struct fsl_desc_sw {
0101     struct fsl_dma_ld_hw hw;
0102     struct list_head node;
0103     struct list_head tx_list;
0104     struct dma_async_tx_descriptor async_tx;
0105 } __attribute__((aligned(32)));
0106
0107 struct fsldma_chan_regs {
0108     u32 mr;     /* 0x00 - Mode Register */
0109     u32 sr;     /* 0x04 - Status Register */
0110     u64 cdar;   /* 0x08 - Current descriptor address register */
0111     u64 sar;    /* 0x10 - Source Address Register */
0112     u64 dar;    /* 0x18 - Destination Address Register */
0113     u32 bcr;    /* 0x20 - Byte Count Register */
0114     u64 ndar;   /* 0x24 - Next Descriptor Address Register */
0115 };
0116
0117 struct fsldma_chan;
0118 #define FSL_DMA_MAX_CHANS_PER_DEVICE 8
0119
0120 struct fsldma_device {
0121     void __iomem *regs; /* DGSR register base */
0122     struct device *dev;
0123     struct dma_device common;
0124     struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
0125     u32 feature;        /* The same as DMA channels */
0126     int irq;        /* Channel IRQ */
0127 };
0128
0129 /* Define macros for fsldma_chan->feature property */
0130 #define FSL_DMA_LITTLE_ENDIAN   0x00000000
0131 #define FSL_DMA_BIG_ENDIAN  0x00000001
0132
0133 #define FSL_DMA_IP_MASK     0x00000ff0
0134 #define FSL_DMA_IP_85XX     0x00000010
0135 #define FSL_DMA_IP_83XX     0x00000020
0136
0137 #define FSL_DMA_CHAN_PAUSE_EXT  0x00001000
0138 #define FSL_DMA_CHAN_START_EXT  0x00002000
0139
0140 #ifdef CONFIG_PM
0141 struct fsldma_chan_regs_save {
0142     u32 mr;
0143 };
0144
0145 enum fsldma_pm_state {
0146     RUNNING = 0,
0147     SUSPENDED,
0148 };
0149 #endif
0150
0151 struct fsldma_chan {
0152     char name[8];           /* Channel name */
0153     struct fsldma_chan_regs __iomem *regs;
0154     spinlock_t desc_lock;       /* Descriptor operation lock */
0155     /*
0156      * Descriptors which are queued to run, but have not yet been
0157      * submitted to the hardware for execution
0158      */
0159     struct list_head ld_pending;
0160     /*
0161      * Descriptors which are currently being executed by the hardware
0162      */
0163     struct list_head ld_running;
0164     /*
0165      * Descriptors which have finished execution by the hardware. These
0166      * descriptors have already had their cleanup actions run. They are
0167      * waiting for the ACK bit to be set by the async_tx API.
0168      */
0169     struct list_head ld_completed;  /* Link descriptors queue */
0170     struct dma_chan common;     /* DMA common channel */
0171     struct dma_pool *desc_pool; /* Descriptors pool */
0172     struct device *dev;     /* Channel device */
0173     int irq;            /* Channel IRQ */
0174     int id;             /* Raw id of this channel */
0175     struct tasklet_struct tasklet;
0176     u32 feature;
0177     bool idle;          /* DMA controller is idle */
0178 #ifdef CONFIG_PM
0179     struct fsldma_chan_regs_save regs_save;
0180     enum fsldma_pm_state pm_state;
0181 #endif
0182
0183     void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
0184     void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
0185     void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
0186     void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
0187     void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
0188 };
0189
0190 #define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
0191 #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
0192 #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
0193
0194 #ifdef  CONFIG_PPC
0195 #define fsl_ioread32(p)     in_le32(p)
0196 #define fsl_ioread32be(p)   in_be32(p)
0197 #define fsl_iowrite32(v, p) out_le32(p, v)
0198 #define fsl_iowrite32be(v, p)   out_be32(p, v)
0199
0200 #ifdef __powerpc64__
0201 #define fsl_ioread64(p)     in_le64(p)
0202 #define fsl_ioread64be(p)   in_be64(p)
0203 #define fsl_iowrite64(v, p) out_le64(p, v)
0204 #define fsl_iowrite64be(v, p)   out_be64(p, v)
0205 #else
0206 static u64 fsl_ioread64(const u64 __iomem *addr)
0207 {
0208     u32 val_lo = in_le32((u32 __iomem *)addr);
0209     u32 val_hi = in_le32((u32 __iomem *)addr + 1);
0210
0211     return ((u64)val_hi << 32) + val_lo;
0212 }
0213
0214 static void fsl_iowrite64(u64 val, u64 __iomem *addr)
0215 {
0216     out_le32((u32 __iomem *)addr + 1, val >> 32);
0217     out_le32((u32 __iomem *)addr, (u32)val);
0218 }
0219
0220 static u64 fsl_ioread64be(const u64 __iomem *addr)
0221 {
0222     u32 val_hi = in_be32((u32 __iomem *)addr);
0223     u32 val_lo = in_be32((u32 __iomem *)addr + 1);
0224
0225     return ((u64)val_hi << 32) + val_lo;
0226 }
0227
0228 static void fsl_iowrite64be(u64 val, u64 __iomem *addr)
0229 {
0230     out_be32((u32 __iomem *)addr, val >> 32);
0231     out_be32((u32 __iomem *)addr + 1, (u32)val);
0232 }
0233 #endif
0234 #endif
0235
0236 #if defined(CONFIG_ARM64) || defined(CONFIG_ARM)
0237 #define fsl_ioread32(p)     ioread32(p)
0238 #define fsl_ioread32be(p)   ioread32be(p)
0239 #define fsl_iowrite32(v, p) iowrite32(v, p)
0240 #define fsl_iowrite32be(v, p)   iowrite32be(v, p)
0241 #define fsl_ioread64(p)     ioread64(p)
0242 #define fsl_ioread64be(p)   ioread64be(p)
0243 #define fsl_iowrite64(v, p) iowrite64(v, p)
0244 #define fsl_iowrite64be(v, p)   iowrite64be(v, p)
0245 #endif
0246
0247 #define FSL_DMA_IN(fsl_dma, addr, width)            \
0248         (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ?    \
0249             fsl_ioread##width##be(addr) : fsl_ioread##width(addr))
0250
0251 #define FSL_DMA_OUT(fsl_dma, addr, val, width)          \
0252         (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ?    \
0253             fsl_iowrite##width##be(val, addr) : fsl_iowrite \
0254         ##width(val, addr))
0255
0256 #define DMA_TO_CPU(fsl_chan, d, width)                  \
0257         (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?       \
0258             be##width##_to_cpu((__force __be##width)(v##width)d) : \
0259             le##width##_to_cpu((__force __le##width)(v##width)d))
0260 #define CPU_TO_DMA(fsl_chan, c, width)                  \
0261         (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?       \
0262             (__force v##width)cpu_to_be##width(c) :     \
0263             (__force v##width)cpu_to_le##width(c))
0264
0265 #endif  /* __DMA_FSLDMA_H */