drivers/dma/fsl_raid.h

0001 /*
0002  * drivers/dma/fsl_raid.h
0003  *
0004  * Freescale RAID Engine device driver
0005  *
0006  * Author:
0007  *  Harninder Rai <harninder.rai@freescale.com>
0008  *  Naveen Burmi <naveenburmi@freescale.com>
0009  *
0010  * Rewrite:
0011  *  Xuelin Shi <xuelin.shi@freescale.com>
0012
0013  * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions are met:
0017  *     * Redistributions of source code must retain the above copyright
0018  *       notice, this list of conditions and the following disclaimer.
0019  *     * Redistributions in binary form must reproduce the above copyright
0020  *       notice, this list of conditions and the following disclaimer in the
0021  *       documentation and/or other materials provided with the distribution.
0022  *     * Neither the name of Freescale Semiconductor nor the
0023  *       names of its contributors may be used to endorse or promote products
0024  *       derived from this software without specific prior written permission.
0025  *
0026  * ALTERNATIVELY, this software may be distributed under the terms of the
0027  * GNU General Public License ("GPL") as published by the Free Software
0028  * Foundation, either version 2 of that License or (at your option) any
0029  * later version.
0030  *
0031  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0032  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0033  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0034  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0035  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0036  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0037  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0038  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0039  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0040  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0041  *
0042  */
0043
0044 #define FSL_RE_MAX_CHANS        4
0045 #define FSL_RE_DPAA_MODE        BIT(30)
0046 #define FSL_RE_NON_DPAA_MODE        BIT(31)
0047 #define FSL_RE_GFM_POLY         0x1d000000
0048 #define FSL_RE_ADD_JOB(x)       ((x) << 16)
0049 #define FSL_RE_RMVD_JOB(x)      ((x) << 16)
0050 #define FSL_RE_CFG1_CBSI        0x08000000
0051 #define FSL_RE_CFG1_CBS0        0x00080000
0052 #define FSL_RE_SLOT_FULL_SHIFT      8
0053 #define FSL_RE_SLOT_FULL(x)     ((x) >> FSL_RE_SLOT_FULL_SHIFT)
0054 #define FSL_RE_SLOT_AVAIL_SHIFT     8
0055 #define FSL_RE_SLOT_AVAIL(x)        ((x) >> FSL_RE_SLOT_AVAIL_SHIFT)
0056 #define FSL_RE_PQ_OPCODE        0x1B
0057 #define FSL_RE_XOR_OPCODE       0x1A
0058 #define FSL_RE_MOVE_OPCODE      0x8
0059 #define FSL_RE_FRAME_ALIGN      16
0060 #define FSL_RE_BLOCK_SIZE       0x3 /* 4096 bytes */
0061 #define FSL_RE_CACHEABLE_IO     0x0
0062 #define FSL_RE_BUFFER_OUTPUT        0x0
0063 #define FSL_RE_INTR_ON_ERROR        0x1
0064 #define FSL_RE_DATA_DEP         0x1
0065 #define FSL_RE_ENABLE_DPI       0x0
0066 #define FSL_RE_RING_SIZE        0x400
0067 #define FSL_RE_RING_SIZE_MASK       (FSL_RE_RING_SIZE - 1)
0068 #define FSL_RE_RING_SIZE_SHIFT      8
0069 #define FSL_RE_ADDR_BIT_SHIFT       4
0070 #define FSL_RE_ADDR_BIT_MASK        (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1)
0071 #define FSL_RE_ERROR            0x40000000
0072 #define FSL_RE_INTR         0x80000000
0073 #define FSL_RE_CLR_INTR         0x80000000
0074 #define FSL_RE_PAUSE            0x80000000
0075 #define FSL_RE_ENABLE           0x80000000
0076 #define FSL_RE_REG_LIODN_MASK       0x00000FFF
0077
0078 #define FSL_RE_CDB_OPCODE_MASK      0xF8000000
0079 #define FSL_RE_CDB_OPCODE_SHIFT     27
0080 #define FSL_RE_CDB_EXCLEN_MASK      0x03000000
0081 #define FSL_RE_CDB_EXCLEN_SHIFT     24
0082 #define FSL_RE_CDB_EXCLQ1_MASK      0x00F00000
0083 #define FSL_RE_CDB_EXCLQ1_SHIFT     20
0084 #define FSL_RE_CDB_EXCLQ2_MASK      0x000F0000
0085 #define FSL_RE_CDB_EXCLQ2_SHIFT     16
0086 #define FSL_RE_CDB_BLKSIZE_MASK     0x0000C000
0087 #define FSL_RE_CDB_BLKSIZE_SHIFT    14
0088 #define FSL_RE_CDB_CACHE_MASK       0x00003000
0089 #define FSL_RE_CDB_CACHE_SHIFT      12
0090 #define FSL_RE_CDB_BUFFER_MASK      0x00000800
0091 #define FSL_RE_CDB_BUFFER_SHIFT     11
0092 #define FSL_RE_CDB_ERROR_MASK       0x00000400
0093 #define FSL_RE_CDB_ERROR_SHIFT      10
0094 #define FSL_RE_CDB_NRCS_MASK        0x0000003C
0095 #define FSL_RE_CDB_NRCS_SHIFT       6
0096 #define FSL_RE_CDB_DEPEND_MASK      0x00000008
0097 #define FSL_RE_CDB_DEPEND_SHIFT     3
0098 #define FSL_RE_CDB_DPI_MASK     0x00000004
0099 #define FSL_RE_CDB_DPI_SHIFT        2
0100
0101 /*
0102  * the largest cf block is 19*sizeof(struct cmpnd_frame), which is 304 bytes.
0103  * here 19 = 1(cdb)+2(dest)+16(src), align to 64bytes, that is 320 bytes.
0104  * the largest cdb block: struct pq_cdb which is 180 bytes, adding to cf block
0105  * 320+180=500, align to 64bytes, that is 512 bytes.
0106  */
0107 #define FSL_RE_CF_DESC_SIZE     320
0108 #define FSL_RE_CF_CDB_SIZE      512
0109 #define FSL_RE_CF_CDB_ALIGN     64
0110
0111 struct fsl_re_ctrl {
0112     /* General Configuration Registers */
0113     __be32 global_config;   /* Global Configuration Register */
0114     u8     rsvd1[4];
0115     __be32 galois_field_config; /* Galois Field Configuration Register */
0116     u8     rsvd2[4];
0117     __be32 jq_wrr_config;   /* WRR Configuration register */
0118     u8     rsvd3[4];
0119     __be32 crc_config;  /* CRC Configuration register */
0120     u8     rsvd4[228];
0121     __be32 system_reset;    /* System Reset Register */
0122     u8     rsvd5[252];
0123     __be32 global_status;   /* Global Status Register */
0124     u8     rsvd6[832];
0125     __be32 re_liodn_base;   /* LIODN Base Register */
0126     u8     rsvd7[1712];
0127     __be32 re_version_id;   /* Version ID register of RE */
0128     __be32 re_version_id_2; /* Version ID 2 register of RE */
0129     u8     rsvd8[512];
0130     __be32 host_config; /* Host I/F Configuration Register */
0131 };
0132
0133 struct fsl_re_chan_cfg {
0134     /* Registers for JR interface */
0135     __be32 jr_config_0; /* Job Queue Configuration 0 Register */
0136     __be32 jr_config_1; /* Job Queue Configuration 1 Register */
0137     __be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */
0138     u8     rsvd1[4];
0139     __be32 jr_command;  /* Job Queue Command Register */
0140     u8     rsvd2[4];
0141     __be32 jr_status;   /* Job Queue Status Register */
0142     u8     rsvd3[228];
0143
0144     /* Input Ring */
0145     __be32 inbring_base_h;  /* Inbound Ring Base Address Register - High */
0146     __be32 inbring_base_l;  /* Inbound Ring Base Address Register - Low */
0147     __be32 inbring_size;    /* Inbound Ring Size Register */
0148     u8     rsvd4[4];
0149     __be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */
0150     u8     rsvd5[4];
0151     __be32 inbring_add_job; /* Inbound Ring Add Job Register */
0152     u8     rsvd6[4];
0153     __be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */
0154     u8     rsvd7[220];
0155
0156     /* Output Ring */
0157     __be32 oubring_base_h;  /* Outbound Ring Base Address Register - High */
0158     __be32 oubring_base_l;  /* Outbound Ring Base Address Register - Low */
0159     __be32 oubring_size;    /* Outbound Ring Size Register */
0160     u8     rsvd8[4];
0161     __be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */
0162     u8     rsvd9[4];
0163     __be32 oubring_slot_full; /* Outbound Ring Slot Full Register */
0164     u8     rsvd10[4];
0165     __be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */
0166 };
0167
0168 /*
0169  * Command Descriptor Block (CDB) for unicast move command.
0170  * In RAID Engine terms, memcpy is done through move command
0171  */
0172 struct fsl_re_move_cdb {
0173     __be32 cdb32;
0174 };
0175
0176 /* Data protection/integrity related fields */
0177 #define FSL_RE_DPI_APPS_MASK        0xC0000000
0178 #define FSL_RE_DPI_APPS_SHIFT       30
0179 #define FSL_RE_DPI_REF_MASK     0x30000000
0180 #define FSL_RE_DPI_REF_SHIFT        28
0181 #define FSL_RE_DPI_GUARD_MASK       0x0C000000
0182 #define FSL_RE_DPI_GUARD_SHIFT      26
0183 #define FSL_RE_DPI_ATTR_MASK        0x03000000
0184 #define FSL_RE_DPI_ATTR_SHIFT       24
0185 #define FSL_RE_DPI_META_MASK        0x0000FFFF
0186
0187 struct fsl_re_dpi {
0188     __be32 dpi32;
0189     __be32 ref;
0190 };
0191
0192 /*
0193  * CDB for GenQ command. In RAID Engine terminology, XOR is
0194  * done through this command
0195  */
0196 struct fsl_re_xor_cdb {
0197     __be32 cdb32;
0198     u8 gfm[16];
0199     struct fsl_re_dpi dpi_dest_spec;
0200     struct fsl_re_dpi dpi_src_spec[16];
0201 };
0202
0203 /* CDB for no-op command */
0204 struct fsl_re_noop_cdb {
0205     __be32 cdb32;
0206 };
0207
0208 /*
0209  * CDB for GenQQ command. In RAID Engine terminology, P/Q is
0210  * done through this command
0211  */
0212 struct fsl_re_pq_cdb {
0213     __be32 cdb32;
0214     u8 gfm_q1[16];
0215     u8 gfm_q2[16];
0216     struct fsl_re_dpi dpi_dest_spec[2];
0217     struct fsl_re_dpi dpi_src_spec[16];
0218 };
0219
0220 /* Compound frame */
0221 #define FSL_RE_CF_ADDR_HIGH_MASK    0x000000FF
0222 #define FSL_RE_CF_EXT_MASK      0x80000000
0223 #define FSL_RE_CF_EXT_SHIFT     31
0224 #define FSL_RE_CF_FINAL_MASK        0x40000000
0225 #define FSL_RE_CF_FINAL_SHIFT       30
0226 #define FSL_RE_CF_LENGTH_MASK       0x000FFFFF
0227 #define FSL_RE_CF_BPID_MASK     0x00FF0000
0228 #define FSL_RE_CF_BPID_SHIFT        16
0229 #define FSL_RE_CF_OFFSET_MASK       0x00001FFF
0230
0231 struct fsl_re_cmpnd_frame {
0232     __be32 addr_high;
0233     __be32 addr_low;
0234     __be32 efrl32;
0235     __be32 rbro32;
0236 };
0237
0238 /* Frame descriptor */
0239 #define FSL_RE_HWDESC_LIODN_MASK    0x3F000000
0240 #define FSL_RE_HWDESC_LIODN_SHIFT   24
0241 #define FSL_RE_HWDESC_BPID_MASK     0x00FF0000
0242 #define FSL_RE_HWDESC_BPID_SHIFT    16
0243 #define FSL_RE_HWDESC_ELIODN_MASK   0x0000F000
0244 #define FSL_RE_HWDESC_ELIODN_SHIFT  12
0245 #define FSL_RE_HWDESC_FMT_SHIFT     29
0246 #define FSL_RE_HWDESC_FMT_MASK      (0x3 << FSL_RE_HWDESC_FMT_SHIFT)
0247
0248 struct fsl_re_hw_desc {
0249     __be32 lbea32;
0250     __be32 addr_low;
0251     __be32 fmt32;
0252     __be32 status;
0253 };
0254
0255 /* Raid Engine device private data */
0256 struct fsl_re_drv_private {
0257     u8 total_chans;
0258     struct dma_device dma_dev;
0259     struct fsl_re_ctrl *re_regs;
0260     struct fsl_re_chan *re_jrs[FSL_RE_MAX_CHANS];
0261     struct dma_pool *cf_desc_pool;
0262     struct dma_pool *hw_desc_pool;
0263 };
0264
0265 /* Per job ring data structure */
0266 struct fsl_re_chan {
0267     char name[16];
0268     spinlock_t desc_lock; /* queue lock */
0269     struct list_head ack_q;  /* wait to acked queue */
0270     struct list_head active_q; /* already issued on hw, not completed */
0271     struct list_head submit_q;
0272     struct list_head free_q; /* alloc available queue */
0273     struct device *dev;
0274     struct fsl_re_drv_private *re_dev;
0275     struct dma_chan chan;
0276     struct fsl_re_chan_cfg *jrregs;
0277     int irq;
0278     struct tasklet_struct irqtask;
0279     u32 alloc_count;
0280
0281     /* hw descriptor ring for inbound queue*/
0282     dma_addr_t inb_phys_addr;
0283     struct fsl_re_hw_desc *inb_ring_virt_addr;
0284     u32 inb_count;
0285
0286     /* hw descriptor ring for outbound queue */
0287     dma_addr_t oub_phys_addr;
0288     struct fsl_re_hw_desc *oub_ring_virt_addr;
0289     u32 oub_count;
0290 };
0291
0292 /* Async transaction descriptor */
0293 struct fsl_re_desc {
0294     struct dma_async_tx_descriptor async_tx;
0295     struct list_head node;
0296     struct fsl_re_hw_desc hwdesc;
0297     struct fsl_re_chan *re_chan;
0298
0299     /* hwdesc will point to cf_addr */
0300     void *cf_addr;
0301     dma_addr_t cf_paddr;
0302
0303     void *cdb_addr;
0304     dma_addr_t cdb_paddr;
0305     int status;
0306 };