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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * drivers/dma/fsl-edma.c
0004  *
0005  * Copyright 2013-2014 Freescale Semiconductor, Inc.
0006  *
0007  * Driver for the Freescale eDMA engine with flexible channel multiplexing
0008  * capability for DMA request sources. The eDMA block can be found on some
0009  * Vybrid and Layerscape SoCs.
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/clk.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_dma.h>
0020 #include <linux/dma-mapping.h>
0021 
0022 #include "fsl-edma-common.h"
0023 
0024 static void fsl_edma_synchronize(struct dma_chan *chan)
0025 {
0026     struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
0027 
0028     vchan_synchronize(&fsl_chan->vchan);
0029 }
0030 
0031 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
0032 {
0033     struct fsl_edma_engine *fsl_edma = dev_id;
0034     unsigned int intr, ch;
0035     struct edma_regs *regs = &fsl_edma->regs;
0036     struct fsl_edma_chan *fsl_chan;
0037 
0038     intr = edma_readl(fsl_edma, regs->intl);
0039     if (!intr)
0040         return IRQ_NONE;
0041 
0042     for (ch = 0; ch < fsl_edma->n_chans; ch++) {
0043         if (intr & (0x1 << ch)) {
0044             edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
0045 
0046             fsl_chan = &fsl_edma->chans[ch];
0047 
0048             spin_lock(&fsl_chan->vchan.lock);
0049 
0050             if (!fsl_chan->edesc) {
0051                 /* terminate_all called before */
0052                 spin_unlock(&fsl_chan->vchan.lock);
0053                 continue;
0054             }
0055 
0056             if (!fsl_chan->edesc->iscyclic) {
0057                 list_del(&fsl_chan->edesc->vdesc.node);
0058                 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
0059                 fsl_chan->edesc = NULL;
0060                 fsl_chan->status = DMA_COMPLETE;
0061                 fsl_chan->idle = true;
0062             } else {
0063                 vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
0064             }
0065 
0066             if (!fsl_chan->edesc)
0067                 fsl_edma_xfer_desc(fsl_chan);
0068 
0069             spin_unlock(&fsl_chan->vchan.lock);
0070         }
0071     }
0072     return IRQ_HANDLED;
0073 }
0074 
0075 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
0076 {
0077     struct fsl_edma_engine *fsl_edma = dev_id;
0078     unsigned int err, ch;
0079     struct edma_regs *regs = &fsl_edma->regs;
0080 
0081     err = edma_readl(fsl_edma, regs->errl);
0082     if (!err)
0083         return IRQ_NONE;
0084 
0085     for (ch = 0; ch < fsl_edma->n_chans; ch++) {
0086         if (err & (0x1 << ch)) {
0087             fsl_edma_disable_request(&fsl_edma->chans[ch]);
0088             edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
0089             fsl_edma->chans[ch].status = DMA_ERROR;
0090             fsl_edma->chans[ch].idle = true;
0091         }
0092     }
0093     return IRQ_HANDLED;
0094 }
0095 
0096 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
0097 {
0098     if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
0099         return IRQ_HANDLED;
0100 
0101     return fsl_edma_err_handler(irq, dev_id);
0102 }
0103 
0104 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
0105         struct of_dma *ofdma)
0106 {
0107     struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
0108     struct dma_chan *chan, *_chan;
0109     struct fsl_edma_chan *fsl_chan;
0110     u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
0111     unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
0112 
0113     if (dma_spec->args_count != 2)
0114         return NULL;
0115 
0116     mutex_lock(&fsl_edma->fsl_edma_mutex);
0117     list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
0118         if (chan->client_count)
0119             continue;
0120         if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
0121             chan = dma_get_slave_channel(chan);
0122             if (chan) {
0123                 chan->device->privatecnt++;
0124                 fsl_chan = to_fsl_edma_chan(chan);
0125                 fsl_chan->slave_id = dma_spec->args[1];
0126                 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
0127                         true);
0128                 mutex_unlock(&fsl_edma->fsl_edma_mutex);
0129                 return chan;
0130             }
0131         }
0132     }
0133     mutex_unlock(&fsl_edma->fsl_edma_mutex);
0134     return NULL;
0135 }
0136 
0137 static int
0138 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
0139 {
0140     int ret;
0141 
0142     fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
0143     if (fsl_edma->txirq < 0)
0144         return fsl_edma->txirq;
0145 
0146     fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
0147     if (fsl_edma->errirq < 0)
0148         return fsl_edma->errirq;
0149 
0150     if (fsl_edma->txirq == fsl_edma->errirq) {
0151         ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
0152                 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
0153         if (ret) {
0154             dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
0155             return ret;
0156         }
0157     } else {
0158         ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
0159                 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
0160         if (ret) {
0161             dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
0162             return ret;
0163         }
0164 
0165         ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
0166                 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
0167         if (ret) {
0168             dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
0169             return ret;
0170         }
0171     }
0172 
0173     return 0;
0174 }
0175 
0176 static int
0177 fsl_edma2_irq_init(struct platform_device *pdev,
0178            struct fsl_edma_engine *fsl_edma)
0179 {
0180     int i, ret, irq;
0181     int count;
0182 
0183     count = platform_irq_count(pdev);
0184     dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
0185     if (count <= 2) {
0186         dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
0187         return -EINVAL;
0188     }
0189     /*
0190      * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
0191      * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
0192      * For now, just simply request irq without IRQF_SHARED flag, since 16
0193      * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
0194      */
0195     for (i = 0; i < count; i++) {
0196         irq = platform_get_irq(pdev, i);
0197         if (irq < 0)
0198             return -ENXIO;
0199 
0200         sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
0201 
0202         /* The last IRQ is for eDMA err */
0203         if (i == count - 1)
0204             ret = devm_request_irq(&pdev->dev, irq,
0205                         fsl_edma_err_handler,
0206                         0, "eDMA2-ERR", fsl_edma);
0207         else
0208             ret = devm_request_irq(&pdev->dev, irq,
0209                         fsl_edma_tx_handler, 0,
0210                         fsl_edma->chans[i].chan_name,
0211                         fsl_edma);
0212         if (ret)
0213             return ret;
0214     }
0215 
0216     return 0;
0217 }
0218 
0219 static void fsl_edma_irq_exit(
0220         struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
0221 {
0222     if (fsl_edma->txirq == fsl_edma->errirq) {
0223         devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
0224     } else {
0225         devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
0226         devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
0227     }
0228 }
0229 
0230 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
0231 {
0232     int i;
0233 
0234     for (i = 0; i < nr_clocks; i++)
0235         clk_disable_unprepare(fsl_edma->muxclk[i]);
0236 }
0237 
0238 static struct fsl_edma_drvdata vf610_data = {
0239     .version = v1,
0240     .dmamuxs = DMAMUX_NR,
0241     .setup_irq = fsl_edma_irq_init,
0242 };
0243 
0244 static struct fsl_edma_drvdata ls1028a_data = {
0245     .version = v1,
0246     .dmamuxs = DMAMUX_NR,
0247     .mux_swap = true,
0248     .setup_irq = fsl_edma_irq_init,
0249 };
0250 
0251 static struct fsl_edma_drvdata imx7ulp_data = {
0252     .version = v3,
0253     .dmamuxs = 1,
0254     .has_dmaclk = true,
0255     .setup_irq = fsl_edma2_irq_init,
0256 };
0257 
0258 static const struct of_device_id fsl_edma_dt_ids[] = {
0259     { .compatible = "fsl,vf610-edma", .data = &vf610_data},
0260     { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
0261     { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
0262     { /* sentinel */ }
0263 };
0264 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
0265 
0266 static int fsl_edma_probe(struct platform_device *pdev)
0267 {
0268     const struct of_device_id *of_id =
0269             of_match_device(fsl_edma_dt_ids, &pdev->dev);
0270     struct device_node *np = pdev->dev.of_node;
0271     struct fsl_edma_engine *fsl_edma;
0272     const struct fsl_edma_drvdata *drvdata = NULL;
0273     struct fsl_edma_chan *fsl_chan;
0274     struct edma_regs *regs;
0275     struct resource *res;
0276     int len, chans;
0277     int ret, i;
0278 
0279     if (of_id)
0280         drvdata = of_id->data;
0281     if (!drvdata) {
0282         dev_err(&pdev->dev, "unable to find driver data\n");
0283         return -EINVAL;
0284     }
0285 
0286     ret = of_property_read_u32(np, "dma-channels", &chans);
0287     if (ret) {
0288         dev_err(&pdev->dev, "Can't get dma-channels.\n");
0289         return ret;
0290     }
0291 
0292     len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
0293     fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
0294     if (!fsl_edma)
0295         return -ENOMEM;
0296 
0297     fsl_edma->drvdata = drvdata;
0298     fsl_edma->n_chans = chans;
0299     mutex_init(&fsl_edma->fsl_edma_mutex);
0300 
0301     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0302     fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
0303     if (IS_ERR(fsl_edma->membase))
0304         return PTR_ERR(fsl_edma->membase);
0305 
0306     fsl_edma_setup_regs(fsl_edma);
0307     regs = &fsl_edma->regs;
0308 
0309     if (drvdata->has_dmaclk) {
0310         fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
0311         if (IS_ERR(fsl_edma->dmaclk)) {
0312             dev_err(&pdev->dev, "Missing DMA block clock.\n");
0313             return PTR_ERR(fsl_edma->dmaclk);
0314         }
0315 
0316         ret = clk_prepare_enable(fsl_edma->dmaclk);
0317         if (ret) {
0318             dev_err(&pdev->dev, "DMA clk block failed.\n");
0319             return ret;
0320         }
0321     }
0322 
0323     for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
0324         char clkname[32];
0325 
0326         res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
0327         fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
0328         if (IS_ERR(fsl_edma->muxbase[i])) {
0329             /* on error: disable all previously enabled clks */
0330             fsl_disable_clocks(fsl_edma, i);
0331             return PTR_ERR(fsl_edma->muxbase[i]);
0332         }
0333 
0334         sprintf(clkname, "dmamux%d", i);
0335         fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
0336         if (IS_ERR(fsl_edma->muxclk[i])) {
0337             dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
0338             /* on error: disable all previously enabled clks */
0339             fsl_disable_clocks(fsl_edma, i);
0340             return PTR_ERR(fsl_edma->muxclk[i]);
0341         }
0342 
0343         ret = clk_prepare_enable(fsl_edma->muxclk[i]);
0344         if (ret)
0345             /* on error: disable all previously enabled clks */
0346             fsl_disable_clocks(fsl_edma, i);
0347 
0348     }
0349 
0350     fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
0351 
0352     INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
0353     for (i = 0; i < fsl_edma->n_chans; i++) {
0354         struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
0355 
0356         fsl_chan->edma = fsl_edma;
0357         fsl_chan->pm_state = RUNNING;
0358         fsl_chan->slave_id = 0;
0359         fsl_chan->idle = true;
0360         fsl_chan->dma_dir = DMA_NONE;
0361         fsl_chan->vchan.desc_free = fsl_edma_free_desc;
0362         vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
0363 
0364         edma_writew(fsl_edma, 0x0, &regs->tcd[i].csr);
0365         fsl_edma_chan_mux(fsl_chan, 0, false);
0366     }
0367 
0368     edma_writel(fsl_edma, ~0, regs->intl);
0369     ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
0370     if (ret)
0371         return ret;
0372 
0373     dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
0374     dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
0375     dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
0376     dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
0377 
0378     fsl_edma->dma_dev.dev = &pdev->dev;
0379     fsl_edma->dma_dev.device_alloc_chan_resources
0380         = fsl_edma_alloc_chan_resources;
0381     fsl_edma->dma_dev.device_free_chan_resources
0382         = fsl_edma_free_chan_resources;
0383     fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
0384     fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
0385     fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
0386     fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
0387     fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
0388     fsl_edma->dma_dev.device_pause = fsl_edma_pause;
0389     fsl_edma->dma_dev.device_resume = fsl_edma_resume;
0390     fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
0391     fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
0392     fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
0393 
0394     fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
0395     fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
0396     fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
0397 
0398     fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;
0399     /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
0400     dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
0401 
0402     platform_set_drvdata(pdev, fsl_edma);
0403 
0404     ret = dma_async_device_register(&fsl_edma->dma_dev);
0405     if (ret) {
0406         dev_err(&pdev->dev,
0407             "Can't register Freescale eDMA engine. (%d)\n", ret);
0408         fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
0409         return ret;
0410     }
0411 
0412     ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
0413     if (ret) {
0414         dev_err(&pdev->dev,
0415             "Can't register Freescale eDMA of_dma. (%d)\n", ret);
0416         dma_async_device_unregister(&fsl_edma->dma_dev);
0417         fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
0418         return ret;
0419     }
0420 
0421     /* enable round robin arbitration */
0422     edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
0423 
0424     return 0;
0425 }
0426 
0427 static int fsl_edma_remove(struct platform_device *pdev)
0428 {
0429     struct device_node *np = pdev->dev.of_node;
0430     struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
0431 
0432     fsl_edma_irq_exit(pdev, fsl_edma);
0433     fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
0434     of_dma_controller_free(np);
0435     dma_async_device_unregister(&fsl_edma->dma_dev);
0436     fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
0437 
0438     return 0;
0439 }
0440 
0441 static int fsl_edma_suspend_late(struct device *dev)
0442 {
0443     struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
0444     struct fsl_edma_chan *fsl_chan;
0445     unsigned long flags;
0446     int i;
0447 
0448     for (i = 0; i < fsl_edma->n_chans; i++) {
0449         fsl_chan = &fsl_edma->chans[i];
0450         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
0451         /* Make sure chan is idle or will force disable. */
0452         if (unlikely(!fsl_chan->idle)) {
0453             dev_warn(dev, "WARN: There is non-idle channel.");
0454             fsl_edma_disable_request(fsl_chan);
0455             fsl_edma_chan_mux(fsl_chan, 0, false);
0456         }
0457 
0458         fsl_chan->pm_state = SUSPENDED;
0459         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
0460     }
0461 
0462     return 0;
0463 }
0464 
0465 static int fsl_edma_resume_early(struct device *dev)
0466 {
0467     struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
0468     struct fsl_edma_chan *fsl_chan;
0469     struct edma_regs *regs = &fsl_edma->regs;
0470     int i;
0471 
0472     for (i = 0; i < fsl_edma->n_chans; i++) {
0473         fsl_chan = &fsl_edma->chans[i];
0474         fsl_chan->pm_state = RUNNING;
0475         edma_writew(fsl_edma, 0x0, &regs->tcd[i].csr);
0476         if (fsl_chan->slave_id != 0)
0477             fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
0478     }
0479 
0480     edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
0481 
0482     return 0;
0483 }
0484 
0485 /*
0486  * eDMA provides the service to others, so it should be suspend late
0487  * and resume early. When eDMA suspend, all of the clients should stop
0488  * the DMA data transmission and let the channel idle.
0489  */
0490 static const struct dev_pm_ops fsl_edma_pm_ops = {
0491     .suspend_late   = fsl_edma_suspend_late,
0492     .resume_early   = fsl_edma_resume_early,
0493 };
0494 
0495 static struct platform_driver fsl_edma_driver = {
0496     .driver     = {
0497         .name   = "fsl-edma",
0498         .of_match_table = fsl_edma_dt_ids,
0499         .pm     = &fsl_edma_pm_ops,
0500     },
0501     .probe          = fsl_edma_probe,
0502     .remove     = fsl_edma_remove,
0503 };
0504 
0505 static int __init fsl_edma_init(void)
0506 {
0507     return platform_driver_register(&fsl_edma_driver);
0508 }
0509 subsys_initcall(fsl_edma_init);
0510 
0511 static void __exit fsl_edma_exit(void)
0512 {
0513     platform_driver_unregister(&fsl_edma_driver);
0514 }
0515 module_exit(fsl_edma_exit);
0516 
0517 MODULE_ALIAS("platform:fsl-edma");
0518 MODULE_DESCRIPTION("Freescale eDMA engine driver");
0519 MODULE_LICENSE("GPL v2");
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