drivers/dma/fsl-edma-common.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright 2013-2014 Freescale Semiconductor, Inc.
0004  * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
0005  */
0006 #ifndef _FSL_EDMA_COMMON_H_
0007 #define _FSL_EDMA_COMMON_H_
0008
0009 #include <linux/dma-direction.h>
0010 #include <linux/platform_device.h>
0011 #include "virt-dma.h"
0012
0013 #define EDMA_CR_EDBG        BIT(1)
0014 #define EDMA_CR_ERCA        BIT(2)
0015 #define EDMA_CR_ERGA        BIT(3)
0016 #define EDMA_CR_HOE     BIT(4)
0017 #define EDMA_CR_HALT        BIT(5)
0018 #define EDMA_CR_CLM     BIT(6)
0019 #define EDMA_CR_EMLM        BIT(7)
0020 #define EDMA_CR_ECX     BIT(16)
0021 #define EDMA_CR_CX      BIT(17)
0022
0023 #define EDMA_SEEI_SEEI(x)   ((x) & GENMASK(4, 0))
0024 #define EDMA_CEEI_CEEI(x)   ((x) & GENMASK(4, 0))
0025 #define EDMA_CINT_CINT(x)   ((x) & GENMASK(4, 0))
0026 #define EDMA_CERR_CERR(x)   ((x) & GENMASK(4, 0))
0027
0028 #define EDMA_TCD_ATTR_DSIZE(x)      (((x) & GENMASK(2, 0)))
0029 #define EDMA_TCD_ATTR_DMOD(x)       (((x) & GENMASK(4, 0)) << 3)
0030 #define EDMA_TCD_ATTR_SSIZE(x)      (((x) & GENMASK(2, 0)) << 8)
0031 #define EDMA_TCD_ATTR_SMOD(x)       (((x) & GENMASK(4, 0)) << 11)
0032 #define EDMA_TCD_ATTR_DSIZE_8BIT    0
0033 #define EDMA_TCD_ATTR_DSIZE_16BIT   BIT(0)
0034 #define EDMA_TCD_ATTR_DSIZE_32BIT   BIT(1)
0035 #define EDMA_TCD_ATTR_DSIZE_64BIT   (BIT(0) | BIT(1))
0036 #define EDMA_TCD_ATTR_DSIZE_32BYTE  (BIT(2) | BIT(0))
0037 #define EDMA_TCD_ATTR_SSIZE_8BIT    0
0038 #define EDMA_TCD_ATTR_SSIZE_16BIT   (EDMA_TCD_ATTR_DSIZE_16BIT << 8)
0039 #define EDMA_TCD_ATTR_SSIZE_32BIT   (EDMA_TCD_ATTR_DSIZE_32BIT << 8)
0040 #define EDMA_TCD_ATTR_SSIZE_64BIT   (EDMA_TCD_ATTR_DSIZE_64BIT << 8)
0041 #define EDMA_TCD_ATTR_SSIZE_32BYTE  (EDMA_TCD_ATTR_DSIZE_32BYTE << 8)
0042
0043 #define EDMA_TCD_CITER_CITER(x)     ((x) & GENMASK(14, 0))
0044 #define EDMA_TCD_BITER_BITER(x)     ((x) & GENMASK(14, 0))
0045
0046 #define EDMA_TCD_CSR_START      BIT(0)
0047 #define EDMA_TCD_CSR_INT_MAJOR      BIT(1)
0048 #define EDMA_TCD_CSR_INT_HALF       BIT(2)
0049 #define EDMA_TCD_CSR_D_REQ      BIT(3)
0050 #define EDMA_TCD_CSR_E_SG       BIT(4)
0051 #define EDMA_TCD_CSR_E_LINK     BIT(5)
0052 #define EDMA_TCD_CSR_ACTIVE     BIT(6)
0053 #define EDMA_TCD_CSR_DONE       BIT(7)
0054
0055 #define EDMAMUX_CHCFG_DIS       0x0
0056 #define EDMAMUX_CHCFG_ENBL      0x80
0057 #define EDMAMUX_CHCFG_SOURCE(n)     ((n) & 0x3F)
0058
0059 #define DMAMUX_NR   2
0060
0061 #define FSL_EDMA_BUSWIDTHS  (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
0062                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
0063                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
0064                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
0065 enum fsl_edma_pm_state {
0066     RUNNING = 0,
0067     SUSPENDED,
0068 };
0069
0070 struct fsl_edma_hw_tcd {
0071     __le32  saddr;
0072     __le16  soff;
0073     __le16  attr;
0074     __le32  nbytes;
0075     __le32  slast;
0076     __le32  daddr;
0077     __le16  doff;
0078     __le16  citer;
0079     __le32  dlast_sga;
0080     __le16  csr;
0081     __le16  biter;
0082 };
0083
0084 /*
0085  * These are iomem pointers, for both v32 and v64.
0086  */
0087 struct edma_regs {
0088     void __iomem *cr;
0089     void __iomem *es;
0090     void __iomem *erqh;
0091     void __iomem *erql; /* aka erq on v32 */
0092     void __iomem *eeih;
0093     void __iomem *eeil; /* aka eei on v32 */
0094     void __iomem *seei;
0095     void __iomem *ceei;
0096     void __iomem *serq;
0097     void __iomem *cerq;
0098     void __iomem *cint;
0099     void __iomem *cerr;
0100     void __iomem *ssrt;
0101     void __iomem *cdne;
0102     void __iomem *inth;
0103     void __iomem *intl;
0104     void __iomem *errh;
0105     void __iomem *errl;
0106     struct fsl_edma_hw_tcd __iomem *tcd;
0107 };
0108
0109 struct fsl_edma_sw_tcd {
0110     dma_addr_t          ptcd;
0111     struct fsl_edma_hw_tcd      *vtcd;
0112 };
0113
0114 struct fsl_edma_chan {
0115     struct virt_dma_chan        vchan;
0116     enum dma_status         status;
0117     enum fsl_edma_pm_state      pm_state;
0118     bool                idle;
0119     u32             slave_id;
0120     struct fsl_edma_engine      *edma;
0121     struct fsl_edma_desc        *edesc;
0122     struct dma_slave_config     cfg;
0123     u32             attr;
0124     bool                            is_sw;
0125     struct dma_pool         *tcd_pool;
0126     dma_addr_t          dma_dev_addr;
0127     u32             dma_dev_size;
0128     enum dma_data_direction     dma_dir;
0129     char                chan_name[16];
0130 };
0131
0132 struct fsl_edma_desc {
0133     struct virt_dma_desc        vdesc;
0134     struct fsl_edma_chan        *echan;
0135     bool                iscyclic;
0136     enum dma_transfer_direction dirn;
0137     unsigned int            n_tcds;
0138     struct fsl_edma_sw_tcd      tcd[];
0139 };
0140
0141 enum edma_version {
0142     v1, /* 32ch, Vybrid, mpc57x, etc */
0143     v2, /* 64ch Coldfire */
0144     v3, /* 32ch, i.mx7ulp */
0145 };
0146
0147 struct fsl_edma_drvdata {
0148     enum edma_version   version;
0149     u32         dmamuxs;
0150     bool            has_dmaclk;
0151     bool            mux_swap;
0152     int         (*setup_irq)(struct platform_device *pdev,
0153                          struct fsl_edma_engine *fsl_edma);
0154 };
0155
0156 struct fsl_edma_engine {
0157     struct dma_device   dma_dev;
0158     void __iomem        *membase;
0159     void __iomem        *muxbase[DMAMUX_NR];
0160     struct clk      *muxclk[DMAMUX_NR];
0161     struct clk      *dmaclk;
0162     struct mutex        fsl_edma_mutex;
0163     const struct fsl_edma_drvdata *drvdata;
0164     u32         n_chans;
0165     int         txirq;
0166     int         errirq;
0167     bool            big_endian;
0168     struct edma_regs    regs;
0169     struct fsl_edma_chan    chans[];
0170 };
0171
0172 /*
0173  * R/W functions for big- or little-endian registers:
0174  * The eDMA controller's endian is independent of the CPU core's endian.
0175  * For the big-endian IP module, the offset for 8-bit or 16-bit registers
0176  * should also be swapped opposite to that in little-endian IP.
0177  */
0178 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
0179 {
0180     if (edma->big_endian)
0181         return ioread32be(addr);
0182     else
0183         return ioread32(addr);
0184 }
0185
0186 static inline void edma_writeb(struct fsl_edma_engine *edma,
0187                    u8 val, void __iomem *addr)
0188 {
0189     /* swap the reg offset for these in big-endian mode */
0190     if (edma->big_endian)
0191         iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
0192     else
0193         iowrite8(val, addr);
0194 }
0195
0196 static inline void edma_writew(struct fsl_edma_engine *edma,
0197                    u16 val, void __iomem *addr)
0198 {
0199     /* swap the reg offset for these in big-endian mode */
0200     if (edma->big_endian)
0201         iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
0202     else
0203         iowrite16(val, addr);
0204 }
0205
0206 static inline void edma_writel(struct fsl_edma_engine *edma,
0207                    u32 val, void __iomem *addr)
0208 {
0209     if (edma->big_endian)
0210         iowrite32be(val, addr);
0211     else
0212         iowrite32(val, addr);
0213 }
0214
0215 static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
0216 {
0217     return container_of(chan, struct fsl_edma_chan, vchan.chan);
0218 }
0219
0220 static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
0221 {
0222     return container_of(vd, struct fsl_edma_desc, vdesc);
0223 }
0224
0225 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
0226 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
0227             unsigned int slot, bool enable);
0228 void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
0229 int fsl_edma_terminate_all(struct dma_chan *chan);
0230 int fsl_edma_pause(struct dma_chan *chan);
0231 int fsl_edma_resume(struct dma_chan *chan);
0232 int fsl_edma_slave_config(struct dma_chan *chan,
0233                  struct dma_slave_config *cfg);
0234 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
0235         dma_cookie_t cookie, struct dma_tx_state *txstate);
0236 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
0237         struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
0238         size_t period_len, enum dma_transfer_direction direction,
0239         unsigned long flags);
0240 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
0241         struct dma_chan *chan, struct scatterlist *sgl,
0242         unsigned int sg_len, enum dma_transfer_direction direction,
0243         unsigned long flags, void *context);
0244 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
0245         struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
0246         size_t len, unsigned long flags);
0247 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
0248 void fsl_edma_issue_pending(struct dma_chan *chan);
0249 int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
0250 void fsl_edma_free_chan_resources(struct dma_chan *chan);
0251 void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
0252 void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
0253
0254 #endif /* _FSL_EDMA_COMMON_H_ */