dma/fsl-dpaa2-qdma/dpaa2-qdma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright 2019 NXP */
0003
0004 #ifndef __DPAA2_QDMA_H
0005 #define __DPAA2_QDMA_H
0006
0007 #define DPAA2_QDMA_STORE_SIZE 16
0008 #define NUM_CH 8
0009
0010 struct dpaa2_qdma_sd_d {
0011     u32 rsv:32;
0012     union {
0013         struct {
0014             u32 ssd:12; /* souce stride distance */
0015             u32 sss:12; /* souce stride size */
0016             u32 rsv1:8;
0017         } sdf;
0018         struct {
0019             u32 dsd:12; /* Destination stride distance */
0020             u32 dss:12; /* Destination stride size */
0021             u32 rsv2:8;
0022         } ddf;
0023     } df;
0024     u32 rbpcmd; /* Route-by-port command */
0025     u32 cmd;
0026 } __attribute__((__packed__));
0027
0028 /* Source descriptor command read transaction type for RBP=0: */
0029 /* coherent copy of cacheable memory */
0030 #define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28)
0031 /* Destination descriptor command write transaction type for RBP=0: */
0032 /* coherent copy of cacheable memory */
0033 #define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28)
0034 #define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28)
0035
0036 #define QMAN_FD_FMT_ENABLE  BIT(0) /* frame list table enable */
0037 #define QMAN_FD_BMT_ENABLE  BIT(15) /* bypass memory translation */
0038 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
0039 #define QMAN_FD_SL_DISABLE  (0) /* short lengthe disabled */
0040 #define QMAN_FD_SL_ENABLE   BIT(14) /* short lengthe enabled */
0041
0042 #define QDMA_FINAL_BIT_DISABLE  (0) /* final bit disable */
0043 #define QDMA_FINAL_BIT_ENABLE   BIT(31) /* final bit enable */
0044
0045 #define QDMA_FD_SHORT_FORMAT    BIT(11) /* short format */
0046 #define QDMA_FD_LONG_FORMAT (0) /* long format */
0047 #define QDMA_SER_DISABLE    (8) /* no notification */
0048 #define QDMA_SER_CTX        BIT(8) /* notification by FQD_CTX[fqid] */
0049 #define QDMA_SER_DEST       (2 << 8) /* notification by destination desc */
0050 #define QDMA_SER_BOTH       (3 << 8) /* soruce and dest notification */
0051 #define QDMA_FD_SPF_ENALBE  BIT(30) /* source prefetch enable */
0052
0053 #define QMAN_FD_VA_ENABLE   BIT(14) /* Address used is virtual address */
0054 #define QMAN_FD_VA_DISABLE  (0)/* Address used is a real address */
0055 /* Flow Context: 49bit physical address */
0056 #define QMAN_FD_CBMT_ENABLE BIT(15)
0057 #define QMAN_FD_CBMT_DISABLE    (0) /* Flow Context: 64bit virtual address */
0058 #define QMAN_FD_SC_DISABLE  (0) /* stashing control */
0059
0060 #define QDMA_FL_FMT_SBF     (0x0) /* Single buffer frame */
0061 #define QDMA_FL_FMT_SGE     (0x2) /* Scatter gather frame */
0062 #define QDMA_FL_BMT_ENABLE  BIT(15) /* enable bypass memory translation */
0063 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
0064 #define QDMA_FL_SL_LONG     (0x0)/* long length */
0065 #define QDMA_FL_SL_SHORT    (0x1) /* short length */
0066 #define QDMA_FL_F       (0x1)/* last frame list bit */
0067
0068 /*Description of Frame list table structure*/
0069 struct dpaa2_qdma_chan {
0070     struct dpaa2_qdma_engine    *qdma;
0071     struct virt_dma_chan        vchan;
0072     struct virt_dma_desc        vdesc;
0073     enum dma_status         status;
0074     u32             fqid;
0075
0076     /* spinlock used by dpaa2 qdma driver */
0077     spinlock_t          queue_lock;
0078     struct dma_pool         *fd_pool;
0079     struct dma_pool         *fl_pool;
0080     struct dma_pool         *sdd_pool;
0081
0082     struct list_head        comp_used;
0083     struct list_head        comp_free;
0084
0085 };
0086
0087 struct dpaa2_qdma_comp {
0088     dma_addr_t      fd_bus_addr;
0089     dma_addr_t      fl_bus_addr;
0090     dma_addr_t      desc_bus_addr;
0091     struct dpaa2_fd     *fd_virt_addr;
0092     struct dpaa2_fl_entry   *fl_virt_addr;
0093     struct dpaa2_qdma_sd_d  *desc_virt_addr;
0094     struct dpaa2_qdma_chan  *qchan;
0095     struct virt_dma_desc    vdesc;
0096     struct list_head    list;
0097 };
0098
0099 struct dpaa2_qdma_engine {
0100     struct dma_device   dma_dev;
0101     u32         n_chans;
0102     struct dpaa2_qdma_chan  chans[NUM_CH];
0103     int         qdma_wrtype_fixup;
0104     int         desc_allocated;
0105
0106     struct dpaa2_qdma_priv *priv;
0107 };
0108
0109 /*
0110  * dpaa2_qdma_priv - driver private data
0111  */
0112 struct dpaa2_qdma_priv {
0113     int dpqdma_id;
0114
0115     struct iommu_domain *iommu_domain;
0116     struct dpdmai_attr  dpdmai_attr;
0117     struct device       *dev;
0118     struct fsl_mc_io    *mc_io;
0119     struct fsl_mc_device    *dpdmai_dev;
0120     u8          num_pairs;
0121
0122     struct dpaa2_qdma_engine    *dpaa2_qdma;
0123     struct dpaa2_qdma_priv_per_prio *ppriv;
0124
0125     struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM];
0126     u32 tx_fqid[DPDMAI_PRIO_NUM];
0127 };
0128
0129 struct dpaa2_qdma_priv_per_prio {
0130     int req_fqid;
0131     int rsp_fqid;
0132     int prio;
0133
0134     struct dpaa2_io_store *store;
0135     struct dpaa2_io_notification_ctx nctx;
0136
0137     struct dpaa2_qdma_priv *priv;
0138 };
0139
0140 static struct soc_device_attribute soc_fixup_tuning[] = {
0141     { .family = "QorIQ LX2160A"},
0142     { /* sentinel */ }
0143 };
0144
0145 /* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
0146 #define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
0147         sizeof(struct dpaa2_fl_entry) * 3 + \
0148         sizeof(struct dpaa2_qdma_sd_d) * 2)
0149
0150 static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma);
0151 static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan,
0152                    struct list_head *head);
0153 #endif /* __DPAA2_QDMA_H */