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0010 #include <linux/of.h>
0011 #include <linux/of_dma.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "internal.h"
0015
0016 static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
0017 struct of_dma *ofdma)
0018 {
0019 struct dw_dma *dw = ofdma->of_dma_data;
0020 struct dw_dma_slave slave = {
0021 .dma_dev = dw->dma.dev,
0022 };
0023 dma_cap_mask_t cap;
0024
0025 if (dma_spec->args_count < 3 || dma_spec->args_count > 4)
0026 return NULL;
0027
0028 slave.src_id = dma_spec->args[0];
0029 slave.dst_id = dma_spec->args[0];
0030 slave.m_master = dma_spec->args[1];
0031 slave.p_master = dma_spec->args[2];
0032 if (dma_spec->args_count >= 4)
0033 slave.channels = dma_spec->args[3];
0034
0035 if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
0036 slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
0037 slave.m_master >= dw->pdata->nr_masters ||
0038 slave.p_master >= dw->pdata->nr_masters ||
0039 slave.channels >= BIT(dw->pdata->nr_channels)))
0040 return NULL;
0041
0042 dma_cap_zero(cap);
0043 dma_cap_set(DMA_SLAVE, cap);
0044
0045
0046 return dma_request_channel(cap, dw_dma_filter, &slave);
0047 }
0048
0049 struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev)
0050 {
0051 struct device_node *np = pdev->dev.of_node;
0052 struct dw_dma_platform_data *pdata;
0053 u32 tmp, arr[DW_DMA_MAX_NR_MASTERS];
0054 u32 nr_masters;
0055 u32 nr_channels;
0056
0057 if (of_property_read_u32(np, "dma-masters", &nr_masters))
0058 return NULL;
0059 if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS)
0060 return NULL;
0061
0062 if (of_property_read_u32(np, "dma-channels", &nr_channels))
0063 return NULL;
0064 if (nr_channels > DW_DMA_MAX_NR_CHANNELS)
0065 return NULL;
0066
0067 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
0068 if (!pdata)
0069 return NULL;
0070
0071 pdata->nr_masters = nr_masters;
0072 pdata->nr_channels = nr_channels;
0073
0074 of_property_read_u32(np, "chan_allocation_order", &pdata->chan_allocation_order);
0075 of_property_read_u32(np, "chan_priority", &pdata->chan_priority);
0076
0077 of_property_read_u32(np, "block_size", &pdata->block_size);
0078
0079
0080 if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
0081 for (tmp = 0; tmp < nr_masters; tmp++)
0082 pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
0083 }
0084
0085
0086 of_property_read_u32_array(np, "data-width", pdata->data_width, nr_masters);
0087
0088 memset32(pdata->multi_block, 1, nr_channels);
0089 of_property_read_u32_array(np, "multi-block", pdata->multi_block, nr_channels);
0090
0091 memset32(pdata->max_burst, DW_DMA_MAX_BURST, nr_channels);
0092 of_property_read_u32_array(np, "snps,max-burst-len", pdata->max_burst, nr_channels);
0093
0094 of_property_read_u32(np, "snps,dma-protection-control", &pdata->protctl);
0095 if (pdata->protctl > CHAN_PROTCTL_MASK)
0096 return NULL;
0097
0098 return pdata;
0099 }
0100
0101 void dw_dma_of_controller_register(struct dw_dma *dw)
0102 {
0103 struct device *dev = dw->dma.dev;
0104 int ret;
0105
0106 if (!dev->of_node)
0107 return;
0108
0109 ret = of_dma_controller_register(dev->of_node, dw_dma_of_xlate, dw);
0110 if (ret)
0111 dev_err(dev, "could not register of_dma_controller\n");
0112 }
0113
0114 void dw_dma_of_controller_free(struct dw_dma *dw)
0115 {
0116 struct device *dev = dw->dma.dev;
0117
0118 if (!dev->of_node)
0119 return;
0120
0121 of_dma_controller_free(dev->of_node);
0122 }