dma/dw/idma32.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2013,2018,2020-2021 Intel Corporation
0003
0004 #include <linux/bitops.h>
0005 #include <linux/dmaengine.h>
0006 #include <linux/errno.h>
0007 #include <linux/io.h>
0008 #include <linux/pci.h>
0009 #include <linux/slab.h>
0010 #include <linux/types.h>
0011
0012 #include "internal.h"
0013
0014 #define DMA_CTL_CH(x)           (0x1000 + (x) * 4)
0015 #define DMA_SRC_ADDR_FILLIN(x)      (0x1100 + (x) * 4)
0016 #define DMA_DST_ADDR_FILLIN(x)      (0x1200 + (x) * 4)
0017 #define DMA_XBAR_SEL(x)         (0x1300 + (x) * 4)
0018 #define DMA_REGACCESS_CHID_CFG      (0x1400)
0019
0020 #define CTL_CH_TRANSFER_MODE_MASK   GENMASK(1, 0)
0021 #define CTL_CH_TRANSFER_MODE_S2S    0
0022 #define CTL_CH_TRANSFER_MODE_S2D    1
0023 #define CTL_CH_TRANSFER_MODE_D2S    2
0024 #define CTL_CH_TRANSFER_MODE_D2D    3
0025 #define CTL_CH_RD_RS_MASK       GENMASK(4, 3)
0026 #define CTL_CH_WR_RS_MASK       GENMASK(6, 5)
0027 #define CTL_CH_RD_NON_SNOOP_BIT     BIT(8)
0028 #define CTL_CH_WR_NON_SNOOP_BIT     BIT(9)
0029
0030 #define XBAR_SEL_DEVID_MASK     GENMASK(15, 0)
0031 #define XBAR_SEL_RX_TX_BIT      BIT(16)
0032 #define XBAR_SEL_RX_TX_SHIFT        16
0033
0034 #define REGACCESS_CHID_MASK     GENMASK(2, 0)
0035
0036 static unsigned int idma32_get_slave_devfn(struct dw_dma_chan *dwc)
0037 {
0038     struct device *slave = dwc->chan.slave;
0039
0040     if (!slave || !dev_is_pci(slave))
0041         return 0;
0042
0043     return to_pci_dev(slave)->devfn;
0044 }
0045
0046 static void idma32_initialize_chan_xbar(struct dw_dma_chan *dwc)
0047 {
0048     struct dw_dma *dw = to_dw_dma(dwc->chan.device);
0049     void __iomem *misc = __dw_regs(dw);
0050     u32 cfghi = 0, cfglo = 0;
0051     u8 dst_id, src_id;
0052     u32 value;
0053
0054     /* DMA Channel ID Configuration register must be programmed first */
0055     value = readl(misc + DMA_REGACCESS_CHID_CFG);
0056
0057     value &= ~REGACCESS_CHID_MASK;
0058     value |= dwc->chan.chan_id;
0059
0060     writel(value, misc + DMA_REGACCESS_CHID_CFG);
0061
0062     /* Configure channel attributes */
0063     value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id));
0064
0065     value &= ~(CTL_CH_RD_NON_SNOOP_BIT | CTL_CH_WR_NON_SNOOP_BIT);
0066     value &= ~(CTL_CH_RD_RS_MASK | CTL_CH_WR_RS_MASK);
0067     value &= ~CTL_CH_TRANSFER_MODE_MASK;
0068
0069     switch (dwc->direction) {
0070     case DMA_MEM_TO_DEV:
0071         value |= CTL_CH_TRANSFER_MODE_D2S;
0072         value |= CTL_CH_WR_NON_SNOOP_BIT;
0073         break;
0074     case DMA_DEV_TO_MEM:
0075         value |= CTL_CH_TRANSFER_MODE_S2D;
0076         value |= CTL_CH_RD_NON_SNOOP_BIT;
0077         break;
0078     default:
0079         /*
0080          * Memory-to-Memory and Device-to-Device are ignored for now.
0081          *
0082          * For Memory-to-Memory transfers we would need to set mode
0083          * and disable snooping on both sides.
0084          */
0085         return;
0086     }
0087
0088     writel(value, misc + DMA_CTL_CH(dwc->chan.chan_id));
0089
0090     /* Configure crossbar selection */
0091     value = readl(misc + DMA_XBAR_SEL(dwc->chan.chan_id));
0092
0093     /* DEVFN selection */
0094     value &= ~XBAR_SEL_DEVID_MASK;
0095     value |= idma32_get_slave_devfn(dwc);
0096
0097     switch (dwc->direction) {
0098     case DMA_MEM_TO_DEV:
0099         value |= XBAR_SEL_RX_TX_BIT;
0100         break;
0101     case DMA_DEV_TO_MEM:
0102         value &= ~XBAR_SEL_RX_TX_BIT;
0103         break;
0104     default:
0105         /* Memory-to-Memory and Device-to-Device are ignored for now */
0106         return;
0107     }
0108
0109     writel(value, misc + DMA_XBAR_SEL(dwc->chan.chan_id));
0110
0111     /* Configure DMA channel low and high registers */
0112     switch (dwc->direction) {
0113     case DMA_MEM_TO_DEV:
0114         dst_id = dwc->chan.chan_id;
0115         src_id = dwc->dws.src_id;
0116         break;
0117     case DMA_DEV_TO_MEM:
0118         dst_id = dwc->dws.dst_id;
0119         src_id = dwc->chan.chan_id;
0120         break;
0121     default:
0122         /* Memory-to-Memory and Device-to-Device are ignored for now */
0123         return;
0124     }
0125
0126     /* Set default burst alignment */
0127     cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
0128
0129     /* Low 4 bits of the request lines */
0130     cfghi |= IDMA32C_CFGH_DST_PER(dst_id & 0xf);
0131     cfghi |= IDMA32C_CFGH_SRC_PER(src_id & 0xf);
0132
0133     /* Request line extension (2 bits) */
0134     cfghi |= IDMA32C_CFGH_DST_PER_EXT(dst_id >> 4 & 0x3);
0135     cfghi |= IDMA32C_CFGH_SRC_PER_EXT(src_id >> 4 & 0x3);
0136
0137     channel_writel(dwc, CFG_LO, cfglo);
0138     channel_writel(dwc, CFG_HI, cfghi);
0139 }
0140
0141 static void idma32_initialize_chan_generic(struct dw_dma_chan *dwc)
0142 {
0143     u32 cfghi = 0;
0144     u32 cfglo = 0;
0145
0146     /* Set default burst alignment */
0147     cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
0148
0149     /* Low 4 bits of the request lines */
0150     cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
0151     cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
0152
0153     /* Request line extension (2 bits) */
0154     cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
0155     cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
0156
0157     channel_writel(dwc, CFG_LO, cfglo);
0158     channel_writel(dwc, CFG_HI, cfghi);
0159 }
0160
0161 static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain)
0162 {
0163     u32 cfglo = channel_readl(dwc, CFG_LO);
0164
0165     if (drain)
0166         cfglo |= IDMA32C_CFGL_CH_DRAIN;
0167
0168     channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
0169 }
0170
0171 static void idma32_resume_chan(struct dw_dma_chan *dwc, bool drain)
0172 {
0173     u32 cfglo = channel_readl(dwc, CFG_LO);
0174
0175     if (drain)
0176         cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
0177
0178     channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
0179 }
0180
0181 static u32 idma32_bytes2block(struct dw_dma_chan *dwc,
0182                   size_t bytes, unsigned int width, size_t *len)
0183 {
0184     u32 block;
0185
0186     if (bytes > dwc->block_size) {
0187         block = dwc->block_size;
0188         *len = dwc->block_size;
0189     } else {
0190         block = bytes;
0191         *len = bytes;
0192     }
0193
0194     return block;
0195 }
0196
0197 static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
0198 {
0199     return IDMA32C_CTLH_BLOCK_TS(block);
0200 }
0201
0202 static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
0203 {
0204     struct dma_slave_config *sconfig = &dwc->dma_sconfig;
0205     u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
0206     u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
0207
0208     return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
0209            DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
0210 }
0211
0212 static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
0213 {
0214     *maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
0215 }
0216
0217 static void idma32_set_device_name(struct dw_dma *dw, int id)
0218 {
0219     snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);
0220 }
0221
0222 /*
0223  * Program FIFO size of channels.
0224  *
0225  * By default full FIFO (512 bytes) is assigned to channel 0. Here we
0226  * slice FIFO on equal parts between channels.
0227  */
0228 static void idma32_fifo_partition(struct dw_dma *dw)
0229 {
0230     u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
0231             IDMA32C_FP_UPDATE;
0232     u64 fifo_partition = 0;
0233
0234     /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
0235     fifo_partition |= value << 0;
0236
0237     /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
0238     fifo_partition |= value << 32;
0239
0240     /* Program FIFO Partition registers - 64 bytes per channel */
0241     idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
0242     idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
0243 }
0244
0245 static void idma32_disable(struct dw_dma *dw)
0246 {
0247     do_dw_dma_off(dw);
0248     idma32_fifo_partition(dw);
0249 }
0250
0251 static void idma32_enable(struct dw_dma *dw)
0252 {
0253     idma32_fifo_partition(dw);
0254     do_dw_dma_on(dw);
0255 }
0256
0257 int idma32_dma_probe(struct dw_dma_chip *chip)
0258 {
0259     struct dw_dma *dw;
0260
0261     dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
0262     if (!dw)
0263         return -ENOMEM;
0264
0265     /* Channel operations */
0266     if (chip->pdata->quirks & DW_DMA_QUIRK_XBAR_PRESENT)
0267         dw->initialize_chan = idma32_initialize_chan_xbar;
0268     else
0269         dw->initialize_chan = idma32_initialize_chan_generic;
0270     dw->suspend_chan = idma32_suspend_chan;
0271     dw->resume_chan = idma32_resume_chan;
0272     dw->prepare_ctllo = idma32_prepare_ctllo;
0273     dw->encode_maxburst = idma32_encode_maxburst;
0274     dw->bytes2block = idma32_bytes2block;
0275     dw->block2bytes = idma32_block2bytes;
0276
0277     /* Device operations */
0278     dw->set_device_name = idma32_set_device_name;
0279     dw->disable = idma32_disable;
0280     dw->enable = idma32_enable;
0281
0282     chip->dw = dw;
0283     return do_dma_probe(chip);
0284 }
0285 EXPORT_SYMBOL_GPL(idma32_dma_probe);
0286
0287 int idma32_dma_remove(struct dw_dma_chip *chip)
0288 {
0289     return do_dma_remove(chip);
0290 }
0291 EXPORT_SYMBOL_GPL(idma32_dma_remove);