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0001 // SPDX-License-Identifier: GPL-2.0
0002 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
0003 
0004 /*
0005  * Synopsys DesignWare AXI DMA Controller driver.
0006  *
0007  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
0008  */
0009 
0010 #include <linux/bitops.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/dmaengine.h>
0014 #include <linux/dmapool.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/err.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/iopoll.h>
0020 #include <linux/io-64-nonatomic-lo-hi.h>
0021 #include <linux/kernel.h>
0022 #include <linux/module.h>
0023 #include <linux/of.h>
0024 #include <linux/of_dma.h>
0025 #include <linux/platform_device.h>
0026 #include <linux/pm_runtime.h>
0027 #include <linux/property.h>
0028 #include <linux/slab.h>
0029 #include <linux/types.h>
0030 
0031 #include "dw-axi-dmac.h"
0032 #include "../dmaengine.h"
0033 #include "../virt-dma.h"
0034 
0035 /*
0036  * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
0037  * master data bus width up to 512 bits (for both AXI master interfaces), but
0038  * it depends on IP block configuration.
0039  */
0040 #define AXI_DMA_BUSWIDTHS         \
0041     (DMA_SLAVE_BUSWIDTH_1_BYTE  | \
0042     DMA_SLAVE_BUSWIDTH_2_BYTES  | \
0043     DMA_SLAVE_BUSWIDTH_4_BYTES  | \
0044     DMA_SLAVE_BUSWIDTH_8_BYTES  | \
0045     DMA_SLAVE_BUSWIDTH_16_BYTES | \
0046     DMA_SLAVE_BUSWIDTH_32_BYTES | \
0047     DMA_SLAVE_BUSWIDTH_64_BYTES)
0048 
0049 static inline void
0050 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
0051 {
0052     iowrite32(val, chip->regs + reg);
0053 }
0054 
0055 static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg)
0056 {
0057     return ioread32(chip->regs + reg);
0058 }
0059 
0060 static inline void
0061 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val)
0062 {
0063     iowrite32(val, chan->chan_regs + reg);
0064 }
0065 
0066 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg)
0067 {
0068     return ioread32(chan->chan_regs + reg);
0069 }
0070 
0071 static inline void
0072 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
0073 {
0074     /*
0075      * We split one 64 bit write for two 32 bit write as some HW doesn't
0076      * support 64 bit access.
0077      */
0078     iowrite32(lower_32_bits(val), chan->chan_regs + reg);
0079     iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4);
0080 }
0081 
0082 static inline void axi_chan_config_write(struct axi_dma_chan *chan,
0083                      struct axi_dma_chan_config *config)
0084 {
0085     u32 cfg_lo, cfg_hi;
0086 
0087     cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
0088           config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
0089     if (chan->chip->dw->hdata->reg_map_8_channels) {
0090         cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
0091              config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
0092              config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
0093              config->src_per << CH_CFG_H_SRC_PER_POS |
0094              config->dst_per << CH_CFG_H_DST_PER_POS |
0095              config->prior << CH_CFG_H_PRIORITY_POS;
0096     } else {
0097         cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS |
0098               config->dst_per << CH_CFG2_L_DST_PER_POS;
0099         cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS |
0100              config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS |
0101              config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS |
0102              config->prior << CH_CFG2_H_PRIORITY_POS;
0103     }
0104     axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo);
0105     axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi);
0106 }
0107 
0108 static inline void axi_dma_disable(struct axi_dma_chip *chip)
0109 {
0110     u32 val;
0111 
0112     val = axi_dma_ioread32(chip, DMAC_CFG);
0113     val &= ~DMAC_EN_MASK;
0114     axi_dma_iowrite32(chip, DMAC_CFG, val);
0115 }
0116 
0117 static inline void axi_dma_enable(struct axi_dma_chip *chip)
0118 {
0119     u32 val;
0120 
0121     val = axi_dma_ioread32(chip, DMAC_CFG);
0122     val |= DMAC_EN_MASK;
0123     axi_dma_iowrite32(chip, DMAC_CFG, val);
0124 }
0125 
0126 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip)
0127 {
0128     u32 val;
0129 
0130     val = axi_dma_ioread32(chip, DMAC_CFG);
0131     val &= ~INT_EN_MASK;
0132     axi_dma_iowrite32(chip, DMAC_CFG, val);
0133 }
0134 
0135 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip)
0136 {
0137     u32 val;
0138 
0139     val = axi_dma_ioread32(chip, DMAC_CFG);
0140     val |= INT_EN_MASK;
0141     axi_dma_iowrite32(chip, DMAC_CFG, val);
0142 }
0143 
0144 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask)
0145 {
0146     u32 val;
0147 
0148     if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) {
0149         axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE);
0150     } else {
0151         val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA);
0152         val &= ~irq_mask;
0153         axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val);
0154     }
0155 }
0156 
0157 static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask)
0158 {
0159     axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask);
0160 }
0161 
0162 static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask)
0163 {
0164     axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask);
0165 }
0166 
0167 static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask)
0168 {
0169     axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask);
0170 }
0171 
0172 static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan)
0173 {
0174     return axi_chan_ioread32(chan, CH_INTSTATUS);
0175 }
0176 
0177 static inline void axi_chan_disable(struct axi_dma_chan *chan)
0178 {
0179     u32 val;
0180 
0181     val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
0182     val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
0183     if (chan->chip->dw->hdata->reg_map_8_channels)
0184         val |=   BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
0185     else
0186         val |=   BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
0187     axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
0188 }
0189 
0190 static inline void axi_chan_enable(struct axi_dma_chan *chan)
0191 {
0192     u32 val;
0193 
0194     val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
0195     if (chan->chip->dw->hdata->reg_map_8_channels)
0196         val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
0197             BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
0198     else
0199         val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
0200             BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
0201     axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
0202 }
0203 
0204 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
0205 {
0206     u32 val;
0207 
0208     val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
0209 
0210     return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT));
0211 }
0212 
0213 static void axi_dma_hw_init(struct axi_dma_chip *chip)
0214 {
0215     int ret;
0216     u32 i;
0217 
0218     for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
0219         axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
0220         axi_chan_disable(&chip->dw->chan[i]);
0221     }
0222     ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
0223     if (ret)
0224         dev_warn(chip->dev, "Unable to set coherent mask\n");
0225 }
0226 
0227 static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,
0228                    dma_addr_t dst, size_t len)
0229 {
0230     u32 max_width = chan->chip->dw->hdata->m_data_width;
0231 
0232     return __ffs(src | dst | len | BIT(max_width));
0233 }
0234 
0235 static inline const char *axi_chan_name(struct axi_dma_chan *chan)
0236 {
0237     return dma_chan_name(&chan->vc.chan);
0238 }
0239 
0240 static struct axi_dma_desc *axi_desc_alloc(u32 num)
0241 {
0242     struct axi_dma_desc *desc;
0243 
0244     desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
0245     if (!desc)
0246         return NULL;
0247 
0248     desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
0249     if (!desc->hw_desc) {
0250         kfree(desc);
0251         return NULL;
0252     }
0253 
0254     return desc;
0255 }
0256 
0257 static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
0258                     dma_addr_t *addr)
0259 {
0260     struct axi_dma_lli *lli;
0261     dma_addr_t phys;
0262 
0263     lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
0264     if (unlikely(!lli)) {
0265         dev_err(chan2dev(chan), "%s: not enough descriptors available\n",
0266             axi_chan_name(chan));
0267         return NULL;
0268     }
0269 
0270     atomic_inc(&chan->descs_allocated);
0271     *addr = phys;
0272 
0273     return lli;
0274 }
0275 
0276 static void axi_desc_put(struct axi_dma_desc *desc)
0277 {
0278     struct axi_dma_chan *chan = desc->chan;
0279     int count = atomic_read(&chan->descs_allocated);
0280     struct axi_dma_hw_desc *hw_desc;
0281     int descs_put;
0282 
0283     for (descs_put = 0; descs_put < count; descs_put++) {
0284         hw_desc = &desc->hw_desc[descs_put];
0285         dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
0286     }
0287 
0288     kfree(desc->hw_desc);
0289     kfree(desc);
0290     atomic_sub(descs_put, &chan->descs_allocated);
0291     dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
0292         axi_chan_name(chan), descs_put,
0293         atomic_read(&chan->descs_allocated));
0294 }
0295 
0296 static void vchan_desc_put(struct virt_dma_desc *vdesc)
0297 {
0298     axi_desc_put(vd_to_axi_desc(vdesc));
0299 }
0300 
0301 static enum dma_status
0302 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
0303           struct dma_tx_state *txstate)
0304 {
0305     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0306     struct virt_dma_desc *vdesc;
0307     enum dma_status status;
0308     u32 completed_length;
0309     unsigned long flags;
0310     u32 completed_blocks;
0311     size_t bytes = 0;
0312     u32 length;
0313     u32 len;
0314 
0315     status = dma_cookie_status(dchan, cookie, txstate);
0316     if (status == DMA_COMPLETE || !txstate)
0317         return status;
0318 
0319     spin_lock_irqsave(&chan->vc.lock, flags);
0320 
0321     vdesc = vchan_find_desc(&chan->vc, cookie);
0322     if (vdesc) {
0323         length = vd_to_axi_desc(vdesc)->length;
0324         completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
0325         len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
0326         completed_length = completed_blocks * len;
0327         bytes = length - completed_length;
0328     } else {
0329         bytes = vd_to_axi_desc(vdesc)->length;
0330     }
0331 
0332     spin_unlock_irqrestore(&chan->vc.lock, flags);
0333     dma_set_residue(txstate, bytes);
0334 
0335     return status;
0336 }
0337 
0338 static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
0339 {
0340     desc->lli->llp = cpu_to_le64(adr);
0341 }
0342 
0343 static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
0344 {
0345     axi_chan_iowrite64(chan, CH_LLP, adr);
0346 }
0347 
0348 static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
0349 {
0350     u32 offset = DMAC_APB_BYTE_WR_CH_EN;
0351     u32 reg_width, val;
0352 
0353     if (!chan->chip->apb_regs) {
0354         dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
0355         return;
0356     }
0357 
0358     reg_width = __ffs(chan->config.dst_addr_width);
0359     if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
0360         offset = DMAC_APB_HALFWORD_WR_CH_EN;
0361 
0362     val = ioread32(chan->chip->apb_regs + offset);
0363 
0364     if (set)
0365         val |= BIT(chan->id);
0366     else
0367         val &= ~BIT(chan->id);
0368 
0369     iowrite32(val, chan->chip->apb_regs + offset);
0370 }
0371 /* Called in chan locked context */
0372 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
0373                       struct axi_dma_desc *first)
0374 {
0375     u32 priority = chan->chip->dw->hdata->priority[chan->id];
0376     struct axi_dma_chan_config config = {};
0377     u32 irq_mask;
0378     u8 lms = 0; /* Select AXI0 master for LLI fetching */
0379 
0380     if (unlikely(axi_chan_is_hw_enable(chan))) {
0381         dev_err(chan2dev(chan), "%s is non-idle!\n",
0382             axi_chan_name(chan));
0383 
0384         return;
0385     }
0386 
0387     axi_dma_enable(chan->chip);
0388 
0389     config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
0390     config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
0391     config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC;
0392     config.prior = priority;
0393     config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
0394     config.hs_sel_src = DWAXIDMAC_HS_SEL_HW;
0395     switch (chan->direction) {
0396     case DMA_MEM_TO_DEV:
0397         dw_axi_dma_set_byte_halfword(chan, true);
0398         config.tt_fc = chan->config.device_fc ?
0399                 DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
0400                 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC;
0401         if (chan->chip->apb_regs)
0402             config.dst_per = chan->id;
0403         else
0404             config.dst_per = chan->hw_handshake_num;
0405         break;
0406     case DMA_DEV_TO_MEM:
0407         config.tt_fc = chan->config.device_fc ?
0408                 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
0409                 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC;
0410         if (chan->chip->apb_regs)
0411             config.src_per = chan->id;
0412         else
0413             config.src_per = chan->hw_handshake_num;
0414         break;
0415     default:
0416         break;
0417     }
0418     axi_chan_config_write(chan, &config);
0419 
0420     write_chan_llp(chan, first->hw_desc[0].llp | lms);
0421 
0422     irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
0423     axi_chan_irq_sig_set(chan, irq_mask);
0424 
0425     /* Generate 'suspend' status but don't generate interrupt */
0426     irq_mask |= DWAXIDMAC_IRQ_SUSPENDED;
0427     axi_chan_irq_set(chan, irq_mask);
0428 
0429     axi_chan_enable(chan);
0430 }
0431 
0432 static void axi_chan_start_first_queued(struct axi_dma_chan *chan)
0433 {
0434     struct axi_dma_desc *desc;
0435     struct virt_dma_desc *vd;
0436 
0437     vd = vchan_next_desc(&chan->vc);
0438     if (!vd)
0439         return;
0440 
0441     desc = vd_to_axi_desc(vd);
0442     dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan),
0443         vd->tx.cookie);
0444     axi_chan_block_xfer_start(chan, desc);
0445 }
0446 
0447 static void dma_chan_issue_pending(struct dma_chan *dchan)
0448 {
0449     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0450     unsigned long flags;
0451 
0452     spin_lock_irqsave(&chan->vc.lock, flags);
0453     if (vchan_issue_pending(&chan->vc))
0454         axi_chan_start_first_queued(chan);
0455     spin_unlock_irqrestore(&chan->vc.lock, flags);
0456 }
0457 
0458 static void dw_axi_dma_synchronize(struct dma_chan *dchan)
0459 {
0460     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0461 
0462     vchan_synchronize(&chan->vc);
0463 }
0464 
0465 static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
0466 {
0467     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0468 
0469     /* ASSERT: channel is idle */
0470     if (axi_chan_is_hw_enable(chan)) {
0471         dev_err(chan2dev(chan), "%s is non-idle!\n",
0472             axi_chan_name(chan));
0473         return -EBUSY;
0474     }
0475 
0476     /* LLI address must be aligned to a 64-byte boundary */
0477     chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
0478                       chan->chip->dev,
0479                       sizeof(struct axi_dma_lli),
0480                       64, 0);
0481     if (!chan->desc_pool) {
0482         dev_err(chan2dev(chan), "No memory for descriptors\n");
0483         return -ENOMEM;
0484     }
0485     dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
0486 
0487     pm_runtime_get(chan->chip->dev);
0488 
0489     return 0;
0490 }
0491 
0492 static void dma_chan_free_chan_resources(struct dma_chan *dchan)
0493 {
0494     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0495 
0496     /* ASSERT: channel is idle */
0497     if (axi_chan_is_hw_enable(chan))
0498         dev_err(dchan2dev(dchan), "%s is non-idle!\n",
0499             axi_chan_name(chan));
0500 
0501     axi_chan_disable(chan);
0502     axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL);
0503 
0504     vchan_free_chan_resources(&chan->vc);
0505 
0506     dma_pool_destroy(chan->desc_pool);
0507     chan->desc_pool = NULL;
0508     dev_vdbg(dchan2dev(dchan),
0509          "%s: free resources, descriptor still allocated: %u\n",
0510          axi_chan_name(chan), atomic_read(&chan->descs_allocated));
0511 
0512     pm_runtime_put(chan->chip->dev);
0513 }
0514 
0515 static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
0516 {
0517     struct axi_dma_chip *chip = chan->chip;
0518     unsigned long reg_value, val;
0519 
0520     if (!chip->apb_regs) {
0521         dev_err(chip->dev, "apb_regs not initialized\n");
0522         return;
0523     }
0524 
0525     /*
0526      * An unused DMA channel has a default value of 0x3F.
0527      * Lock the DMA channel by assign a handshake number to the channel.
0528      * Unlock the DMA channel by assign 0x3F to the channel.
0529      */
0530     if (set)
0531         val = chan->hw_handshake_num;
0532     else
0533         val = UNUSED_CHANNEL;
0534 
0535     reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
0536 
0537     /* Channel is already allocated, set handshake as per channel ID */
0538     /* 64 bit write should handle for 8 channels */
0539 
0540     reg_value &= ~(DMA_APB_HS_SEL_MASK <<
0541             (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
0542     reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
0543     lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
0544 
0545     return;
0546 }
0547 
0548 /*
0549  * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
0550  * as 1, it understands that the current block is the final block in the
0551  * transfer and completes the DMA transfer operation at the end of current
0552  * block transfer.
0553  */
0554 static void set_desc_last(struct axi_dma_hw_desc *desc)
0555 {
0556     u32 val;
0557 
0558     val = le32_to_cpu(desc->lli->ctl_hi);
0559     val |= CH_CTL_H_LLI_LAST;
0560     desc->lli->ctl_hi = cpu_to_le32(val);
0561 }
0562 
0563 static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
0564 {
0565     desc->lli->sar = cpu_to_le64(adr);
0566 }
0567 
0568 static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
0569 {
0570     desc->lli->dar = cpu_to_le64(adr);
0571 }
0572 
0573 static void set_desc_src_master(struct axi_dma_hw_desc *desc)
0574 {
0575     u32 val;
0576 
0577     /* Select AXI0 for source master */
0578     val = le32_to_cpu(desc->lli->ctl_lo);
0579     val &= ~CH_CTL_L_SRC_MAST;
0580     desc->lli->ctl_lo = cpu_to_le32(val);
0581 }
0582 
0583 static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
0584                  struct axi_dma_desc *desc)
0585 {
0586     u32 val;
0587 
0588     /* Select AXI1 for source master if available */
0589     val = le32_to_cpu(hw_desc->lli->ctl_lo);
0590     if (desc->chan->chip->dw->hdata->nr_masters > 1)
0591         val |= CH_CTL_L_DST_MAST;
0592     else
0593         val &= ~CH_CTL_L_DST_MAST;
0594 
0595     hw_desc->lli->ctl_lo = cpu_to_le32(val);
0596 }
0597 
0598 static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
0599                   struct axi_dma_hw_desc *hw_desc,
0600                   dma_addr_t mem_addr, size_t len)
0601 {
0602     unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
0603     unsigned int reg_width;
0604     unsigned int mem_width;
0605     dma_addr_t device_addr;
0606     size_t axi_block_ts;
0607     size_t block_ts;
0608     u32 ctllo, ctlhi;
0609     u32 burst_len;
0610 
0611     axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
0612 
0613     mem_width = __ffs(data_width | mem_addr | len);
0614     if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
0615         mem_width = DWAXIDMAC_TRANS_WIDTH_32;
0616 
0617     if (!IS_ALIGNED(mem_addr, 4)) {
0618         dev_err(chan->chip->dev, "invalid buffer alignment\n");
0619         return -EINVAL;
0620     }
0621 
0622     switch (chan->direction) {
0623     case DMA_MEM_TO_DEV:
0624         reg_width = __ffs(chan->config.dst_addr_width);
0625         device_addr = chan->config.dst_addr;
0626         ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
0627             mem_width << CH_CTL_L_SRC_WIDTH_POS |
0628             DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
0629             DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
0630         block_ts = len >> mem_width;
0631         break;
0632     case DMA_DEV_TO_MEM:
0633         reg_width = __ffs(chan->config.src_addr_width);
0634         device_addr = chan->config.src_addr;
0635         ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
0636             mem_width << CH_CTL_L_DST_WIDTH_POS |
0637             DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
0638             DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
0639         block_ts = len >> reg_width;
0640         break;
0641     default:
0642         return -EINVAL;
0643     }
0644 
0645     if (block_ts > axi_block_ts)
0646         return -EINVAL;
0647 
0648     hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
0649     if (unlikely(!hw_desc->lli))
0650         return -ENOMEM;
0651 
0652     ctlhi = CH_CTL_H_LLI_VALID;
0653 
0654     if (chan->chip->dw->hdata->restrict_axi_burst_len) {
0655         burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
0656         ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
0657              burst_len << CH_CTL_H_ARLEN_POS |
0658              burst_len << CH_CTL_H_AWLEN_POS;
0659     }
0660 
0661     hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
0662 
0663     if (chan->direction == DMA_MEM_TO_DEV) {
0664         write_desc_sar(hw_desc, mem_addr);
0665         write_desc_dar(hw_desc, device_addr);
0666     } else {
0667         write_desc_sar(hw_desc, device_addr);
0668         write_desc_dar(hw_desc, mem_addr);
0669     }
0670 
0671     hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
0672 
0673     ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
0674          DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
0675     hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
0676 
0677     set_desc_src_master(hw_desc);
0678 
0679     hw_desc->len = len;
0680     return 0;
0681 }
0682 
0683 static size_t calculate_block_len(struct axi_dma_chan *chan,
0684                   dma_addr_t dma_addr, size_t buf_len,
0685                   enum dma_transfer_direction direction)
0686 {
0687     u32 data_width, reg_width, mem_width;
0688     size_t axi_block_ts, block_len;
0689 
0690     axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
0691 
0692     switch (direction) {
0693     case DMA_MEM_TO_DEV:
0694         data_width = BIT(chan->chip->dw->hdata->m_data_width);
0695         mem_width = __ffs(data_width | dma_addr | buf_len);
0696         if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
0697             mem_width = DWAXIDMAC_TRANS_WIDTH_32;
0698 
0699         block_len = axi_block_ts << mem_width;
0700         break;
0701     case DMA_DEV_TO_MEM:
0702         reg_width = __ffs(chan->config.src_addr_width);
0703         block_len = axi_block_ts << reg_width;
0704         break;
0705     default:
0706         block_len = 0;
0707     }
0708 
0709     return block_len;
0710 }
0711 
0712 static struct dma_async_tx_descriptor *
0713 dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
0714                 size_t buf_len, size_t period_len,
0715                 enum dma_transfer_direction direction,
0716                 unsigned long flags)
0717 {
0718     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0719     struct axi_dma_hw_desc *hw_desc = NULL;
0720     struct axi_dma_desc *desc = NULL;
0721     dma_addr_t src_addr = dma_addr;
0722     u32 num_periods, num_segments;
0723     size_t axi_block_len;
0724     u32 total_segments;
0725     u32 segment_len;
0726     unsigned int i;
0727     int status;
0728     u64 llp = 0;
0729     u8 lms = 0; /* Select AXI0 master for LLI fetching */
0730 
0731     num_periods = buf_len / period_len;
0732 
0733     axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
0734     if (axi_block_len == 0)
0735         return NULL;
0736 
0737     num_segments = DIV_ROUND_UP(period_len, axi_block_len);
0738     segment_len = DIV_ROUND_UP(period_len, num_segments);
0739 
0740     total_segments = num_periods * num_segments;
0741 
0742     desc = axi_desc_alloc(total_segments);
0743     if (unlikely(!desc))
0744         goto err_desc_get;
0745 
0746     chan->direction = direction;
0747     desc->chan = chan;
0748     chan->cyclic = true;
0749     desc->length = 0;
0750     desc->period_len = period_len;
0751 
0752     for (i = 0; i < total_segments; i++) {
0753         hw_desc = &desc->hw_desc[i];
0754 
0755         status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
0756                         segment_len);
0757         if (status < 0)
0758             goto err_desc_get;
0759 
0760         desc->length += hw_desc->len;
0761         /* Set end-of-link to the linked descriptor, so that cyclic
0762          * callback function can be triggered during interrupt.
0763          */
0764         set_desc_last(hw_desc);
0765 
0766         src_addr += segment_len;
0767     }
0768 
0769     llp = desc->hw_desc[0].llp;
0770 
0771     /* Managed transfer list */
0772     do {
0773         hw_desc = &desc->hw_desc[--total_segments];
0774         write_desc_llp(hw_desc, llp | lms);
0775         llp = hw_desc->llp;
0776     } while (total_segments);
0777 
0778     dw_axi_dma_set_hw_channel(chan, true);
0779 
0780     return vchan_tx_prep(&chan->vc, &desc->vd, flags);
0781 
0782 err_desc_get:
0783     if (desc)
0784         axi_desc_put(desc);
0785 
0786     return NULL;
0787 }
0788 
0789 static struct dma_async_tx_descriptor *
0790 dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
0791                   unsigned int sg_len,
0792                   enum dma_transfer_direction direction,
0793                   unsigned long flags, void *context)
0794 {
0795     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0796     struct axi_dma_hw_desc *hw_desc = NULL;
0797     struct axi_dma_desc *desc = NULL;
0798     u32 num_segments, segment_len;
0799     unsigned int loop = 0;
0800     struct scatterlist *sg;
0801     size_t axi_block_len;
0802     u32 len, num_sgs = 0;
0803     unsigned int i;
0804     dma_addr_t mem;
0805     int status;
0806     u64 llp = 0;
0807     u8 lms = 0; /* Select AXI0 master for LLI fetching */
0808 
0809     if (unlikely(!is_slave_direction(direction) || !sg_len))
0810         return NULL;
0811 
0812     mem = sg_dma_address(sgl);
0813     len = sg_dma_len(sgl);
0814 
0815     axi_block_len = calculate_block_len(chan, mem, len, direction);
0816     if (axi_block_len == 0)
0817         return NULL;
0818 
0819     for_each_sg(sgl, sg, sg_len, i)
0820         num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
0821 
0822     desc = axi_desc_alloc(num_sgs);
0823     if (unlikely(!desc))
0824         goto err_desc_get;
0825 
0826     desc->chan = chan;
0827     desc->length = 0;
0828     chan->direction = direction;
0829 
0830     for_each_sg(sgl, sg, sg_len, i) {
0831         mem = sg_dma_address(sg);
0832         len = sg_dma_len(sg);
0833         num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
0834         segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments);
0835 
0836         do {
0837             hw_desc = &desc->hw_desc[loop++];
0838             status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len);
0839             if (status < 0)
0840                 goto err_desc_get;
0841 
0842             desc->length += hw_desc->len;
0843             len -= segment_len;
0844             mem += segment_len;
0845         } while (len >= segment_len);
0846     }
0847 
0848     /* Set end-of-link to the last link descriptor of list */
0849     set_desc_last(&desc->hw_desc[num_sgs - 1]);
0850 
0851     /* Managed transfer list */
0852     do {
0853         hw_desc = &desc->hw_desc[--num_sgs];
0854         write_desc_llp(hw_desc, llp | lms);
0855         llp = hw_desc->llp;
0856     } while (num_sgs);
0857 
0858     dw_axi_dma_set_hw_channel(chan, true);
0859 
0860     return vchan_tx_prep(&chan->vc, &desc->vd, flags);
0861 
0862 err_desc_get:
0863     if (desc)
0864         axi_desc_put(desc);
0865 
0866     return NULL;
0867 }
0868 
0869 static struct dma_async_tx_descriptor *
0870 dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
0871              dma_addr_t src_adr, size_t len, unsigned long flags)
0872 {
0873     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0874     size_t block_ts, max_block_ts, xfer_len;
0875     struct axi_dma_hw_desc *hw_desc = NULL;
0876     struct axi_dma_desc *desc = NULL;
0877     u32 xfer_width, reg, num;
0878     u64 llp = 0;
0879     u8 lms = 0; /* Select AXI0 master for LLI fetching */
0880 
0881     dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx",
0882         axi_chan_name(chan), &src_adr, &dst_adr, len, flags);
0883 
0884     max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
0885     xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len);
0886     num = DIV_ROUND_UP(len, max_block_ts << xfer_width);
0887     desc = axi_desc_alloc(num);
0888     if (unlikely(!desc))
0889         goto err_desc_get;
0890 
0891     desc->chan = chan;
0892     num = 0;
0893     desc->length = 0;
0894     while (len) {
0895         xfer_len = len;
0896 
0897         hw_desc = &desc->hw_desc[num];
0898         /*
0899          * Take care for the alignment.
0900          * Actually source and destination widths can be different, but
0901          * make them same to be simpler.
0902          */
0903         xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len);
0904 
0905         /*
0906          * block_ts indicates the total number of data of width
0907          * to be transferred in a DMA block transfer.
0908          * BLOCK_TS register should be set to block_ts - 1
0909          */
0910         block_ts = xfer_len >> xfer_width;
0911         if (block_ts > max_block_ts) {
0912             block_ts = max_block_ts;
0913             xfer_len = max_block_ts << xfer_width;
0914         }
0915 
0916         hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
0917         if (unlikely(!hw_desc->lli))
0918             goto err_desc_get;
0919 
0920         write_desc_sar(hw_desc, src_adr);
0921         write_desc_dar(hw_desc, dst_adr);
0922         hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
0923 
0924         reg = CH_CTL_H_LLI_VALID;
0925         if (chan->chip->dw->hdata->restrict_axi_burst_len) {
0926             u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
0927 
0928             reg |= (CH_CTL_H_ARLEN_EN |
0929                 burst_len << CH_CTL_H_ARLEN_POS |
0930                 CH_CTL_H_AWLEN_EN |
0931                 burst_len << CH_CTL_H_AWLEN_POS);
0932         }
0933         hw_desc->lli->ctl_hi = cpu_to_le32(reg);
0934 
0935         reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
0936                DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS |
0937                xfer_width << CH_CTL_L_DST_WIDTH_POS |
0938                xfer_width << CH_CTL_L_SRC_WIDTH_POS |
0939                DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
0940                DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
0941         hw_desc->lli->ctl_lo = cpu_to_le32(reg);
0942 
0943         set_desc_src_master(hw_desc);
0944         set_desc_dest_master(hw_desc, desc);
0945 
0946         hw_desc->len = xfer_len;
0947         desc->length += hw_desc->len;
0948         /* update the length and addresses for the next loop cycle */
0949         len -= xfer_len;
0950         dst_adr += xfer_len;
0951         src_adr += xfer_len;
0952         num++;
0953     }
0954 
0955     /* Set end-of-link to the last link descriptor of list */
0956     set_desc_last(&desc->hw_desc[num - 1]);
0957     /* Managed transfer list */
0958     do {
0959         hw_desc = &desc->hw_desc[--num];
0960         write_desc_llp(hw_desc, llp | lms);
0961         llp = hw_desc->llp;
0962     } while (num);
0963 
0964     return vchan_tx_prep(&chan->vc, &desc->vd, flags);
0965 
0966 err_desc_get:
0967     if (desc)
0968         axi_desc_put(desc);
0969     return NULL;
0970 }
0971 
0972 static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
0973                     struct dma_slave_config *config)
0974 {
0975     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
0976 
0977     memcpy(&chan->config, config, sizeof(*config));
0978 
0979     return 0;
0980 }
0981 
0982 static void axi_chan_dump_lli(struct axi_dma_chan *chan,
0983                   struct axi_dma_hw_desc *desc)
0984 {
0985     if (!desc->lli) {
0986         dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n");
0987         return;
0988     }
0989 
0990     dev_err(dchan2dev(&chan->vc.chan),
0991         "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x",
0992         le64_to_cpu(desc->lli->sar),
0993         le64_to_cpu(desc->lli->dar),
0994         le64_to_cpu(desc->lli->llp),
0995         le32_to_cpu(desc->lli->block_ts_lo),
0996         le32_to_cpu(desc->lli->ctl_hi),
0997         le32_to_cpu(desc->lli->ctl_lo));
0998 }
0999 
1000 static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,
1001                    struct axi_dma_desc *desc_head)
1002 {
1003     int count = atomic_read(&chan->descs_allocated);
1004     int i;
1005 
1006     for (i = 0; i < count; i++)
1007         axi_chan_dump_lli(chan, &desc_head->hw_desc[i]);
1008 }
1009 
1010 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
1011 {
1012     struct virt_dma_desc *vd;
1013     unsigned long flags;
1014 
1015     spin_lock_irqsave(&chan->vc.lock, flags);
1016 
1017     axi_chan_disable(chan);
1018 
1019     /* The bad descriptor currently is in the head of vc list */
1020     vd = vchan_next_desc(&chan->vc);
1021     /* Remove the completed descriptor from issued list */
1022     list_del(&vd->node);
1023 
1024     /* WARN about bad descriptor */
1025     dev_err(chan2dev(chan),
1026         "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n",
1027         axi_chan_name(chan), vd->tx.cookie, status);
1028     axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd));
1029 
1030     vchan_cookie_complete(vd);
1031 
1032     /* Try to restart the controller */
1033     axi_chan_start_first_queued(chan);
1034 
1035     spin_unlock_irqrestore(&chan->vc.lock, flags);
1036 }
1037 
1038 static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
1039 {
1040     int count = atomic_read(&chan->descs_allocated);
1041     struct axi_dma_hw_desc *hw_desc;
1042     struct axi_dma_desc *desc;
1043     struct virt_dma_desc *vd;
1044     unsigned long flags;
1045     u64 llp;
1046     int i;
1047 
1048     spin_lock_irqsave(&chan->vc.lock, flags);
1049     if (unlikely(axi_chan_is_hw_enable(chan))) {
1050         dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n",
1051             axi_chan_name(chan));
1052         axi_chan_disable(chan);
1053     }
1054 
1055     /* The completed descriptor currently is in the head of vc list */
1056     vd = vchan_next_desc(&chan->vc);
1057     if (!vd) {
1058         dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n",
1059             axi_chan_name(chan));
1060         goto out;
1061     }
1062 
1063     if (chan->cyclic) {
1064         desc = vd_to_axi_desc(vd);
1065         if (desc) {
1066             llp = lo_hi_readq(chan->chan_regs + CH_LLP);
1067             for (i = 0; i < count; i++) {
1068                 hw_desc = &desc->hw_desc[i];
1069                 if (hw_desc->llp == llp) {
1070                     axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
1071                     hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
1072                     desc->completed_blocks = i;
1073 
1074                     if (((hw_desc->len * (i + 1)) % desc->period_len) == 0)
1075                         vchan_cyclic_callback(vd);
1076                     break;
1077                 }
1078             }
1079 
1080             axi_chan_enable(chan);
1081         }
1082     } else {
1083         /* Remove the completed descriptor from issued list before completing */
1084         list_del(&vd->node);
1085         vchan_cookie_complete(vd);
1086 
1087         /* Submit queued descriptors after processing the completed ones */
1088         axi_chan_start_first_queued(chan);
1089     }
1090 
1091 out:
1092     spin_unlock_irqrestore(&chan->vc.lock, flags);
1093 }
1094 
1095 static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
1096 {
1097     struct axi_dma_chip *chip = dev_id;
1098     struct dw_axi_dma *dw = chip->dw;
1099     struct axi_dma_chan *chan;
1100 
1101     u32 status, i;
1102 
1103     /* Disable DMAC interrupts. We'll enable them after processing channels */
1104     axi_dma_irq_disable(chip);
1105 
1106     /* Poll, clear and process every channel interrupt status */
1107     for (i = 0; i < dw->hdata->nr_channels; i++) {
1108         chan = &dw->chan[i];
1109         status = axi_chan_irq_read(chan);
1110         axi_chan_irq_clear(chan, status);
1111 
1112         dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n",
1113             axi_chan_name(chan), i, status);
1114 
1115         if (status & DWAXIDMAC_IRQ_ALL_ERR)
1116             axi_chan_handle_err(chan, status);
1117         else if (status & DWAXIDMAC_IRQ_DMA_TRF)
1118             axi_chan_block_xfer_complete(chan);
1119     }
1120 
1121     /* Re-enable interrupts */
1122     axi_dma_irq_enable(chip);
1123 
1124     return IRQ_HANDLED;
1125 }
1126 
1127 static int dma_chan_terminate_all(struct dma_chan *dchan)
1128 {
1129     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1130     u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
1131     unsigned long flags;
1132     u32 val;
1133     int ret;
1134     LIST_HEAD(head);
1135 
1136     axi_chan_disable(chan);
1137 
1138     ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
1139                     !(val & chan_active), 1000, 10000);
1140     if (ret == -ETIMEDOUT)
1141         dev_warn(dchan2dev(dchan),
1142              "%s failed to stop\n", axi_chan_name(chan));
1143 
1144     if (chan->direction != DMA_MEM_TO_MEM)
1145         dw_axi_dma_set_hw_channel(chan, false);
1146     if (chan->direction == DMA_MEM_TO_DEV)
1147         dw_axi_dma_set_byte_halfword(chan, false);
1148 
1149     spin_lock_irqsave(&chan->vc.lock, flags);
1150 
1151     vchan_get_all_descriptors(&chan->vc, &head);
1152 
1153     chan->cyclic = false;
1154     spin_unlock_irqrestore(&chan->vc.lock, flags);
1155 
1156     vchan_dma_desc_free_list(&chan->vc, &head);
1157 
1158     dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan));
1159 
1160     return 0;
1161 }
1162 
1163 static int dma_chan_pause(struct dma_chan *dchan)
1164 {
1165     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1166     unsigned long flags;
1167     unsigned int timeout = 20; /* timeout iterations */
1168     u32 val;
1169 
1170     spin_lock_irqsave(&chan->vc.lock, flags);
1171 
1172     if (chan->chip->dw->hdata->reg_map_8_channels) {
1173         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1174         val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
1175             BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
1176         axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1177     } else {
1178         val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1179         val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
1180             BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
1181         axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1182     }
1183 
1184     do  {
1185         if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED)
1186             break;
1187 
1188         udelay(2);
1189     } while (--timeout);
1190 
1191     axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED);
1192 
1193     chan->is_paused = true;
1194 
1195     spin_unlock_irqrestore(&chan->vc.lock, flags);
1196 
1197     return timeout ? 0 : -EAGAIN;
1198 }
1199 
1200 /* Called in chan locked context */
1201 static inline void axi_chan_resume(struct axi_dma_chan *chan)
1202 {
1203     u32 val;
1204 
1205     if (chan->chip->dw->hdata->reg_map_8_channels) {
1206         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1207         val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
1208         val |=  (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
1209         axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1210     } else {
1211         val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1212         val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
1213         val |=  (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
1214         axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1215     }
1216 
1217     chan->is_paused = false;
1218 }
1219 
1220 static int dma_chan_resume(struct dma_chan *dchan)
1221 {
1222     struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1223     unsigned long flags;
1224 
1225     spin_lock_irqsave(&chan->vc.lock, flags);
1226 
1227     if (chan->is_paused)
1228         axi_chan_resume(chan);
1229 
1230     spin_unlock_irqrestore(&chan->vc.lock, flags);
1231 
1232     return 0;
1233 }
1234 
1235 static int axi_dma_suspend(struct axi_dma_chip *chip)
1236 {
1237     axi_dma_irq_disable(chip);
1238     axi_dma_disable(chip);
1239 
1240     clk_disable_unprepare(chip->core_clk);
1241     clk_disable_unprepare(chip->cfgr_clk);
1242 
1243     return 0;
1244 }
1245 
1246 static int axi_dma_resume(struct axi_dma_chip *chip)
1247 {
1248     int ret;
1249 
1250     ret = clk_prepare_enable(chip->cfgr_clk);
1251     if (ret < 0)
1252         return ret;
1253 
1254     ret = clk_prepare_enable(chip->core_clk);
1255     if (ret < 0)
1256         return ret;
1257 
1258     axi_dma_enable(chip);
1259     axi_dma_irq_enable(chip);
1260 
1261     return 0;
1262 }
1263 
1264 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev)
1265 {
1266     struct axi_dma_chip *chip = dev_get_drvdata(dev);
1267 
1268     return axi_dma_suspend(chip);
1269 }
1270 
1271 static int __maybe_unused axi_dma_runtime_resume(struct device *dev)
1272 {
1273     struct axi_dma_chip *chip = dev_get_drvdata(dev);
1274 
1275     return axi_dma_resume(chip);
1276 }
1277 
1278 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
1279                         struct of_dma *ofdma)
1280 {
1281     struct dw_axi_dma *dw = ofdma->of_dma_data;
1282     struct axi_dma_chan *chan;
1283     struct dma_chan *dchan;
1284 
1285     dchan = dma_get_any_slave_channel(&dw->dma);
1286     if (!dchan)
1287         return NULL;
1288 
1289     chan = dchan_to_axi_dma_chan(dchan);
1290     chan->hw_handshake_num = dma_spec->args[0];
1291     return dchan;
1292 }
1293 
1294 static int parse_device_properties(struct axi_dma_chip *chip)
1295 {
1296     struct device *dev = chip->dev;
1297     u32 tmp, carr[DMAC_MAX_CHANNELS];
1298     int ret;
1299 
1300     ret = device_property_read_u32(dev, "dma-channels", &tmp);
1301     if (ret)
1302         return ret;
1303     if (tmp == 0 || tmp > DMAC_MAX_CHANNELS)
1304         return -EINVAL;
1305 
1306     chip->dw->hdata->nr_channels = tmp;
1307     if (tmp <= DMA_REG_MAP_CH_REF)
1308         chip->dw->hdata->reg_map_8_channels = true;
1309 
1310     ret = device_property_read_u32(dev, "snps,dma-masters", &tmp);
1311     if (ret)
1312         return ret;
1313     if (tmp == 0 || tmp > DMAC_MAX_MASTERS)
1314         return -EINVAL;
1315 
1316     chip->dw->hdata->nr_masters = tmp;
1317 
1318     ret = device_property_read_u32(dev, "snps,data-width", &tmp);
1319     if (ret)
1320         return ret;
1321     if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX)
1322         return -EINVAL;
1323 
1324     chip->dw->hdata->m_data_width = tmp;
1325 
1326     ret = device_property_read_u32_array(dev, "snps,block-size", carr,
1327                          chip->dw->hdata->nr_channels);
1328     if (ret)
1329         return ret;
1330     for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1331         if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE)
1332             return -EINVAL;
1333 
1334         chip->dw->hdata->block_size[tmp] = carr[tmp];
1335     }
1336 
1337     ret = device_property_read_u32_array(dev, "snps,priority", carr,
1338                          chip->dw->hdata->nr_channels);
1339     if (ret)
1340         return ret;
1341     /* Priority value must be programmed within [0:nr_channels-1] range */
1342     for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1343         if (carr[tmp] >= chip->dw->hdata->nr_channels)
1344             return -EINVAL;
1345 
1346         chip->dw->hdata->priority[tmp] = carr[tmp];
1347     }
1348 
1349     /* axi-max-burst-len is optional property */
1350     ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp);
1351     if (!ret) {
1352         if (tmp > DWAXIDMAC_ARWLEN_MAX + 1)
1353             return -EINVAL;
1354         if (tmp < DWAXIDMAC_ARWLEN_MIN + 1)
1355             return -EINVAL;
1356 
1357         chip->dw->hdata->restrict_axi_burst_len = true;
1358         chip->dw->hdata->axi_rw_burst_len = tmp;
1359     }
1360 
1361     return 0;
1362 }
1363 
1364 static int dw_probe(struct platform_device *pdev)
1365 {
1366     struct device_node *node = pdev->dev.of_node;
1367     struct axi_dma_chip *chip;
1368     struct resource *mem;
1369     struct dw_axi_dma *dw;
1370     struct dw_axi_dma_hcfg *hdata;
1371     u32 i;
1372     int ret;
1373 
1374     chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1375     if (!chip)
1376         return -ENOMEM;
1377 
1378     dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
1379     if (!dw)
1380         return -ENOMEM;
1381 
1382     hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL);
1383     if (!hdata)
1384         return -ENOMEM;
1385 
1386     chip->dw = dw;
1387     chip->dev = &pdev->dev;
1388     chip->dw->hdata = hdata;
1389 
1390     chip->irq = platform_get_irq(pdev, 0);
1391     if (chip->irq < 0)
1392         return chip->irq;
1393 
1394     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1395     chip->regs = devm_ioremap_resource(chip->dev, mem);
1396     if (IS_ERR(chip->regs))
1397         return PTR_ERR(chip->regs);
1398 
1399     if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
1400         chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
1401         if (IS_ERR(chip->apb_regs))
1402             return PTR_ERR(chip->apb_regs);
1403     }
1404 
1405     chip->core_clk = devm_clk_get(chip->dev, "core-clk");
1406     if (IS_ERR(chip->core_clk))
1407         return PTR_ERR(chip->core_clk);
1408 
1409     chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
1410     if (IS_ERR(chip->cfgr_clk))
1411         return PTR_ERR(chip->cfgr_clk);
1412 
1413     ret = parse_device_properties(chip);
1414     if (ret)
1415         return ret;
1416 
1417     dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
1418                 sizeof(*dw->chan), GFP_KERNEL);
1419     if (!dw->chan)
1420         return -ENOMEM;
1421 
1422     ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt,
1423                    IRQF_SHARED, KBUILD_MODNAME, chip);
1424     if (ret)
1425         return ret;
1426 
1427     INIT_LIST_HEAD(&dw->dma.channels);
1428     for (i = 0; i < hdata->nr_channels; i++) {
1429         struct axi_dma_chan *chan = &dw->chan[i];
1430 
1431         chan->chip = chip;
1432         chan->id = i;
1433         chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN;
1434         atomic_set(&chan->descs_allocated, 0);
1435 
1436         chan->vc.desc_free = vchan_desc_put;
1437         vchan_init(&chan->vc, &dw->dma);
1438     }
1439 
1440     /* Set capabilities */
1441     dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1442     dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1443     dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask);
1444 
1445     /* DMA capabilities */
1446     dw->dma.chancnt = hdata->nr_channels;
1447     dw->dma.max_burst = hdata->axi_rw_burst_len;
1448     dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
1449     dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
1450     dw->dma.directions = BIT(DMA_MEM_TO_MEM);
1451     dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1452     dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1453 
1454     dw->dma.dev = chip->dev;
1455     dw->dma.device_tx_status = dma_chan_tx_status;
1456     dw->dma.device_issue_pending = dma_chan_issue_pending;
1457     dw->dma.device_terminate_all = dma_chan_terminate_all;
1458     dw->dma.device_pause = dma_chan_pause;
1459     dw->dma.device_resume = dma_chan_resume;
1460 
1461     dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources;
1462     dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
1463 
1464     dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
1465     dw->dma.device_synchronize = dw_axi_dma_synchronize;
1466     dw->dma.device_config = dw_axi_dma_chan_slave_config;
1467     dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
1468     dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
1469 
1470     /*
1471      * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
1472      * supported blocks is 1024. Device register width is 4 bytes.
1473      * Therefore, set constraint to 1024 * 4.
1474      */
1475     dw->dma.dev->dma_parms = &dw->dma_parms;
1476     dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
1477     platform_set_drvdata(pdev, chip);
1478 
1479     pm_runtime_enable(chip->dev);
1480 
1481     /*
1482      * We can't just call pm_runtime_get here instead of
1483      * pm_runtime_get_noresume + axi_dma_resume because we need
1484      * driver to work also without Runtime PM.
1485      */
1486     pm_runtime_get_noresume(chip->dev);
1487     ret = axi_dma_resume(chip);
1488     if (ret < 0)
1489         goto err_pm_disable;
1490 
1491     axi_dma_hw_init(chip);
1492 
1493     pm_runtime_put(chip->dev);
1494 
1495     ret = dmaenginem_async_device_register(&dw->dma);
1496     if (ret)
1497         goto err_pm_disable;
1498 
1499     /* Register with OF helpers for DMA lookups */
1500     ret = of_dma_controller_register(pdev->dev.of_node,
1501                      dw_axi_dma_of_xlate, dw);
1502     if (ret < 0)
1503         dev_warn(&pdev->dev,
1504              "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n");
1505 
1506     dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
1507          dw->hdata->nr_channels);
1508 
1509     return 0;
1510 
1511 err_pm_disable:
1512     pm_runtime_disable(chip->dev);
1513 
1514     return ret;
1515 }
1516 
1517 static int dw_remove(struct platform_device *pdev)
1518 {
1519     struct axi_dma_chip *chip = platform_get_drvdata(pdev);
1520     struct dw_axi_dma *dw = chip->dw;
1521     struct axi_dma_chan *chan, *_chan;
1522     u32 i;
1523 
1524     /* Enable clk before accessing to registers */
1525     clk_prepare_enable(chip->cfgr_clk);
1526     clk_prepare_enable(chip->core_clk);
1527     axi_dma_irq_disable(chip);
1528     for (i = 0; i < dw->hdata->nr_channels; i++) {
1529         axi_chan_disable(&chip->dw->chan[i]);
1530         axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
1531     }
1532     axi_dma_disable(chip);
1533 
1534     pm_runtime_disable(chip->dev);
1535     axi_dma_suspend(chip);
1536 
1537     devm_free_irq(chip->dev, chip->irq, chip);
1538 
1539     of_dma_controller_free(chip->dev->of_node);
1540 
1541     list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
1542             vc.chan.device_node) {
1543         list_del(&chan->vc.chan.device_node);
1544         tasklet_kill(&chan->vc.task);
1545     }
1546 
1547     return 0;
1548 }
1549 
1550 static const struct dev_pm_ops dw_axi_dma_pm_ops = {
1551     SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL)
1552 };
1553 
1554 static const struct of_device_id dw_dma_of_id_table[] = {
1555     { .compatible = "snps,axi-dma-1.01a" },
1556     { .compatible = "intel,kmb-axi-dma" },
1557     {}
1558 };
1559 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
1560 
1561 static struct platform_driver dw_driver = {
1562     .probe      = dw_probe,
1563     .remove     = dw_remove,
1564     .driver = {
1565         .name   = KBUILD_MODNAME,
1566         .of_match_table = dw_dma_of_id_table,
1567         .pm = &dw_axi_dma_pm_ops,
1568     },
1569 };
1570 module_platform_driver(dw_driver);
1571 
1572 MODULE_LICENSE("GPL v2");
1573 MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver");
1574 MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
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