Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2017 Broadcom
0003 
0004 /*
0005  * Broadcom SBA RAID Driver
0006  *
0007  * The Broadcom stream buffer accelerator (SBA) provides offloading
0008  * capabilities for RAID operations. The SBA offload engine is accessible
0009  * via Broadcom SoC specific ring manager. Two or more offload engines
0010  * can share same Broadcom SoC specific ring manager due to this Broadcom
0011  * SoC specific ring manager driver is implemented as a mailbox controller
0012  * driver and offload engine drivers are implemented as mallbox clients.
0013  *
0014  * Typically, Broadcom SoC specific ring manager will implement larger
0015  * number of hardware rings over one or more SBA hardware devices. By
0016  * design, the internal buffer size of SBA hardware device is limited
0017  * but all offload operations supported by SBA can be broken down into
0018  * multiple small size requests and executed parallely on multiple SBA
0019  * hardware devices for achieving high through-put.
0020  *
0021  * The Broadcom SBA RAID driver does not require any register programming
0022  * except submitting request to SBA hardware device via mailbox channels.
0023  * This driver implements a DMA device with one DMA channel using a single
0024  * mailbox channel provided by Broadcom SoC specific ring manager driver.
0025  * For having more SBA DMA channels, we can create more SBA device nodes
0026  * in Broadcom SoC specific DTS based on number of hardware rings supported
0027  * by Broadcom SoC ring manager.
0028  */
0029 
0030 #include <linux/bitops.h>
0031 #include <linux/debugfs.h>
0032 #include <linux/dma-mapping.h>
0033 #include <linux/dmaengine.h>
0034 #include <linux/list.h>
0035 #include <linux/mailbox_client.h>
0036 #include <linux/mailbox/brcm-message.h>
0037 #include <linux/module.h>
0038 #include <linux/of_device.h>
0039 #include <linux/slab.h>
0040 #include <linux/raid/pq.h>
0041 
0042 #include "dmaengine.h"
0043 
0044 /* ====== Driver macros and defines ===== */
0045 
0046 #define SBA_TYPE_SHIFT                  48
0047 #define SBA_TYPE_MASK                   GENMASK(1, 0)
0048 #define SBA_TYPE_A                  0x0
0049 #define SBA_TYPE_B                  0x2
0050 #define SBA_TYPE_C                  0x3
0051 #define SBA_USER_DEF_SHIFT              32
0052 #define SBA_USER_DEF_MASK               GENMASK(15, 0)
0053 #define SBA_R_MDATA_SHIFT               24
0054 #define SBA_R_MDATA_MASK                GENMASK(7, 0)
0055 #define SBA_C_MDATA_MS_SHIFT                18
0056 #define SBA_C_MDATA_MS_MASK             GENMASK(1, 0)
0057 #define SBA_INT_SHIFT                   17
0058 #define SBA_INT_MASK                    BIT(0)
0059 #define SBA_RESP_SHIFT                  16
0060 #define SBA_RESP_MASK                   BIT(0)
0061 #define SBA_C_MDATA_SHIFT               8
0062 #define SBA_C_MDATA_MASK                GENMASK(7, 0)
0063 #define SBA_C_MDATA_BNUMx_SHIFT(__bnum)         (2 * (__bnum))
0064 #define SBA_C_MDATA_BNUMx_MASK              GENMASK(1, 0)
0065 #define SBA_C_MDATA_DNUM_SHIFT              5
0066 #define SBA_C_MDATA_DNUM_MASK               GENMASK(4, 0)
0067 #define SBA_C_MDATA_LS(__v)             ((__v) & 0xff)
0068 #define SBA_C_MDATA_MS(__v)             (((__v) >> 8) & 0x3)
0069 #define SBA_CMD_SHIFT                   0
0070 #define SBA_CMD_MASK                    GENMASK(3, 0)
0071 #define SBA_CMD_ZERO_BUFFER             0x4
0072 #define SBA_CMD_ZERO_ALL_BUFFERS            0x8
0073 #define SBA_CMD_LOAD_BUFFER             0x9
0074 #define SBA_CMD_XOR                 0xa
0075 #define SBA_CMD_GALOIS_XOR              0xb
0076 #define SBA_CMD_WRITE_BUFFER                0xc
0077 #define SBA_CMD_GALOIS                  0xe
0078 
0079 #define SBA_MAX_REQ_PER_MBOX_CHANNEL            8192
0080 #define SBA_MAX_MSG_SEND_PER_MBOX_CHANNEL       8
0081 
0082 /* Driver helper macros */
0083 #define to_sba_request(tx)      \
0084     container_of(tx, struct sba_request, tx)
0085 #define to_sba_device(dchan)        \
0086     container_of(dchan, struct sba_device, dma_chan)
0087 
0088 /* ===== Driver data structures ===== */
0089 
0090 enum sba_request_flags {
0091     SBA_REQUEST_STATE_FREE      = 0x001,
0092     SBA_REQUEST_STATE_ALLOCED   = 0x002,
0093     SBA_REQUEST_STATE_PENDING   = 0x004,
0094     SBA_REQUEST_STATE_ACTIVE    = 0x008,
0095     SBA_REQUEST_STATE_ABORTED   = 0x010,
0096     SBA_REQUEST_STATE_MASK      = 0x0ff,
0097     SBA_REQUEST_FENCE       = 0x100,
0098 };
0099 
0100 struct sba_request {
0101     /* Global state */
0102     struct list_head node;
0103     struct sba_device *sba;
0104     u32 flags;
0105     /* Chained requests management */
0106     struct sba_request *first;
0107     struct list_head next;
0108     atomic_t next_pending_count;
0109     /* BRCM message data */
0110     struct brcm_message msg;
0111     struct dma_async_tx_descriptor tx;
0112     /* SBA commands */
0113     struct brcm_sba_command cmds[];
0114 };
0115 
0116 enum sba_version {
0117     SBA_VER_1 = 0,
0118     SBA_VER_2
0119 };
0120 
0121 struct sba_device {
0122     /* Underlying device */
0123     struct device *dev;
0124     /* DT configuration parameters */
0125     enum sba_version ver;
0126     /* Derived configuration parameters */
0127     u32 max_req;
0128     u32 hw_buf_size;
0129     u32 hw_resp_size;
0130     u32 max_pq_coefs;
0131     u32 max_pq_srcs;
0132     u32 max_cmd_per_req;
0133     u32 max_xor_srcs;
0134     u32 max_resp_pool_size;
0135     u32 max_cmds_pool_size;
0136     /* Maibox client and Mailbox channels */
0137     struct mbox_client client;
0138     struct mbox_chan *mchan;
0139     struct device *mbox_dev;
0140     /* DMA device and DMA channel */
0141     struct dma_device dma_dev;
0142     struct dma_chan dma_chan;
0143     /* DMA channel resources */
0144     void *resp_base;
0145     dma_addr_t resp_dma_base;
0146     void *cmds_base;
0147     dma_addr_t cmds_dma_base;
0148     spinlock_t reqs_lock;
0149     bool reqs_fence;
0150     struct list_head reqs_alloc_list;
0151     struct list_head reqs_pending_list;
0152     struct list_head reqs_active_list;
0153     struct list_head reqs_aborted_list;
0154     struct list_head reqs_free_list;
0155     /* DebugFS directory entries */
0156     struct dentry *root;
0157 };
0158 
0159 /* ====== Command helper routines ===== */
0160 
0161 static inline u64 __pure sba_cmd_enc(u64 cmd, u32 val, u32 shift, u32 mask)
0162 {
0163     cmd &= ~((u64)mask << shift);
0164     cmd |= ((u64)(val & mask) << shift);
0165     return cmd;
0166 }
0167 
0168 static inline u32 __pure sba_cmd_load_c_mdata(u32 b0)
0169 {
0170     return b0 & SBA_C_MDATA_BNUMx_MASK;
0171 }
0172 
0173 static inline u32 __pure sba_cmd_write_c_mdata(u32 b0)
0174 {
0175     return b0 & SBA_C_MDATA_BNUMx_MASK;
0176 }
0177 
0178 static inline u32 __pure sba_cmd_xor_c_mdata(u32 b1, u32 b0)
0179 {
0180     return (b0 & SBA_C_MDATA_BNUMx_MASK) |
0181            ((b1 & SBA_C_MDATA_BNUMx_MASK) << SBA_C_MDATA_BNUMx_SHIFT(1));
0182 }
0183 
0184 static inline u32 __pure sba_cmd_pq_c_mdata(u32 d, u32 b1, u32 b0)
0185 {
0186     return (b0 & SBA_C_MDATA_BNUMx_MASK) |
0187            ((b1 & SBA_C_MDATA_BNUMx_MASK) << SBA_C_MDATA_BNUMx_SHIFT(1)) |
0188            ((d & SBA_C_MDATA_DNUM_MASK) << SBA_C_MDATA_DNUM_SHIFT);
0189 }
0190 
0191 /* ====== General helper routines ===== */
0192 
0193 static struct sba_request *sba_alloc_request(struct sba_device *sba)
0194 {
0195     bool found = false;
0196     unsigned long flags;
0197     struct sba_request *req = NULL;
0198 
0199     spin_lock_irqsave(&sba->reqs_lock, flags);
0200     list_for_each_entry(req, &sba->reqs_free_list, node) {
0201         if (async_tx_test_ack(&req->tx)) {
0202             list_move_tail(&req->node, &sba->reqs_alloc_list);
0203             found = true;
0204             break;
0205         }
0206     }
0207     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0208 
0209     if (!found) {
0210         /*
0211          * We have no more free requests so, we peek
0212          * mailbox channels hoping few active requests
0213          * would have completed which will create more
0214          * room for new requests.
0215          */
0216         mbox_client_peek_data(sba->mchan);
0217         return NULL;
0218     }
0219 
0220     req->flags = SBA_REQUEST_STATE_ALLOCED;
0221     req->first = req;
0222     INIT_LIST_HEAD(&req->next);
0223     atomic_set(&req->next_pending_count, 1);
0224 
0225     dma_async_tx_descriptor_init(&req->tx, &sba->dma_chan);
0226     async_tx_ack(&req->tx);
0227 
0228     return req;
0229 }
0230 
0231 /* Note: Must be called with sba->reqs_lock held */
0232 static void _sba_pending_request(struct sba_device *sba,
0233                  struct sba_request *req)
0234 {
0235     lockdep_assert_held(&sba->reqs_lock);
0236     req->flags &= ~SBA_REQUEST_STATE_MASK;
0237     req->flags |= SBA_REQUEST_STATE_PENDING;
0238     list_move_tail(&req->node, &sba->reqs_pending_list);
0239     if (list_empty(&sba->reqs_active_list))
0240         sba->reqs_fence = false;
0241 }
0242 
0243 /* Note: Must be called with sba->reqs_lock held */
0244 static bool _sba_active_request(struct sba_device *sba,
0245                 struct sba_request *req)
0246 {
0247     lockdep_assert_held(&sba->reqs_lock);
0248     if (list_empty(&sba->reqs_active_list))
0249         sba->reqs_fence = false;
0250     if (sba->reqs_fence)
0251         return false;
0252     req->flags &= ~SBA_REQUEST_STATE_MASK;
0253     req->flags |= SBA_REQUEST_STATE_ACTIVE;
0254     list_move_tail(&req->node, &sba->reqs_active_list);
0255     if (req->flags & SBA_REQUEST_FENCE)
0256         sba->reqs_fence = true;
0257     return true;
0258 }
0259 
0260 /* Note: Must be called with sba->reqs_lock held */
0261 static void _sba_abort_request(struct sba_device *sba,
0262                    struct sba_request *req)
0263 {
0264     lockdep_assert_held(&sba->reqs_lock);
0265     req->flags &= ~SBA_REQUEST_STATE_MASK;
0266     req->flags |= SBA_REQUEST_STATE_ABORTED;
0267     list_move_tail(&req->node, &sba->reqs_aborted_list);
0268     if (list_empty(&sba->reqs_active_list))
0269         sba->reqs_fence = false;
0270 }
0271 
0272 /* Note: Must be called with sba->reqs_lock held */
0273 static void _sba_free_request(struct sba_device *sba,
0274                   struct sba_request *req)
0275 {
0276     lockdep_assert_held(&sba->reqs_lock);
0277     req->flags &= ~SBA_REQUEST_STATE_MASK;
0278     req->flags |= SBA_REQUEST_STATE_FREE;
0279     list_move_tail(&req->node, &sba->reqs_free_list);
0280     if (list_empty(&sba->reqs_active_list))
0281         sba->reqs_fence = false;
0282 }
0283 
0284 static void sba_free_chained_requests(struct sba_request *req)
0285 {
0286     unsigned long flags;
0287     struct sba_request *nreq;
0288     struct sba_device *sba = req->sba;
0289 
0290     spin_lock_irqsave(&sba->reqs_lock, flags);
0291 
0292     _sba_free_request(sba, req);
0293     list_for_each_entry(nreq, &req->next, next)
0294         _sba_free_request(sba, nreq);
0295 
0296     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0297 }
0298 
0299 static void sba_chain_request(struct sba_request *first,
0300                   struct sba_request *req)
0301 {
0302     unsigned long flags;
0303     struct sba_device *sba = req->sba;
0304 
0305     spin_lock_irqsave(&sba->reqs_lock, flags);
0306 
0307     list_add_tail(&req->next, &first->next);
0308     req->first = first;
0309     atomic_inc(&first->next_pending_count);
0310 
0311     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0312 }
0313 
0314 static void sba_cleanup_nonpending_requests(struct sba_device *sba)
0315 {
0316     unsigned long flags;
0317     struct sba_request *req, *req1;
0318 
0319     spin_lock_irqsave(&sba->reqs_lock, flags);
0320 
0321     /* Freeup all alloced request */
0322     list_for_each_entry_safe(req, req1, &sba->reqs_alloc_list, node)
0323         _sba_free_request(sba, req);
0324 
0325     /* Set all active requests as aborted */
0326     list_for_each_entry_safe(req, req1, &sba->reqs_active_list, node)
0327         _sba_abort_request(sba, req);
0328 
0329     /*
0330      * Note: We expect that aborted request will be eventually
0331      * freed by sba_receive_message()
0332      */
0333 
0334     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0335 }
0336 
0337 static void sba_cleanup_pending_requests(struct sba_device *sba)
0338 {
0339     unsigned long flags;
0340     struct sba_request *req, *req1;
0341 
0342     spin_lock_irqsave(&sba->reqs_lock, flags);
0343 
0344     /* Freeup all pending request */
0345     list_for_each_entry_safe(req, req1, &sba->reqs_pending_list, node)
0346         _sba_free_request(sba, req);
0347 
0348     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0349 }
0350 
0351 static int sba_send_mbox_request(struct sba_device *sba,
0352                  struct sba_request *req)
0353 {
0354     int ret = 0;
0355 
0356     /* Send message for the request */
0357     req->msg.error = 0;
0358     ret = mbox_send_message(sba->mchan, &req->msg);
0359     if (ret < 0) {
0360         dev_err(sba->dev, "send message failed with error %d", ret);
0361         return ret;
0362     }
0363 
0364     /* Check error returned by mailbox controller */
0365     ret = req->msg.error;
0366     if (ret < 0) {
0367         dev_err(sba->dev, "message error %d", ret);
0368     }
0369 
0370     /* Signal txdone for mailbox channel */
0371     mbox_client_txdone(sba->mchan, ret);
0372 
0373     return ret;
0374 }
0375 
0376 /* Note: Must be called with sba->reqs_lock held */
0377 static void _sba_process_pending_requests(struct sba_device *sba)
0378 {
0379     int ret;
0380     u32 count;
0381     struct sba_request *req;
0382 
0383     /* Process few pending requests */
0384     count = SBA_MAX_MSG_SEND_PER_MBOX_CHANNEL;
0385     while (!list_empty(&sba->reqs_pending_list) && count) {
0386         /* Get the first pending request */
0387         req = list_first_entry(&sba->reqs_pending_list,
0388                        struct sba_request, node);
0389 
0390         /* Try to make request active */
0391         if (!_sba_active_request(sba, req))
0392             break;
0393 
0394         /* Send request to mailbox channel */
0395         ret = sba_send_mbox_request(sba, req);
0396         if (ret < 0) {
0397             _sba_pending_request(sba, req);
0398             break;
0399         }
0400 
0401         count--;
0402     }
0403 }
0404 
0405 static void sba_process_received_request(struct sba_device *sba,
0406                      struct sba_request *req)
0407 {
0408     unsigned long flags;
0409     struct dma_async_tx_descriptor *tx;
0410     struct sba_request *nreq, *first = req->first;
0411 
0412     /* Process only after all chained requests are received */
0413     if (!atomic_dec_return(&first->next_pending_count)) {
0414         tx = &first->tx;
0415 
0416         WARN_ON(tx->cookie < 0);
0417         if (tx->cookie > 0) {
0418             spin_lock_irqsave(&sba->reqs_lock, flags);
0419             dma_cookie_complete(tx);
0420             spin_unlock_irqrestore(&sba->reqs_lock, flags);
0421             dmaengine_desc_get_callback_invoke(tx, NULL);
0422             dma_descriptor_unmap(tx);
0423             tx->callback = NULL;
0424             tx->callback_result = NULL;
0425         }
0426 
0427         dma_run_dependencies(tx);
0428 
0429         spin_lock_irqsave(&sba->reqs_lock, flags);
0430 
0431         /* Free all requests chained to first request */
0432         list_for_each_entry(nreq, &first->next, next)
0433             _sba_free_request(sba, nreq);
0434         INIT_LIST_HEAD(&first->next);
0435 
0436         /* Free the first request */
0437         _sba_free_request(sba, first);
0438 
0439         /* Process pending requests */
0440         _sba_process_pending_requests(sba);
0441 
0442         spin_unlock_irqrestore(&sba->reqs_lock, flags);
0443     }
0444 }
0445 
0446 static void sba_write_stats_in_seqfile(struct sba_device *sba,
0447                        struct seq_file *file)
0448 {
0449     unsigned long flags;
0450     struct sba_request *req;
0451     u32 free_count = 0, alloced_count = 0;
0452     u32 pending_count = 0, active_count = 0, aborted_count = 0;
0453 
0454     spin_lock_irqsave(&sba->reqs_lock, flags);
0455 
0456     list_for_each_entry(req, &sba->reqs_free_list, node)
0457         if (async_tx_test_ack(&req->tx))
0458             free_count++;
0459 
0460     list_for_each_entry(req, &sba->reqs_alloc_list, node)
0461         alloced_count++;
0462 
0463     list_for_each_entry(req, &sba->reqs_pending_list, node)
0464         pending_count++;
0465 
0466     list_for_each_entry(req, &sba->reqs_active_list, node)
0467         active_count++;
0468 
0469     list_for_each_entry(req, &sba->reqs_aborted_list, node)
0470         aborted_count++;
0471 
0472     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0473 
0474     seq_printf(file, "maximum requests   = %d\n", sba->max_req);
0475     seq_printf(file, "free requests      = %d\n", free_count);
0476     seq_printf(file, "alloced requests   = %d\n", alloced_count);
0477     seq_printf(file, "pending requests   = %d\n", pending_count);
0478     seq_printf(file, "active requests    = %d\n", active_count);
0479     seq_printf(file, "aborted requests   = %d\n", aborted_count);
0480 }
0481 
0482 /* ====== DMAENGINE callbacks ===== */
0483 
0484 static void sba_free_chan_resources(struct dma_chan *dchan)
0485 {
0486     /*
0487      * Channel resources are pre-alloced so we just free-up
0488      * whatever we can so that we can re-use pre-alloced
0489      * channel resources next time.
0490      */
0491     sba_cleanup_nonpending_requests(to_sba_device(dchan));
0492 }
0493 
0494 static int sba_device_terminate_all(struct dma_chan *dchan)
0495 {
0496     /* Cleanup all pending requests */
0497     sba_cleanup_pending_requests(to_sba_device(dchan));
0498 
0499     return 0;
0500 }
0501 
0502 static void sba_issue_pending(struct dma_chan *dchan)
0503 {
0504     unsigned long flags;
0505     struct sba_device *sba = to_sba_device(dchan);
0506 
0507     /* Process pending requests */
0508     spin_lock_irqsave(&sba->reqs_lock, flags);
0509     _sba_process_pending_requests(sba);
0510     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0511 }
0512 
0513 static dma_cookie_t sba_tx_submit(struct dma_async_tx_descriptor *tx)
0514 {
0515     unsigned long flags;
0516     dma_cookie_t cookie;
0517     struct sba_device *sba;
0518     struct sba_request *req, *nreq;
0519 
0520     if (unlikely(!tx))
0521         return -EINVAL;
0522 
0523     sba = to_sba_device(tx->chan);
0524     req = to_sba_request(tx);
0525 
0526     /* Assign cookie and mark all chained requests pending */
0527     spin_lock_irqsave(&sba->reqs_lock, flags);
0528     cookie = dma_cookie_assign(tx);
0529     _sba_pending_request(sba, req);
0530     list_for_each_entry(nreq, &req->next, next)
0531         _sba_pending_request(sba, nreq);
0532     spin_unlock_irqrestore(&sba->reqs_lock, flags);
0533 
0534     return cookie;
0535 }
0536 
0537 static enum dma_status sba_tx_status(struct dma_chan *dchan,
0538                      dma_cookie_t cookie,
0539                      struct dma_tx_state *txstate)
0540 {
0541     enum dma_status ret;
0542     struct sba_device *sba = to_sba_device(dchan);
0543 
0544     ret = dma_cookie_status(dchan, cookie, txstate);
0545     if (ret == DMA_COMPLETE)
0546         return ret;
0547 
0548     mbox_client_peek_data(sba->mchan);
0549 
0550     return dma_cookie_status(dchan, cookie, txstate);
0551 }
0552 
0553 static void sba_fillup_interrupt_msg(struct sba_request *req,
0554                      struct brcm_sba_command *cmds,
0555                      struct brcm_message *msg)
0556 {
0557     u64 cmd;
0558     u32 c_mdata;
0559     dma_addr_t resp_dma = req->tx.phys;
0560     struct brcm_sba_command *cmdsp = cmds;
0561 
0562     /* Type-B command to load dummy data into buf0 */
0563     cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
0564               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0565     cmd = sba_cmd_enc(cmd, req->sba->hw_resp_size,
0566               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0567     c_mdata = sba_cmd_load_c_mdata(0);
0568     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0569               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0570     cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
0571               SBA_CMD_SHIFT, SBA_CMD_MASK);
0572     cmdsp->cmd = cmd;
0573     *cmdsp->cmd_dma = cpu_to_le64(cmd);
0574     cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
0575     cmdsp->data = resp_dma;
0576     cmdsp->data_len = req->sba->hw_resp_size;
0577     cmdsp++;
0578 
0579     /* Type-A command to write buf0 to dummy location */
0580     cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
0581               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0582     cmd = sba_cmd_enc(cmd, req->sba->hw_resp_size,
0583               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0584     cmd = sba_cmd_enc(cmd, 0x1,
0585               SBA_RESP_SHIFT, SBA_RESP_MASK);
0586     c_mdata = sba_cmd_write_c_mdata(0);
0587     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0588               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0589     cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
0590               SBA_CMD_SHIFT, SBA_CMD_MASK);
0591     cmdsp->cmd = cmd;
0592     *cmdsp->cmd_dma = cpu_to_le64(cmd);
0593     cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
0594     if (req->sba->hw_resp_size) {
0595         cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
0596         cmdsp->resp = resp_dma;
0597         cmdsp->resp_len = req->sba->hw_resp_size;
0598     }
0599     cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
0600     cmdsp->data = resp_dma;
0601     cmdsp->data_len = req->sba->hw_resp_size;
0602     cmdsp++;
0603 
0604     /* Fillup brcm_message */
0605     msg->type = BRCM_MESSAGE_SBA;
0606     msg->sba.cmds = cmds;
0607     msg->sba.cmds_count = cmdsp - cmds;
0608     msg->ctx = req;
0609     msg->error = 0;
0610 }
0611 
0612 static struct dma_async_tx_descriptor *
0613 sba_prep_dma_interrupt(struct dma_chan *dchan, unsigned long flags)
0614 {
0615     struct sba_request *req = NULL;
0616     struct sba_device *sba = to_sba_device(dchan);
0617 
0618     /* Alloc new request */
0619     req = sba_alloc_request(sba);
0620     if (!req)
0621         return NULL;
0622 
0623     /*
0624      * Force fence so that no requests are submitted
0625      * until DMA callback for this request is invoked.
0626      */
0627     req->flags |= SBA_REQUEST_FENCE;
0628 
0629     /* Fillup request message */
0630     sba_fillup_interrupt_msg(req, req->cmds, &req->msg);
0631 
0632     /* Init async_tx descriptor */
0633     req->tx.flags = flags;
0634     req->tx.cookie = -EBUSY;
0635 
0636     return &req->tx;
0637 }
0638 
0639 static void sba_fillup_memcpy_msg(struct sba_request *req,
0640                   struct brcm_sba_command *cmds,
0641                   struct brcm_message *msg,
0642                   dma_addr_t msg_offset, size_t msg_len,
0643                   dma_addr_t dst, dma_addr_t src)
0644 {
0645     u64 cmd;
0646     u32 c_mdata;
0647     dma_addr_t resp_dma = req->tx.phys;
0648     struct brcm_sba_command *cmdsp = cmds;
0649 
0650     /* Type-B command to load data into buf0 */
0651     cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
0652               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0653     cmd = sba_cmd_enc(cmd, msg_len,
0654               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0655     c_mdata = sba_cmd_load_c_mdata(0);
0656     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0657               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0658     cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
0659               SBA_CMD_SHIFT, SBA_CMD_MASK);
0660     cmdsp->cmd = cmd;
0661     *cmdsp->cmd_dma = cpu_to_le64(cmd);
0662     cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
0663     cmdsp->data = src + msg_offset;
0664     cmdsp->data_len = msg_len;
0665     cmdsp++;
0666 
0667     /* Type-A command to write buf0 */
0668     cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
0669               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0670     cmd = sba_cmd_enc(cmd, msg_len,
0671               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0672     cmd = sba_cmd_enc(cmd, 0x1,
0673               SBA_RESP_SHIFT, SBA_RESP_MASK);
0674     c_mdata = sba_cmd_write_c_mdata(0);
0675     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0676               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0677     cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
0678               SBA_CMD_SHIFT, SBA_CMD_MASK);
0679     cmdsp->cmd = cmd;
0680     *cmdsp->cmd_dma = cpu_to_le64(cmd);
0681     cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
0682     if (req->sba->hw_resp_size) {
0683         cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
0684         cmdsp->resp = resp_dma;
0685         cmdsp->resp_len = req->sba->hw_resp_size;
0686     }
0687     cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
0688     cmdsp->data = dst + msg_offset;
0689     cmdsp->data_len = msg_len;
0690     cmdsp++;
0691 
0692     /* Fillup brcm_message */
0693     msg->type = BRCM_MESSAGE_SBA;
0694     msg->sba.cmds = cmds;
0695     msg->sba.cmds_count = cmdsp - cmds;
0696     msg->ctx = req;
0697     msg->error = 0;
0698 }
0699 
0700 static struct sba_request *
0701 sba_prep_dma_memcpy_req(struct sba_device *sba,
0702             dma_addr_t off, dma_addr_t dst, dma_addr_t src,
0703             size_t len, unsigned long flags)
0704 {
0705     struct sba_request *req = NULL;
0706 
0707     /* Alloc new request */
0708     req = sba_alloc_request(sba);
0709     if (!req)
0710         return NULL;
0711     if (flags & DMA_PREP_FENCE)
0712         req->flags |= SBA_REQUEST_FENCE;
0713 
0714     /* Fillup request message */
0715     sba_fillup_memcpy_msg(req, req->cmds, &req->msg,
0716                   off, len, dst, src);
0717 
0718     /* Init async_tx descriptor */
0719     req->tx.flags = flags;
0720     req->tx.cookie = -EBUSY;
0721 
0722     return req;
0723 }
0724 
0725 static struct dma_async_tx_descriptor *
0726 sba_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
0727             size_t len, unsigned long flags)
0728 {
0729     size_t req_len;
0730     dma_addr_t off = 0;
0731     struct sba_device *sba = to_sba_device(dchan);
0732     struct sba_request *first = NULL, *req;
0733 
0734     /* Create chained requests where each request is upto hw_buf_size */
0735     while (len) {
0736         req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
0737 
0738         req = sba_prep_dma_memcpy_req(sba, off, dst, src,
0739                           req_len, flags);
0740         if (!req) {
0741             if (first)
0742                 sba_free_chained_requests(first);
0743             return NULL;
0744         }
0745 
0746         if (first)
0747             sba_chain_request(first, req);
0748         else
0749             first = req;
0750 
0751         off += req_len;
0752         len -= req_len;
0753     }
0754 
0755     return (first) ? &first->tx : NULL;
0756 }
0757 
0758 static void sba_fillup_xor_msg(struct sba_request *req,
0759                 struct brcm_sba_command *cmds,
0760                 struct brcm_message *msg,
0761                 dma_addr_t msg_offset, size_t msg_len,
0762                 dma_addr_t dst, dma_addr_t *src, u32 src_cnt)
0763 {
0764     u64 cmd;
0765     u32 c_mdata;
0766     unsigned int i;
0767     dma_addr_t resp_dma = req->tx.phys;
0768     struct brcm_sba_command *cmdsp = cmds;
0769 
0770     /* Type-B command to load data into buf0 */
0771     cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
0772               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0773     cmd = sba_cmd_enc(cmd, msg_len,
0774               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0775     c_mdata = sba_cmd_load_c_mdata(0);
0776     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0777               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0778     cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
0779               SBA_CMD_SHIFT, SBA_CMD_MASK);
0780     cmdsp->cmd = cmd;
0781     *cmdsp->cmd_dma = cpu_to_le64(cmd);
0782     cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
0783     cmdsp->data = src[0] + msg_offset;
0784     cmdsp->data_len = msg_len;
0785     cmdsp++;
0786 
0787     /* Type-B commands to xor data with buf0 and put it back in buf0 */
0788     for (i = 1; i < src_cnt; i++) {
0789         cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
0790                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0791         cmd = sba_cmd_enc(cmd, msg_len,
0792                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0793         c_mdata = sba_cmd_xor_c_mdata(0, 0);
0794         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0795                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0796         cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
0797                   SBA_CMD_SHIFT, SBA_CMD_MASK);
0798         cmdsp->cmd = cmd;
0799         *cmdsp->cmd_dma = cpu_to_le64(cmd);
0800         cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
0801         cmdsp->data = src[i] + msg_offset;
0802         cmdsp->data_len = msg_len;
0803         cmdsp++;
0804     }
0805 
0806     /* Type-A command to write buf0 */
0807     cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
0808               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0809     cmd = sba_cmd_enc(cmd, msg_len,
0810               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0811     cmd = sba_cmd_enc(cmd, 0x1,
0812               SBA_RESP_SHIFT, SBA_RESP_MASK);
0813     c_mdata = sba_cmd_write_c_mdata(0);
0814     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0815               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0816     cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
0817               SBA_CMD_SHIFT, SBA_CMD_MASK);
0818     cmdsp->cmd = cmd;
0819     *cmdsp->cmd_dma = cpu_to_le64(cmd);
0820     cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
0821     if (req->sba->hw_resp_size) {
0822         cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
0823         cmdsp->resp = resp_dma;
0824         cmdsp->resp_len = req->sba->hw_resp_size;
0825     }
0826     cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
0827     cmdsp->data = dst + msg_offset;
0828     cmdsp->data_len = msg_len;
0829     cmdsp++;
0830 
0831     /* Fillup brcm_message */
0832     msg->type = BRCM_MESSAGE_SBA;
0833     msg->sba.cmds = cmds;
0834     msg->sba.cmds_count = cmdsp - cmds;
0835     msg->ctx = req;
0836     msg->error = 0;
0837 }
0838 
0839 static struct sba_request *
0840 sba_prep_dma_xor_req(struct sba_device *sba,
0841              dma_addr_t off, dma_addr_t dst, dma_addr_t *src,
0842              u32 src_cnt, size_t len, unsigned long flags)
0843 {
0844     struct sba_request *req = NULL;
0845 
0846     /* Alloc new request */
0847     req = sba_alloc_request(sba);
0848     if (!req)
0849         return NULL;
0850     if (flags & DMA_PREP_FENCE)
0851         req->flags |= SBA_REQUEST_FENCE;
0852 
0853     /* Fillup request message */
0854     sba_fillup_xor_msg(req, req->cmds, &req->msg,
0855                off, len, dst, src, src_cnt);
0856 
0857     /* Init async_tx descriptor */
0858     req->tx.flags = flags;
0859     req->tx.cookie = -EBUSY;
0860 
0861     return req;
0862 }
0863 
0864 static struct dma_async_tx_descriptor *
0865 sba_prep_dma_xor(struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
0866          u32 src_cnt, size_t len, unsigned long flags)
0867 {
0868     size_t req_len;
0869     dma_addr_t off = 0;
0870     struct sba_device *sba = to_sba_device(dchan);
0871     struct sba_request *first = NULL, *req;
0872 
0873     /* Sanity checks */
0874     if (unlikely(src_cnt > sba->max_xor_srcs))
0875         return NULL;
0876 
0877     /* Create chained requests where each request is upto hw_buf_size */
0878     while (len) {
0879         req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
0880 
0881         req = sba_prep_dma_xor_req(sba, off, dst, src, src_cnt,
0882                        req_len, flags);
0883         if (!req) {
0884             if (first)
0885                 sba_free_chained_requests(first);
0886             return NULL;
0887         }
0888 
0889         if (first)
0890             sba_chain_request(first, req);
0891         else
0892             first = req;
0893 
0894         off += req_len;
0895         len -= req_len;
0896     }
0897 
0898     return (first) ? &first->tx : NULL;
0899 }
0900 
0901 static void sba_fillup_pq_msg(struct sba_request *req,
0902                 bool pq_continue,
0903                 struct brcm_sba_command *cmds,
0904                 struct brcm_message *msg,
0905                 dma_addr_t msg_offset, size_t msg_len,
0906                 dma_addr_t *dst_p, dma_addr_t *dst_q,
0907                 const u8 *scf, dma_addr_t *src, u32 src_cnt)
0908 {
0909     u64 cmd;
0910     u32 c_mdata;
0911     unsigned int i;
0912     dma_addr_t resp_dma = req->tx.phys;
0913     struct brcm_sba_command *cmdsp = cmds;
0914 
0915     if (pq_continue) {
0916         /* Type-B command to load old P into buf0 */
0917         if (dst_p) {
0918             cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
0919                 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0920             cmd = sba_cmd_enc(cmd, msg_len,
0921                 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0922             c_mdata = sba_cmd_load_c_mdata(0);
0923             cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0924                 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0925             cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
0926                 SBA_CMD_SHIFT, SBA_CMD_MASK);
0927             cmdsp->cmd = cmd;
0928             *cmdsp->cmd_dma = cpu_to_le64(cmd);
0929             cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
0930             cmdsp->data = *dst_p + msg_offset;
0931             cmdsp->data_len = msg_len;
0932             cmdsp++;
0933         }
0934 
0935         /* Type-B command to load old Q into buf1 */
0936         if (dst_q) {
0937             cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
0938                 SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0939             cmd = sba_cmd_enc(cmd, msg_len,
0940                 SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0941             c_mdata = sba_cmd_load_c_mdata(1);
0942             cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0943                 SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0944             cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
0945                 SBA_CMD_SHIFT, SBA_CMD_MASK);
0946             cmdsp->cmd = cmd;
0947             *cmdsp->cmd_dma = cpu_to_le64(cmd);
0948             cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
0949             cmdsp->data = *dst_q + msg_offset;
0950             cmdsp->data_len = msg_len;
0951             cmdsp++;
0952         }
0953     } else {
0954         /* Type-A command to zero all buffers */
0955         cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
0956                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0957         cmd = sba_cmd_enc(cmd, msg_len,
0958                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0959         cmd = sba_cmd_enc(cmd, SBA_CMD_ZERO_ALL_BUFFERS,
0960                   SBA_CMD_SHIFT, SBA_CMD_MASK);
0961         cmdsp->cmd = cmd;
0962         *cmdsp->cmd_dma = cpu_to_le64(cmd);
0963         cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
0964         cmdsp++;
0965     }
0966 
0967     /* Type-B commands for generate P onto buf0 and Q onto buf1 */
0968     for (i = 0; i < src_cnt; i++) {
0969         cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
0970                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0971         cmd = sba_cmd_enc(cmd, msg_len,
0972                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0973         c_mdata = sba_cmd_pq_c_mdata(raid6_gflog[scf[i]], 1, 0);
0974         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0975                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0976         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
0977                   SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
0978         cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS_XOR,
0979                   SBA_CMD_SHIFT, SBA_CMD_MASK);
0980         cmdsp->cmd = cmd;
0981         *cmdsp->cmd_dma = cpu_to_le64(cmd);
0982         cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
0983         cmdsp->data = src[i] + msg_offset;
0984         cmdsp->data_len = msg_len;
0985         cmdsp++;
0986     }
0987 
0988     /* Type-A command to write buf0 */
0989     if (dst_p) {
0990         cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
0991                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
0992         cmd = sba_cmd_enc(cmd, msg_len,
0993                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
0994         cmd = sba_cmd_enc(cmd, 0x1,
0995                   SBA_RESP_SHIFT, SBA_RESP_MASK);
0996         c_mdata = sba_cmd_write_c_mdata(0);
0997         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
0998                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
0999         cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1000                   SBA_CMD_SHIFT, SBA_CMD_MASK);
1001         cmdsp->cmd = cmd;
1002         *cmdsp->cmd_dma = cpu_to_le64(cmd);
1003         cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1004         if (req->sba->hw_resp_size) {
1005             cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1006             cmdsp->resp = resp_dma;
1007             cmdsp->resp_len = req->sba->hw_resp_size;
1008         }
1009         cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1010         cmdsp->data = *dst_p + msg_offset;
1011         cmdsp->data_len = msg_len;
1012         cmdsp++;
1013     }
1014 
1015     /* Type-A command to write buf1 */
1016     if (dst_q) {
1017         cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1018                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1019         cmd = sba_cmd_enc(cmd, msg_len,
1020                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1021         cmd = sba_cmd_enc(cmd, 0x1,
1022                   SBA_RESP_SHIFT, SBA_RESP_MASK);
1023         c_mdata = sba_cmd_write_c_mdata(1);
1024         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1025                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1026         cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1027                   SBA_CMD_SHIFT, SBA_CMD_MASK);
1028         cmdsp->cmd = cmd;
1029         *cmdsp->cmd_dma = cpu_to_le64(cmd);
1030         cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1031         if (req->sba->hw_resp_size) {
1032             cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1033             cmdsp->resp = resp_dma;
1034             cmdsp->resp_len = req->sba->hw_resp_size;
1035         }
1036         cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1037         cmdsp->data = *dst_q + msg_offset;
1038         cmdsp->data_len = msg_len;
1039         cmdsp++;
1040     }
1041 
1042     /* Fillup brcm_message */
1043     msg->type = BRCM_MESSAGE_SBA;
1044     msg->sba.cmds = cmds;
1045     msg->sba.cmds_count = cmdsp - cmds;
1046     msg->ctx = req;
1047     msg->error = 0;
1048 }
1049 
1050 static struct sba_request *
1051 sba_prep_dma_pq_req(struct sba_device *sba, dma_addr_t off,
1052             dma_addr_t *dst_p, dma_addr_t *dst_q, dma_addr_t *src,
1053             u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1054 {
1055     struct sba_request *req = NULL;
1056 
1057     /* Alloc new request */
1058     req = sba_alloc_request(sba);
1059     if (!req)
1060         return NULL;
1061     if (flags & DMA_PREP_FENCE)
1062         req->flags |= SBA_REQUEST_FENCE;
1063 
1064     /* Fillup request messages */
1065     sba_fillup_pq_msg(req, dmaf_continue(flags),
1066               req->cmds, &req->msg,
1067               off, len, dst_p, dst_q, scf, src, src_cnt);
1068 
1069     /* Init async_tx descriptor */
1070     req->tx.flags = flags;
1071     req->tx.cookie = -EBUSY;
1072 
1073     return req;
1074 }
1075 
1076 static void sba_fillup_pq_single_msg(struct sba_request *req,
1077                 bool pq_continue,
1078                 struct brcm_sba_command *cmds,
1079                 struct brcm_message *msg,
1080                 dma_addr_t msg_offset, size_t msg_len,
1081                 dma_addr_t *dst_p, dma_addr_t *dst_q,
1082                 dma_addr_t src, u8 scf)
1083 {
1084     u64 cmd;
1085     u32 c_mdata;
1086     u8 pos, dpos = raid6_gflog[scf];
1087     dma_addr_t resp_dma = req->tx.phys;
1088     struct brcm_sba_command *cmdsp = cmds;
1089 
1090     if (!dst_p)
1091         goto skip_p;
1092 
1093     if (pq_continue) {
1094         /* Type-B command to load old P into buf0 */
1095         cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1096                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1097         cmd = sba_cmd_enc(cmd, msg_len,
1098                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1099         c_mdata = sba_cmd_load_c_mdata(0);
1100         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1101                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1102         cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
1103                   SBA_CMD_SHIFT, SBA_CMD_MASK);
1104         cmdsp->cmd = cmd;
1105         *cmdsp->cmd_dma = cpu_to_le64(cmd);
1106         cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1107         cmdsp->data = *dst_p + msg_offset;
1108         cmdsp->data_len = msg_len;
1109         cmdsp++;
1110 
1111         /*
1112          * Type-B commands to xor data with buf0 and put it
1113          * back in buf0
1114          */
1115         cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1116                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1117         cmd = sba_cmd_enc(cmd, msg_len,
1118                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1119         c_mdata = sba_cmd_xor_c_mdata(0, 0);
1120         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1121                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1122         cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
1123                   SBA_CMD_SHIFT, SBA_CMD_MASK);
1124         cmdsp->cmd = cmd;
1125         *cmdsp->cmd_dma = cpu_to_le64(cmd);
1126         cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1127         cmdsp->data = src + msg_offset;
1128         cmdsp->data_len = msg_len;
1129         cmdsp++;
1130     } else {
1131         /* Type-B command to load old P into buf0 */
1132         cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1133                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1134         cmd = sba_cmd_enc(cmd, msg_len,
1135                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1136         c_mdata = sba_cmd_load_c_mdata(0);
1137         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1138                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1139         cmd = sba_cmd_enc(cmd, SBA_CMD_LOAD_BUFFER,
1140                   SBA_CMD_SHIFT, SBA_CMD_MASK);
1141         cmdsp->cmd = cmd;
1142         *cmdsp->cmd_dma = cpu_to_le64(cmd);
1143         cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1144         cmdsp->data = src + msg_offset;
1145         cmdsp->data_len = msg_len;
1146         cmdsp++;
1147     }
1148 
1149     /* Type-A command to write buf0 */
1150     cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1151               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1152     cmd = sba_cmd_enc(cmd, msg_len,
1153               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1154     cmd = sba_cmd_enc(cmd, 0x1,
1155               SBA_RESP_SHIFT, SBA_RESP_MASK);
1156     c_mdata = sba_cmd_write_c_mdata(0);
1157     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1158               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1159     cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1160               SBA_CMD_SHIFT, SBA_CMD_MASK);
1161     cmdsp->cmd = cmd;
1162     *cmdsp->cmd_dma = cpu_to_le64(cmd);
1163     cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1164     if (req->sba->hw_resp_size) {
1165         cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1166         cmdsp->resp = resp_dma;
1167         cmdsp->resp_len = req->sba->hw_resp_size;
1168     }
1169     cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1170     cmdsp->data = *dst_p + msg_offset;
1171     cmdsp->data_len = msg_len;
1172     cmdsp++;
1173 
1174 skip_p:
1175     if (!dst_q)
1176         goto skip_q;
1177 
1178     /* Type-A command to zero all buffers */
1179     cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1180               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1181     cmd = sba_cmd_enc(cmd, msg_len,
1182               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1183     cmd = sba_cmd_enc(cmd, SBA_CMD_ZERO_ALL_BUFFERS,
1184               SBA_CMD_SHIFT, SBA_CMD_MASK);
1185     cmdsp->cmd = cmd;
1186     *cmdsp->cmd_dma = cpu_to_le64(cmd);
1187     cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1188     cmdsp++;
1189 
1190     if (dpos == 255)
1191         goto skip_q_computation;
1192     pos = (dpos < req->sba->max_pq_coefs) ?
1193         dpos : (req->sba->max_pq_coefs - 1);
1194 
1195     /*
1196      * Type-B command to generate initial Q from data
1197      * and store output into buf0
1198      */
1199     cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1200               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1201     cmd = sba_cmd_enc(cmd, msg_len,
1202               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1203     c_mdata = sba_cmd_pq_c_mdata(pos, 0, 0);
1204     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1205               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1206     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
1207               SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
1208     cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS,
1209               SBA_CMD_SHIFT, SBA_CMD_MASK);
1210     cmdsp->cmd = cmd;
1211     *cmdsp->cmd_dma = cpu_to_le64(cmd);
1212     cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1213     cmdsp->data = src + msg_offset;
1214     cmdsp->data_len = msg_len;
1215     cmdsp++;
1216 
1217     dpos -= pos;
1218 
1219     /* Multiple Type-A command to generate final Q */
1220     while (dpos) {
1221         pos = (dpos < req->sba->max_pq_coefs) ?
1222             dpos : (req->sba->max_pq_coefs - 1);
1223 
1224         /*
1225          * Type-A command to generate Q with buf0 and
1226          * buf1 store result in buf0
1227          */
1228         cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1229                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1230         cmd = sba_cmd_enc(cmd, msg_len,
1231                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1232         c_mdata = sba_cmd_pq_c_mdata(pos, 0, 1);
1233         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1234                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1235         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_MS(c_mdata),
1236                   SBA_C_MDATA_MS_SHIFT, SBA_C_MDATA_MS_MASK);
1237         cmd = sba_cmd_enc(cmd, SBA_CMD_GALOIS,
1238                   SBA_CMD_SHIFT, SBA_CMD_MASK);
1239         cmdsp->cmd = cmd;
1240         *cmdsp->cmd_dma = cpu_to_le64(cmd);
1241         cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1242         cmdsp++;
1243 
1244         dpos -= pos;
1245     }
1246 
1247 skip_q_computation:
1248     if (pq_continue) {
1249         /*
1250          * Type-B command to XOR previous output with
1251          * buf0 and write it into buf0
1252          */
1253         cmd = sba_cmd_enc(0x0, SBA_TYPE_B,
1254                   SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1255         cmd = sba_cmd_enc(cmd, msg_len,
1256                   SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1257         c_mdata = sba_cmd_xor_c_mdata(0, 0);
1258         cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1259                   SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1260         cmd = sba_cmd_enc(cmd, SBA_CMD_XOR,
1261                   SBA_CMD_SHIFT, SBA_CMD_MASK);
1262         cmdsp->cmd = cmd;
1263         *cmdsp->cmd_dma = cpu_to_le64(cmd);
1264         cmdsp->flags = BRCM_SBA_CMD_TYPE_B;
1265         cmdsp->data = *dst_q + msg_offset;
1266         cmdsp->data_len = msg_len;
1267         cmdsp++;
1268     }
1269 
1270     /* Type-A command to write buf0 */
1271     cmd = sba_cmd_enc(0x0, SBA_TYPE_A,
1272               SBA_TYPE_SHIFT, SBA_TYPE_MASK);
1273     cmd = sba_cmd_enc(cmd, msg_len,
1274               SBA_USER_DEF_SHIFT, SBA_USER_DEF_MASK);
1275     cmd = sba_cmd_enc(cmd, 0x1,
1276               SBA_RESP_SHIFT, SBA_RESP_MASK);
1277     c_mdata = sba_cmd_write_c_mdata(0);
1278     cmd = sba_cmd_enc(cmd, SBA_C_MDATA_LS(c_mdata),
1279               SBA_C_MDATA_SHIFT, SBA_C_MDATA_MASK);
1280     cmd = sba_cmd_enc(cmd, SBA_CMD_WRITE_BUFFER,
1281               SBA_CMD_SHIFT, SBA_CMD_MASK);
1282     cmdsp->cmd = cmd;
1283     *cmdsp->cmd_dma = cpu_to_le64(cmd);
1284     cmdsp->flags = BRCM_SBA_CMD_TYPE_A;
1285     if (req->sba->hw_resp_size) {
1286         cmdsp->flags |= BRCM_SBA_CMD_HAS_RESP;
1287         cmdsp->resp = resp_dma;
1288         cmdsp->resp_len = req->sba->hw_resp_size;
1289     }
1290     cmdsp->flags |= BRCM_SBA_CMD_HAS_OUTPUT;
1291     cmdsp->data = *dst_q + msg_offset;
1292     cmdsp->data_len = msg_len;
1293     cmdsp++;
1294 
1295 skip_q:
1296     /* Fillup brcm_message */
1297     msg->type = BRCM_MESSAGE_SBA;
1298     msg->sba.cmds = cmds;
1299     msg->sba.cmds_count = cmdsp - cmds;
1300     msg->ctx = req;
1301     msg->error = 0;
1302 }
1303 
1304 static struct sba_request *
1305 sba_prep_dma_pq_single_req(struct sba_device *sba, dma_addr_t off,
1306                dma_addr_t *dst_p, dma_addr_t *dst_q,
1307                dma_addr_t src, u8 scf, size_t len,
1308                unsigned long flags)
1309 {
1310     struct sba_request *req = NULL;
1311 
1312     /* Alloc new request */
1313     req = sba_alloc_request(sba);
1314     if (!req)
1315         return NULL;
1316     if (flags & DMA_PREP_FENCE)
1317         req->flags |= SBA_REQUEST_FENCE;
1318 
1319     /* Fillup request messages */
1320     sba_fillup_pq_single_msg(req,  dmaf_continue(flags),
1321                  req->cmds, &req->msg, off, len,
1322                  dst_p, dst_q, src, scf);
1323 
1324     /* Init async_tx descriptor */
1325     req->tx.flags = flags;
1326     req->tx.cookie = -EBUSY;
1327 
1328     return req;
1329 }
1330 
1331 static struct dma_async_tx_descriptor *
1332 sba_prep_dma_pq(struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1333         u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1334 {
1335     u32 i, dst_q_index;
1336     size_t req_len;
1337     bool slow = false;
1338     dma_addr_t off = 0;
1339     dma_addr_t *dst_p = NULL, *dst_q = NULL;
1340     struct sba_device *sba = to_sba_device(dchan);
1341     struct sba_request *first = NULL, *req;
1342 
1343     /* Sanity checks */
1344     if (unlikely(src_cnt > sba->max_pq_srcs))
1345         return NULL;
1346     for (i = 0; i < src_cnt; i++)
1347         if (sba->max_pq_coefs <= raid6_gflog[scf[i]])
1348             slow = true;
1349 
1350     /* Figure-out P and Q destination addresses */
1351     if (!(flags & DMA_PREP_PQ_DISABLE_P))
1352         dst_p = &dst[0];
1353     if (!(flags & DMA_PREP_PQ_DISABLE_Q))
1354         dst_q = &dst[1];
1355 
1356     /* Create chained requests where each request is upto hw_buf_size */
1357     while (len) {
1358         req_len = (len < sba->hw_buf_size) ? len : sba->hw_buf_size;
1359 
1360         if (slow) {
1361             dst_q_index = src_cnt;
1362 
1363             if (dst_q) {
1364                 for (i = 0; i < src_cnt; i++) {
1365                     if (*dst_q == src[i]) {
1366                         dst_q_index = i;
1367                         break;
1368                     }
1369                 }
1370             }
1371 
1372             if (dst_q_index < src_cnt) {
1373                 i = dst_q_index;
1374                 req = sba_prep_dma_pq_single_req(sba,
1375                     off, dst_p, dst_q, src[i], scf[i],
1376                     req_len, flags | DMA_PREP_FENCE);
1377                 if (!req)
1378                     goto fail;
1379 
1380                 if (first)
1381                     sba_chain_request(first, req);
1382                 else
1383                     first = req;
1384 
1385                 flags |= DMA_PREP_CONTINUE;
1386             }
1387 
1388             for (i = 0; i < src_cnt; i++) {
1389                 if (dst_q_index == i)
1390                     continue;
1391 
1392                 req = sba_prep_dma_pq_single_req(sba,
1393                     off, dst_p, dst_q, src[i], scf[i],
1394                     req_len, flags | DMA_PREP_FENCE);
1395                 if (!req)
1396                     goto fail;
1397 
1398                 if (first)
1399                     sba_chain_request(first, req);
1400                 else
1401                     first = req;
1402 
1403                 flags |= DMA_PREP_CONTINUE;
1404             }
1405         } else {
1406             req = sba_prep_dma_pq_req(sba, off,
1407                           dst_p, dst_q, src, src_cnt,
1408                           scf, req_len, flags);
1409             if (!req)
1410                 goto fail;
1411 
1412             if (first)
1413                 sba_chain_request(first, req);
1414             else
1415                 first = req;
1416         }
1417 
1418         off += req_len;
1419         len -= req_len;
1420     }
1421 
1422     return (first) ? &first->tx : NULL;
1423 
1424 fail:
1425     if (first)
1426         sba_free_chained_requests(first);
1427     return NULL;
1428 }
1429 
1430 /* ====== Mailbox callbacks ===== */
1431 
1432 static void sba_receive_message(struct mbox_client *cl, void *msg)
1433 {
1434     struct brcm_message *m = msg;
1435     struct sba_request *req = m->ctx;
1436     struct sba_device *sba = req->sba;
1437 
1438     /* Error count if message has error */
1439     if (m->error < 0)
1440         dev_err(sba->dev, "%s got message with error %d",
1441             dma_chan_name(&sba->dma_chan), m->error);
1442 
1443     /* Process received request */
1444     sba_process_received_request(sba, req);
1445 }
1446 
1447 /* ====== Debugfs callbacks ====== */
1448 
1449 static int sba_debugfs_stats_show(struct seq_file *file, void *offset)
1450 {
1451     struct sba_device *sba = dev_get_drvdata(file->private);
1452 
1453     /* Write stats in file */
1454     sba_write_stats_in_seqfile(sba, file);
1455 
1456     return 0;
1457 }
1458 
1459 /* ====== Platform driver routines ===== */
1460 
1461 static int sba_prealloc_channel_resources(struct sba_device *sba)
1462 {
1463     int i, j, ret = 0;
1464     struct sba_request *req = NULL;
1465 
1466     sba->resp_base = dma_alloc_coherent(sba->mbox_dev,
1467                         sba->max_resp_pool_size,
1468                         &sba->resp_dma_base, GFP_KERNEL);
1469     if (!sba->resp_base)
1470         return -ENOMEM;
1471 
1472     sba->cmds_base = dma_alloc_coherent(sba->mbox_dev,
1473                         sba->max_cmds_pool_size,
1474                         &sba->cmds_dma_base, GFP_KERNEL);
1475     if (!sba->cmds_base) {
1476         ret = -ENOMEM;
1477         goto fail_free_resp_pool;
1478     }
1479 
1480     spin_lock_init(&sba->reqs_lock);
1481     sba->reqs_fence = false;
1482     INIT_LIST_HEAD(&sba->reqs_alloc_list);
1483     INIT_LIST_HEAD(&sba->reqs_pending_list);
1484     INIT_LIST_HEAD(&sba->reqs_active_list);
1485     INIT_LIST_HEAD(&sba->reqs_aborted_list);
1486     INIT_LIST_HEAD(&sba->reqs_free_list);
1487 
1488     for (i = 0; i < sba->max_req; i++) {
1489         req = devm_kzalloc(sba->dev,
1490                    struct_size(req, cmds, sba->max_cmd_per_req),
1491                    GFP_KERNEL);
1492         if (!req) {
1493             ret = -ENOMEM;
1494             goto fail_free_cmds_pool;
1495         }
1496         INIT_LIST_HEAD(&req->node);
1497         req->sba = sba;
1498         req->flags = SBA_REQUEST_STATE_FREE;
1499         INIT_LIST_HEAD(&req->next);
1500         atomic_set(&req->next_pending_count, 0);
1501         for (j = 0; j < sba->max_cmd_per_req; j++) {
1502             req->cmds[j].cmd = 0;
1503             req->cmds[j].cmd_dma = sba->cmds_base +
1504                 (i * sba->max_cmd_per_req + j) * sizeof(u64);
1505             req->cmds[j].cmd_dma_addr = sba->cmds_dma_base +
1506                 (i * sba->max_cmd_per_req + j) * sizeof(u64);
1507             req->cmds[j].flags = 0;
1508         }
1509         memset(&req->msg, 0, sizeof(req->msg));
1510         dma_async_tx_descriptor_init(&req->tx, &sba->dma_chan);
1511         async_tx_ack(&req->tx);
1512         req->tx.tx_submit = sba_tx_submit;
1513         req->tx.phys = sba->resp_dma_base + i * sba->hw_resp_size;
1514         list_add_tail(&req->node, &sba->reqs_free_list);
1515     }
1516 
1517     return 0;
1518 
1519 fail_free_cmds_pool:
1520     dma_free_coherent(sba->mbox_dev,
1521               sba->max_cmds_pool_size,
1522               sba->cmds_base, sba->cmds_dma_base);
1523 fail_free_resp_pool:
1524     dma_free_coherent(sba->mbox_dev,
1525               sba->max_resp_pool_size,
1526               sba->resp_base, sba->resp_dma_base);
1527     return ret;
1528 }
1529 
1530 static void sba_freeup_channel_resources(struct sba_device *sba)
1531 {
1532     dmaengine_terminate_all(&sba->dma_chan);
1533     dma_free_coherent(sba->mbox_dev, sba->max_cmds_pool_size,
1534               sba->cmds_base, sba->cmds_dma_base);
1535     dma_free_coherent(sba->mbox_dev, sba->max_resp_pool_size,
1536               sba->resp_base, sba->resp_dma_base);
1537     sba->resp_base = NULL;
1538     sba->resp_dma_base = 0;
1539 }
1540 
1541 static int sba_async_register(struct sba_device *sba)
1542 {
1543     int ret;
1544     struct dma_device *dma_dev = &sba->dma_dev;
1545 
1546     /* Initialize DMA channel cookie */
1547     sba->dma_chan.device = dma_dev;
1548     dma_cookie_init(&sba->dma_chan);
1549 
1550     /* Initialize DMA device capability mask */
1551     dma_cap_zero(dma_dev->cap_mask);
1552     dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
1553     dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1554     dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1555     dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1556 
1557     /*
1558      * Set mailbox channel device as the base device of
1559      * our dma_device because the actual memory accesses
1560      * will be done by mailbox controller
1561      */
1562     dma_dev->dev = sba->mbox_dev;
1563 
1564     /* Set base prep routines */
1565     dma_dev->device_free_chan_resources = sba_free_chan_resources;
1566     dma_dev->device_terminate_all = sba_device_terminate_all;
1567     dma_dev->device_issue_pending = sba_issue_pending;
1568     dma_dev->device_tx_status = sba_tx_status;
1569 
1570     /* Set interrupt routine */
1571     if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1572         dma_dev->device_prep_dma_interrupt = sba_prep_dma_interrupt;
1573 
1574     /* Set memcpy routine */
1575     if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1576         dma_dev->device_prep_dma_memcpy = sba_prep_dma_memcpy;
1577 
1578     /* Set xor routine and capability */
1579     if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1580         dma_dev->device_prep_dma_xor = sba_prep_dma_xor;
1581         dma_dev->max_xor = sba->max_xor_srcs;
1582     }
1583 
1584     /* Set pq routine and capability */
1585     if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1586         dma_dev->device_prep_dma_pq = sba_prep_dma_pq;
1587         dma_set_maxpq(dma_dev, sba->max_pq_srcs, 0);
1588     }
1589 
1590     /* Initialize DMA device channel list */
1591     INIT_LIST_HEAD(&dma_dev->channels);
1592     list_add_tail(&sba->dma_chan.device_node, &dma_dev->channels);
1593 
1594     /* Register with Linux async DMA framework*/
1595     ret = dma_async_device_register(dma_dev);
1596     if (ret) {
1597         dev_err(sba->dev, "async device register error %d", ret);
1598         return ret;
1599     }
1600 
1601     dev_info(sba->dev, "%s capabilities: %s%s%s%s\n",
1602     dma_chan_name(&sba->dma_chan),
1603     dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "interrupt " : "",
1604     dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "memcpy " : "",
1605     dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1606     dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "");
1607 
1608     return 0;
1609 }
1610 
1611 static int sba_probe(struct platform_device *pdev)
1612 {
1613     int ret = 0;
1614     struct sba_device *sba;
1615     struct platform_device *mbox_pdev;
1616     struct of_phandle_args args;
1617 
1618     /* Allocate main SBA struct */
1619     sba = devm_kzalloc(&pdev->dev, sizeof(*sba), GFP_KERNEL);
1620     if (!sba)
1621         return -ENOMEM;
1622 
1623     sba->dev = &pdev->dev;
1624     platform_set_drvdata(pdev, sba);
1625 
1626     /* Number of mailbox channels should be atleast 1 */
1627     ret = of_count_phandle_with_args(pdev->dev.of_node,
1628                      "mboxes", "#mbox-cells");
1629     if (ret <= 0)
1630         return -ENODEV;
1631 
1632     /* Determine SBA version from DT compatible string */
1633     if (of_device_is_compatible(sba->dev->of_node, "brcm,iproc-sba"))
1634         sba->ver = SBA_VER_1;
1635     else if (of_device_is_compatible(sba->dev->of_node,
1636                      "brcm,iproc-sba-v2"))
1637         sba->ver = SBA_VER_2;
1638     else
1639         return -ENODEV;
1640 
1641     /* Derived Configuration parameters */
1642     switch (sba->ver) {
1643     case SBA_VER_1:
1644         sba->hw_buf_size = 4096;
1645         sba->hw_resp_size = 8;
1646         sba->max_pq_coefs = 6;
1647         sba->max_pq_srcs = 6;
1648         break;
1649     case SBA_VER_2:
1650         sba->hw_buf_size = 4096;
1651         sba->hw_resp_size = 8;
1652         sba->max_pq_coefs = 30;
1653         /*
1654          * We can support max_pq_srcs == max_pq_coefs because
1655          * we are limited by number of SBA commands that we can
1656          * fit in one message for underlying ring manager HW.
1657          */
1658         sba->max_pq_srcs = 12;
1659         break;
1660     default:
1661         return -EINVAL;
1662     }
1663     sba->max_req = SBA_MAX_REQ_PER_MBOX_CHANNEL;
1664     sba->max_cmd_per_req = sba->max_pq_srcs + 3;
1665     sba->max_xor_srcs = sba->max_cmd_per_req - 1;
1666     sba->max_resp_pool_size = sba->max_req * sba->hw_resp_size;
1667     sba->max_cmds_pool_size = sba->max_req *
1668                   sba->max_cmd_per_req * sizeof(u64);
1669 
1670     /* Setup mailbox client */
1671     sba->client.dev         = &pdev->dev;
1672     sba->client.rx_callback     = sba_receive_message;
1673     sba->client.tx_block        = false;
1674     sba->client.knows_txdone    = true;
1675     sba->client.tx_tout     = 0;
1676 
1677     /* Request mailbox channel */
1678     sba->mchan = mbox_request_channel(&sba->client, 0);
1679     if (IS_ERR(sba->mchan)) {
1680         ret = PTR_ERR(sba->mchan);
1681         goto fail_free_mchan;
1682     }
1683 
1684     /* Find-out underlying mailbox device */
1685     ret = of_parse_phandle_with_args(pdev->dev.of_node,
1686                      "mboxes", "#mbox-cells", 0, &args);
1687     if (ret)
1688         goto fail_free_mchan;
1689     mbox_pdev = of_find_device_by_node(args.np);
1690     of_node_put(args.np);
1691     if (!mbox_pdev) {
1692         ret = -ENODEV;
1693         goto fail_free_mchan;
1694     }
1695     sba->mbox_dev = &mbox_pdev->dev;
1696 
1697     /* Prealloc channel resource */
1698     ret = sba_prealloc_channel_resources(sba);
1699     if (ret)
1700         goto fail_free_mchan;
1701 
1702     /* Check availability of debugfs */
1703     if (!debugfs_initialized())
1704         goto skip_debugfs;
1705 
1706     /* Create debugfs root entry */
1707     sba->root = debugfs_create_dir(dev_name(sba->dev), NULL);
1708 
1709     /* Create debugfs stats entry */
1710     debugfs_create_devm_seqfile(sba->dev, "stats", sba->root,
1711                     sba_debugfs_stats_show);
1712 
1713 skip_debugfs:
1714 
1715     /* Register DMA device with Linux async framework */
1716     ret = sba_async_register(sba);
1717     if (ret)
1718         goto fail_free_resources;
1719 
1720     /* Print device info */
1721     dev_info(sba->dev, "%s using SBAv%d mailbox channel from %s",
1722          dma_chan_name(&sba->dma_chan), sba->ver+1,
1723          dev_name(sba->mbox_dev));
1724 
1725     return 0;
1726 
1727 fail_free_resources:
1728     debugfs_remove_recursive(sba->root);
1729     sba_freeup_channel_resources(sba);
1730 fail_free_mchan:
1731     mbox_free_channel(sba->mchan);
1732     return ret;
1733 }
1734 
1735 static int sba_remove(struct platform_device *pdev)
1736 {
1737     struct sba_device *sba = platform_get_drvdata(pdev);
1738 
1739     dma_async_device_unregister(&sba->dma_dev);
1740 
1741     debugfs_remove_recursive(sba->root);
1742 
1743     sba_freeup_channel_resources(sba);
1744 
1745     mbox_free_channel(sba->mchan);
1746 
1747     return 0;
1748 }
1749 
1750 static const struct of_device_id sba_of_match[] = {
1751     { .compatible = "brcm,iproc-sba", },
1752     { .compatible = "brcm,iproc-sba-v2", },
1753     {},
1754 };
1755 MODULE_DEVICE_TABLE(of, sba_of_match);
1756 
1757 static struct platform_driver sba_driver = {
1758     .probe = sba_probe,
1759     .remove = sba_remove,
1760     .driver = {
1761         .name = "bcm-sba-raid",
1762         .of_match_table = sba_of_match,
1763     },
1764 };
1765 module_platform_driver(sba_driver);
1766 
1767 MODULE_DESCRIPTION("Broadcom SBA RAID driver");
1768 MODULE_AUTHOR("Anup Patel <anup.patel@broadcom.com>");
1769 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!