drivers/dma/at_hdmac_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Header file for the Atmel AHB DMA Controller driver
0004  *
0005  * Copyright (C) 2008 Atmel Corporation
0006  */
0007 #ifndef AT_HDMAC_REGS_H
0008 #define AT_HDMAC_REGS_H
0009
0010 #define AT_DMA_MAX_NR_CHANNELS  8
0011
0012
0013 #define AT_DMA_GCFG 0x00    /* Global Configuration Register */
0014 #define     AT_DMA_IF_BIGEND(i) (0x1 << (i))    /* AHB-Lite Interface i in Big-endian mode */
0015 #define     AT_DMA_ARB_CFG  (0x1 << 4)  /* Arbiter mode. */
0016 #define         AT_DMA_ARB_CFG_FIXED        (0x0 << 4)
0017 #define         AT_DMA_ARB_CFG_ROUND_ROBIN  (0x1 << 4)
0018
0019 #define AT_DMA_EN   0x04    /* Controller Enable Register */
0020 #define     AT_DMA_ENABLE   (0x1 << 0)
0021
0022 #define AT_DMA_SREQ 0x08    /* Software Single Request Register */
0023 #define     AT_DMA_SSREQ(x) (0x1 << ((x) << 1))     /* Request a source single transfer on channel x */
0024 #define     AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1)))   /* Request a destination single transfer on channel x */
0025
0026 #define AT_DMA_CREQ 0x0C    /* Software Chunk Transfer Request Register */
0027 #define     AT_DMA_SCREQ(x) (0x1 << ((x) << 1))     /* Request a source chunk transfer on channel x */
0028 #define     AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1)))   /* Request a destination chunk transfer on channel x */
0029
0030 #define AT_DMA_LAST 0x10    /* Software Last Transfer Flag Register */
0031 #define     AT_DMA_SLAST(x) (0x1 << ((x) << 1))     /* This src rq is last tx of buffer on channel x */
0032 #define     AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1)))   /* This dst rq is last tx of buffer on channel x */
0033
0034 #define AT_DMA_SYNC 0x14    /* Request Synchronization Register */
0035 #define     AT_DMA_SYR(h)   (0x1 << (h))            /* Synchronize handshake line h */
0036
0037 /* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
0038 #define AT_DMA_EBCIER   0x18    /* Enable register */
0039 #define AT_DMA_EBCIDR   0x1C    /* Disable register */
0040 #define AT_DMA_EBCIMR   0x20    /* Mask Register */
0041 #define AT_DMA_EBCISR   0x24    /* Status Register */
0042 #define     AT_DMA_CBTC_OFFSET  8
0043 #define     AT_DMA_ERR_OFFSET   16
0044 #define     AT_DMA_BTC(x)   (0x1 << (x))
0045 #define     AT_DMA_CBTC(x)  (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
0046 #define     AT_DMA_ERR(x)   (0x1 << (AT_DMA_ERR_OFFSET + (x)))
0047
0048 #define AT_DMA_CHER 0x28    /* Channel Handler Enable Register */
0049 #define     AT_DMA_ENA(x)   (0x1 << (x))
0050 #define     AT_DMA_SUSP(x)  (0x1 << ( 8 + (x)))
0051 #define     AT_DMA_KEEP(x)  (0x1 << (24 + (x)))
0052
0053 #define AT_DMA_CHDR 0x2C    /* Channel Handler Disable Register */
0054 #define     AT_DMA_DIS(x)   (0x1 << (x))
0055 #define     AT_DMA_RES(x)   (0x1 << ( 8 + (x)))
0056
0057 #define AT_DMA_CHSR 0x30    /* Channel Handler Status Register */
0058 #define     AT_DMA_EMPT(x)  (0x1 << (16 + (x)))
0059 #define     AT_DMA_STAL(x)  (0x1 << (24 + (x)))
0060
0061
0062 #define AT_DMA_CH_REGS_BASE 0x3C    /* Channel registers base address */
0063 #define ch_regs(x)  (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
0064
0065 /* Hardware register offset for each channel */
0066 #define ATC_SADDR_OFFSET    0x00    /* Source Address Register */
0067 #define ATC_DADDR_OFFSET    0x04    /* Destination Address Register */
0068 #define ATC_DSCR_OFFSET     0x08    /* Descriptor Address Register */
0069 #define ATC_CTRLA_OFFSET    0x0C    /* Control A Register */
0070 #define ATC_CTRLB_OFFSET    0x10    /* Control B Register */
0071 #define ATC_CFG_OFFSET      0x14    /* Configuration Register */
0072 #define ATC_SPIP_OFFSET     0x18    /* Src PIP Configuration Register */
0073 #define ATC_DPIP_OFFSET     0x1C    /* Dst PIP Configuration Register */
0074
0075
0076 /* Bitfield definitions */
0077
0078 /* Bitfields in DSCR */
0079 #define ATC_DSCR_IF(i)      (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */
0080
0081 /* Bitfields in CTRLA */
0082 #define ATC_BTSIZE_MAX      0xFFFFUL    /* Maximum Buffer Transfer Size */
0083 #define ATC_BTSIZE(x)       (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
0084 #define ATC_SCSIZE_MASK     (0x7 << 16) /* Source Chunk Transfer Size */
0085 #define     ATC_SCSIZE(x)       (ATC_SCSIZE_MASK & ((x) << 16))
0086 #define     ATC_SCSIZE_1        (0x0 << 16)
0087 #define     ATC_SCSIZE_4        (0x1 << 16)
0088 #define     ATC_SCSIZE_8        (0x2 << 16)
0089 #define     ATC_SCSIZE_16       (0x3 << 16)
0090 #define     ATC_SCSIZE_32       (0x4 << 16)
0091 #define     ATC_SCSIZE_64       (0x5 << 16)
0092 #define     ATC_SCSIZE_128      (0x6 << 16)
0093 #define     ATC_SCSIZE_256      (0x7 << 16)
0094 #define ATC_DCSIZE_MASK     (0x7 << 20) /* Destination Chunk Transfer Size */
0095 #define     ATC_DCSIZE(x)       (ATC_DCSIZE_MASK & ((x) << 20))
0096 #define     ATC_DCSIZE_1        (0x0 << 20)
0097 #define     ATC_DCSIZE_4        (0x1 << 20)
0098 #define     ATC_DCSIZE_8        (0x2 << 20)
0099 #define     ATC_DCSIZE_16       (0x3 << 20)
0100 #define     ATC_DCSIZE_32       (0x4 << 20)
0101 #define     ATC_DCSIZE_64       (0x5 << 20)
0102 #define     ATC_DCSIZE_128      (0x6 << 20)
0103 #define     ATC_DCSIZE_256      (0x7 << 20)
0104 #define ATC_SRC_WIDTH_MASK  (0x3 << 24) /* Source Single Transfer Size */
0105 #define     ATC_SRC_WIDTH(x)    ((x) << 24)
0106 #define     ATC_SRC_WIDTH_BYTE  (0x0 << 24)
0107 #define     ATC_SRC_WIDTH_HALFWORD  (0x1 << 24)
0108 #define     ATC_SRC_WIDTH_WORD  (0x2 << 24)
0109 #define     ATC_REG_TO_SRC_WIDTH(r) (((r) >> 24) & 0x3)
0110 #define ATC_DST_WIDTH_MASK  (0x3 << 28) /* Destination Single Transfer Size */
0111 #define     ATC_DST_WIDTH(x)    ((x) << 28)
0112 #define     ATC_DST_WIDTH_BYTE  (0x0 << 28)
0113 #define     ATC_DST_WIDTH_HALFWORD  (0x1 << 28)
0114 #define     ATC_DST_WIDTH_WORD  (0x2 << 28)
0115 #define ATC_DONE        (0x1 << 31) /* Tx Done (only written back in descriptor) */
0116
0117 /* Bitfields in CTRLB */
0118 #define ATC_SIF(i)      (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */
0119 #define ATC_DIF(i)      ((0x3 & (i)) <<  4) /* Dst tx done via AHB-Lite Interface i */
0120                   /* Specify AHB interfaces */
0121 #define AT_DMA_MEM_IF       0 /* interface 0 as memory interface */
0122 #define AT_DMA_PER_IF       1 /* interface 1 as peripheral interface */
0123
0124 #define ATC_SRC_PIP     (0x1 <<  8) /* Source Picture-in-Picture enabled */
0125 #define ATC_DST_PIP     (0x1 << 12) /* Destination Picture-in-Picture enabled */
0126 #define ATC_SRC_DSCR_DIS    (0x1 << 16) /* Src Descriptor fetch disable */
0127 #define ATC_DST_DSCR_DIS    (0x1 << 20) /* Dst Descriptor fetch disable */
0128 #define ATC_FC_MASK     (0x7 << 21) /* Choose Flow Controller */
0129 #define     ATC_FC_MEM2MEM      (0x0 << 21) /* Mem-to-Mem (DMA) */
0130 #define     ATC_FC_MEM2PER      (0x1 << 21) /* Mem-to-Periph (DMA) */
0131 #define     ATC_FC_PER2MEM      (0x2 << 21) /* Periph-to-Mem (DMA) */
0132 #define     ATC_FC_PER2PER      (0x3 << 21) /* Periph-to-Periph (DMA) */
0133 #define     ATC_FC_PER2MEM_PER  (0x4 << 21) /* Periph-to-Mem (Peripheral) */
0134 #define     ATC_FC_MEM2PER_PER  (0x5 << 21) /* Mem-to-Periph (Peripheral) */
0135 #define     ATC_FC_PER2PER_SRCPER   (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */
0136 #define     ATC_FC_PER2PER_DSTPER   (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */
0137 #define ATC_SRC_ADDR_MODE_MASK  (0x3 << 24)
0138 #define     ATC_SRC_ADDR_MODE_INCR  (0x0 << 24) /* Incrementing Mode */
0139 #define     ATC_SRC_ADDR_MODE_DECR  (0x1 << 24) /* Decrementing Mode */
0140 #define     ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */
0141 #define ATC_DST_ADDR_MODE_MASK  (0x3 << 28)
0142 #define     ATC_DST_ADDR_MODE_INCR  (0x0 << 28) /* Incrementing Mode */
0143 #define     ATC_DST_ADDR_MODE_DECR  (0x1 << 28) /* Decrementing Mode */
0144 #define     ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */
0145 #define ATC_IEN         (0x1 << 30) /* BTC interrupt enable (active low) */
0146 #define ATC_AUTO        (0x1 << 31) /* Auto multiple buffer tx enable */
0147
0148 /* Bitfields in CFG */
0149 #define ATC_PER_MSB(h)  ((0x30U & (h)) >> 4)    /* Extract most significant bits of a handshaking identifier */
0150
0151 #define ATC_SRC_PER(h)      (0xFU & (h))    /* Channel src rq associated with periph handshaking ifc h */
0152 #define ATC_DST_PER(h)      ((0xFU & (h)) <<  4)    /* Channel dst rq associated with periph handshaking ifc h */
0153 #define ATC_SRC_REP     (0x1 <<  8) /* Source Replay Mod */
0154 #define ATC_SRC_H2SEL       (0x1 <<  9) /* Source Handshaking Mod */
0155 #define     ATC_SRC_H2SEL_SW    (0x0 <<  9)
0156 #define     ATC_SRC_H2SEL_HW    (0x1 <<  9)
0157 #define ATC_SRC_PER_MSB(h)  (ATC_PER_MSB(h) << 10)  /* Channel src rq (most significant bits) */
0158 #define ATC_DST_REP     (0x1 << 12) /* Destination Replay Mod */
0159 #define ATC_DST_H2SEL       (0x1 << 13) /* Destination Handshaking Mod */
0160 #define     ATC_DST_H2SEL_SW    (0x0 << 13)
0161 #define     ATC_DST_H2SEL_HW    (0x1 << 13)
0162 #define ATC_DST_PER_MSB(h)  (ATC_PER_MSB(h) << 14)  /* Channel dst rq (most significant bits) */
0163 #define ATC_SOD         (0x1 << 16) /* Stop On Done */
0164 #define ATC_LOCK_IF     (0x1 << 20) /* Interface Lock */
0165 #define ATC_LOCK_B      (0x1 << 21) /* AHB Bus Lock */
0166 #define ATC_LOCK_IF_L       (0x1 << 22) /* Master Interface Arbiter Lock */
0167 #define     ATC_LOCK_IF_L_CHUNK (0x0 << 22)
0168 #define     ATC_LOCK_IF_L_BUFFER    (0x1 << 22)
0169 #define ATC_AHB_PROT_MASK   (0x7 << 24) /* AHB Protection */
0170 #define ATC_FIFOCFG_MASK    (0x3 << 28) /* FIFO Request Configuration */
0171 #define     ATC_FIFOCFG_LARGESTBURST    (0x0 << 28)
0172 #define     ATC_FIFOCFG_HALFFIFO        (0x1 << 28)
0173 #define     ATC_FIFOCFG_ENOUGHSPACE     (0x2 << 28)
0174
0175 /* Bitfields in SPIP */
0176 #define ATC_SPIP_HOLE(x)    (0xFFFFU & (x))
0177 #define ATC_SPIP_BOUNDARY(x)    ((0x3FF & (x)) << 16)
0178
0179 /* Bitfields in DPIP */
0180 #define ATC_DPIP_HOLE(x)    (0xFFFFU & (x))
0181 #define ATC_DPIP_BOUNDARY(x)    ((0x3FF & (x)) << 16)
0182
0183
0184 /*--  descriptors  -----------------------------------------------------*/
0185
0186 /* LLI == Linked List Item; aka DMA buffer descriptor */
0187 struct at_lli {
0188     /* values that are not changed by hardware */
0189     dma_addr_t  saddr;
0190     dma_addr_t  daddr;
0191     /* value that may get written back: */
0192     u32     ctrla;
0193     /* more values that are not changed by hardware */
0194     u32     ctrlb;
0195     dma_addr_t  dscr;   /* chain to next lli */
0196 };
0197
0198 /**
0199  * struct at_desc - software descriptor
0200  * @at_lli: hardware lli structure
0201  * @txd: support for the async_tx api
0202  * @desc_node: node on the channed descriptors list
0203  * @len: descriptor byte count
0204  * @total_len: total transaction byte count
0205  */
0206 struct at_desc {
0207     /* FIRST values the hardware uses */
0208     struct at_lli           lli;
0209
0210     /* THEN values for driver housekeeping */
0211     struct list_head        tx_list;
0212     struct dma_async_tx_descriptor  txd;
0213     struct list_head        desc_node;
0214     size_t              len;
0215     size_t              total_len;
0216
0217     /* Interleaved data */
0218     size_t              boundary;
0219     size_t              dst_hole;
0220     size_t              src_hole;
0221
0222     /* Memset temporary buffer */
0223     bool                memset_buffer;
0224     dma_addr_t          memset_paddr;
0225     int             *memset_vaddr;
0226 };
0227
0228 static inline struct at_desc *
0229 txd_to_at_desc(struct dma_async_tx_descriptor *txd)
0230 {
0231     return container_of(txd, struct at_desc, txd);
0232 }
0233
0234
0235 /*--  Channels  --------------------------------------------------------*/
0236
0237 /**
0238  * atc_status - information bits stored in channel status flag
0239  *
0240  * Manipulated with atomic operations.
0241  */
0242 enum atc_status {
0243     ATC_IS_ERROR = 0,
0244     ATC_IS_PAUSED = 1,
0245     ATC_IS_CYCLIC = 24,
0246 };
0247
0248 /**
0249  * struct at_dma_chan - internal representation of an Atmel HDMAC channel
0250  * @chan_common: common dmaengine channel object members
0251  * @device: parent device
0252  * @ch_regs: memory mapped register base
0253  * @mask: channel index in a mask
0254  * @per_if: peripheral interface
0255  * @mem_if: memory interface
0256  * @status: transmit status information from irq/prep* functions
0257  *                to tasklet (use atomic operations)
0258  * @tasklet: bottom half to finish transaction work
0259  * @save_cfg: configuration register that is saved on suspend/resume cycle
0260  * @save_dscr: for cyclic operations, preserve next descriptor address in
0261  *             the cyclic list on suspend/resume cycle
0262  * @dma_sconfig: configuration for slave transfers, passed via
0263  * .device_config
0264  * @lock: serializes enqueue/dequeue operations to descriptors lists
0265  * @active_list: list of descriptors dmaengine is being running on
0266  * @queue: list of descriptors ready to be submitted to engine
0267  * @free_list: list of descriptors usable by the channel
0268  */
0269 struct at_dma_chan {
0270     struct dma_chan     chan_common;
0271     struct at_dma       *device;
0272     void __iomem        *ch_regs;
0273     u8          mask;
0274     u8          per_if;
0275     u8          mem_if;
0276     unsigned long       status;
0277     struct tasklet_struct   tasklet;
0278     u32         save_cfg;
0279     u32         save_dscr;
0280     struct dma_slave_config dma_sconfig;
0281
0282     spinlock_t      lock;
0283
0284     /* these other elements are all protected by lock */
0285     struct list_head    active_list;
0286     struct list_head    queue;
0287     struct list_head    free_list;
0288 };
0289
0290 #define channel_readl(atchan, name) \
0291     __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
0292
0293 #define channel_writel(atchan, name, val) \
0294     __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
0295
0296 static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
0297 {
0298     return container_of(dchan, struct at_dma_chan, chan_common);
0299 }
0300
0301 /*
0302  * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
0303  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
0304  *
0305  * This can be done by finding most significant bit set.
0306  */
0307 static inline void convert_burst(u32 *maxburst)
0308 {
0309     if (*maxburst > 1)
0310         *maxburst = fls(*maxburst) - 2;
0311     else
0312         *maxburst = 0;
0313 }
0314
0315 /*
0316  * Fix sconfig's bus width according to at_hdmac.
0317  * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
0318  */
0319 static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
0320 {
0321     switch (addr_width) {
0322     case DMA_SLAVE_BUSWIDTH_2_BYTES:
0323         return 1;
0324     case DMA_SLAVE_BUSWIDTH_4_BYTES:
0325         return 2;
0326     default:
0327         /* For 1 byte width or fallback */
0328         return 0;
0329     }
0330 }
0331
0332 /*--  Controller  ------------------------------------------------------*/
0333
0334 /**
0335  * struct at_dma - internal representation of an Atmel HDMA Controller
0336  * @chan_common: common dmaengine dma_device object members
0337  * @atdma_devtype: identifier of DMA controller compatibility
0338  * @ch_regs: memory mapped register base
0339  * @clk: dma controller clock
0340  * @save_imr: interrupt mask register that is saved on suspend/resume cycle
0341  * @all_chan_mask: all channels availlable in a mask
0342  * @dma_desc_pool: base of DMA descriptor region (DMA address)
0343  * @chan: channels table to store at_dma_chan structures
0344  */
0345 struct at_dma {
0346     struct dma_device   dma_common;
0347     void __iomem        *regs;
0348     struct clk      *clk;
0349     u32         save_imr;
0350
0351     u8          all_chan_mask;
0352
0353     struct dma_pool     *dma_desc_pool;
0354     struct dma_pool     *memset_pool;
0355     /* AT THE END channels table */
0356     struct at_dma_chan  chan[];
0357 };
0358
0359 #define dma_readl(atdma, name) \
0360     __raw_readl((atdma)->regs + AT_DMA_##name)
0361 #define dma_writel(atdma, name, val) \
0362     __raw_writel((val), (atdma)->regs + AT_DMA_##name)
0363
0364 static inline struct at_dma *to_at_dma(struct dma_device *ddev)
0365 {
0366     return container_of(ddev, struct at_dma, dma_common);
0367 }
0368
0369
0370 /*--  Helper functions  ------------------------------------------------*/
0371
0372 static struct device *chan2dev(struct dma_chan *chan)
0373 {
0374     return &chan->dev->device;
0375 }
0376
0377 #if defined(VERBOSE_DEBUG)
0378 static void vdbg_dump_regs(struct at_dma_chan *atchan)
0379 {
0380     struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
0381
0382     dev_err(chan2dev(&atchan->chan_common),
0383         "  channel %d : imr = 0x%x, chsr = 0x%x\n",
0384         atchan->chan_common.chan_id,
0385         dma_readl(atdma, EBCIMR),
0386         dma_readl(atdma, CHSR));
0387
0388     dev_err(chan2dev(&atchan->chan_common),
0389         "  channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
0390         channel_readl(atchan, SADDR),
0391         channel_readl(atchan, DADDR),
0392         channel_readl(atchan, CTRLA),
0393         channel_readl(atchan, CTRLB),
0394         channel_readl(atchan, CFG),
0395         channel_readl(atchan, DSCR));
0396 }
0397 #else
0398 static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
0399 #endif
0400
0401 static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
0402 {
0403     dev_crit(chan2dev(&atchan->chan_common),
0404          "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n",
0405          &lli->saddr, &lli->daddr,
0406          lli->ctrla, lli->ctrlb, &lli->dscr);
0407 }
0408
0409
0410 static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
0411 {
0412     u32 ebci;
0413
0414     /* enable interrupts on buffer transfer completion & error */
0415     ebci =    AT_DMA_BTC(chan_id)
0416         | AT_DMA_ERR(chan_id);
0417     if (on)
0418         dma_writel(atdma, EBCIER, ebci);
0419     else
0420         dma_writel(atdma, EBCIDR, ebci);
0421 }
0422
0423 static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
0424 {
0425     atc_setup_irq(atdma, chan_id, 1);
0426 }
0427
0428 static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
0429 {
0430     atc_setup_irq(atdma, chan_id, 0);
0431 }
0432
0433
0434 /**
0435  * atc_chan_is_enabled - test if given channel is enabled
0436  * @atchan: channel we want to test status
0437  */
0438 static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
0439 {
0440     struct at_dma   *atdma = to_at_dma(atchan->chan_common.device);
0441
0442     return !!(dma_readl(atdma, CHSR) & atchan->mask);
0443 }
0444
0445 /**
0446  * atc_chan_is_paused - test channel pause/resume status
0447  * @atchan: channel we want to test status
0448  */
0449 static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
0450 {
0451     return test_bit(ATC_IS_PAUSED, &atchan->status);
0452 }
0453
0454 /**
0455  * atc_chan_is_cyclic - test if given channel has cyclic property set
0456  * @atchan: channel we want to test status
0457  */
0458 static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
0459 {
0460     return test_bit(ATC_IS_CYCLIC, &atchan->status);
0461 }
0462
0463 /**
0464  * set_desc_eol - set end-of-link to descriptor so it will end transfer
0465  * @desc: descriptor, signle or at the end of a chain, to end chain on
0466  */
0467 static void set_desc_eol(struct at_desc *desc)
0468 {
0469     u32 ctrlb = desc->lli.ctrlb;
0470
0471     ctrlb &= ~ATC_IEN;
0472     ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
0473
0474     desc->lli.ctrlb = ctrlb;
0475     desc->lli.dscr = 0;
0476 }
0477
0478 #endif /* AT_HDMAC_REGS_H */