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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * A devfreq driver for NVIDIA Tegra SoCs
0004  *
0005  * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
0006  * Copyright (C) 2014 Google, Inc
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/cpufreq.h>
0011 #include <linux/devfreq.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/irq.h>
0015 #include <linux/module.h>
0016 #include <linux/of_device.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_opp.h>
0019 #include <linux/reset.h>
0020 #include <linux/workqueue.h>
0021 
0022 #include <soc/tegra/fuse.h>
0023 
0024 #include "governor.h"
0025 
0026 #define ACTMON_GLB_STATUS                   0x0
0027 #define ACTMON_GLB_PERIOD_CTRL                  0x4
0028 
0029 #define ACTMON_DEV_CTRL                     0x0
0030 #define ACTMON_DEV_CTRL_K_VAL_SHIFT             10
0031 #define ACTMON_DEV_CTRL_ENB_PERIODIC                BIT(18)
0032 #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN          BIT(20)
0033 #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN          BIT(21)
0034 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT   23
0035 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT   26
0036 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN      BIT(29)
0037 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN      BIT(30)
0038 #define ACTMON_DEV_CTRL_ENB                 BIT(31)
0039 
0040 #define ACTMON_DEV_CTRL_STOP                    0x00000000
0041 
0042 #define ACTMON_DEV_UPPER_WMARK                  0x4
0043 #define ACTMON_DEV_LOWER_WMARK                  0x8
0044 #define ACTMON_DEV_INIT_AVG                 0xc
0045 #define ACTMON_DEV_AVG_UPPER_WMARK              0x10
0046 #define ACTMON_DEV_AVG_LOWER_WMARK              0x14
0047 #define ACTMON_DEV_COUNT_WEIGHT                 0x18
0048 #define ACTMON_DEV_AVG_COUNT                    0x20
0049 #define ACTMON_DEV_INTR_STATUS                  0x24
0050 
0051 #define ACTMON_INTR_STATUS_CLEAR                0xffffffff
0052 
0053 #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER           BIT(31)
0054 #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER           BIT(30)
0055 
0056 #define ACTMON_ABOVE_WMARK_WINDOW               1
0057 #define ACTMON_BELOW_WMARK_WINDOW               3
0058 #define ACTMON_BOOST_FREQ_STEP                  16000
0059 
0060 /*
0061  * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which
0062  * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128
0063  */
0064 #define ACTMON_AVERAGE_WINDOW_LOG2          6
0065 #define ACTMON_SAMPLING_PERIOD              12 /* ms */
0066 #define ACTMON_DEFAULT_AVG_BAND             6  /* 1/10 of % */
0067 
0068 #define KHZ                         1000
0069 
0070 #define KHZ_MAX                     (ULONG_MAX / KHZ)
0071 
0072 /* Assume that the bus is saturated if the utilization is 25% */
0073 #define BUS_SATURATION_RATIO                    25
0074 
0075 /**
0076  * struct tegra_devfreq_device_config - configuration specific to an ACTMON
0077  * device
0078  *
0079  * Coefficients and thresholds are percentages unless otherwise noted
0080  */
0081 struct tegra_devfreq_device_config {
0082     u32     offset;
0083     u32     irq_mask;
0084 
0085     /* Factors applied to boost_freq every consecutive watermark breach */
0086     unsigned int    boost_up_coeff;
0087     unsigned int    boost_down_coeff;
0088 
0089     /* Define the watermark bounds when applied to the current avg */
0090     unsigned int    boost_up_threshold;
0091     unsigned int    boost_down_threshold;
0092 
0093     /*
0094      * Threshold of activity (cycles translated to kHz) below which the
0095      * CPU frequency isn't to be taken into account. This is to avoid
0096      * increasing the EMC frequency when the CPU is very busy but not
0097      * accessing the bus often.
0098      */
0099     u32     avg_dependency_threshold;
0100 };
0101 
0102 enum tegra_actmon_device {
0103     MCALL = 0,
0104     MCCPU,
0105 };
0106 
0107 static const struct tegra_devfreq_device_config tegra124_device_configs[] = {
0108     {
0109         /* MCALL: All memory accesses (including from the CPUs) */
0110         .offset = 0x1c0,
0111         .irq_mask = 1 << 26,
0112         .boost_up_coeff = 200,
0113         .boost_down_coeff = 50,
0114         .boost_up_threshold = 60,
0115         .boost_down_threshold = 40,
0116     },
0117     {
0118         /* MCCPU: memory accesses from the CPUs */
0119         .offset = 0x200,
0120         .irq_mask = 1 << 25,
0121         .boost_up_coeff = 800,
0122         .boost_down_coeff = 40,
0123         .boost_up_threshold = 27,
0124         .boost_down_threshold = 10,
0125         .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
0126     },
0127 };
0128 
0129 static const struct tegra_devfreq_device_config tegra30_device_configs[] = {
0130     {
0131         /* MCALL: All memory accesses (including from the CPUs) */
0132         .offset = 0x1c0,
0133         .irq_mask = 1 << 26,
0134         .boost_up_coeff = 200,
0135         .boost_down_coeff = 50,
0136         .boost_up_threshold = 20,
0137         .boost_down_threshold = 10,
0138     },
0139     {
0140         /* MCCPU: memory accesses from the CPUs */
0141         .offset = 0x200,
0142         .irq_mask = 1 << 25,
0143         .boost_up_coeff = 800,
0144         .boost_down_coeff = 40,
0145         .boost_up_threshold = 27,
0146         .boost_down_threshold = 10,
0147         .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
0148     },
0149 };
0150 
0151 /**
0152  * struct tegra_devfreq_device - state specific to an ACTMON device
0153  *
0154  * Frequencies are in kHz.
0155  */
0156 struct tegra_devfreq_device {
0157     const struct tegra_devfreq_device_config *config;
0158     void __iomem *regs;
0159 
0160     /* Average event count sampled in the last interrupt */
0161     u32 avg_count;
0162 
0163     /*
0164      * Extra frequency to increase the target by due to consecutive
0165      * watermark breaches.
0166      */
0167     unsigned long boost_freq;
0168 
0169     /* Optimal frequency calculated from the stats for this device */
0170     unsigned long target_freq;
0171 };
0172 
0173 struct tegra_devfreq_soc_data {
0174     const struct tegra_devfreq_device_config *configs;
0175     /* Weight value for count measurements */
0176     unsigned int count_weight;
0177 };
0178 
0179 struct tegra_devfreq {
0180     struct devfreq      *devfreq;
0181 
0182     struct reset_control    *reset;
0183     struct clk      *clock;
0184     void __iomem        *regs;
0185 
0186     struct clk      *emc_clock;
0187     unsigned long       max_freq;
0188     unsigned long       cur_freq;
0189     struct notifier_block   clk_rate_change_nb;
0190 
0191     struct delayed_work cpufreq_update_work;
0192     struct notifier_block   cpu_rate_change_nb;
0193 
0194     struct tegra_devfreq_device devices[2];
0195 
0196     unsigned int        irq;
0197 
0198     bool            started;
0199 
0200     const struct tegra_devfreq_soc_data *soc;
0201 };
0202 
0203 struct tegra_actmon_emc_ratio {
0204     unsigned long cpu_freq;
0205     unsigned long emc_freq;
0206 };
0207 
0208 static const struct tegra_actmon_emc_ratio actmon_emc_ratios[] = {
0209     { 1400000,    KHZ_MAX },
0210     { 1200000,    750000 },
0211     { 1100000,    600000 },
0212     { 1000000,    500000 },
0213     {  800000,    375000 },
0214     {  500000,    200000 },
0215     {  250000,    100000 },
0216 };
0217 
0218 static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset)
0219 {
0220     return readl_relaxed(tegra->regs + offset);
0221 }
0222 
0223 static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset)
0224 {
0225     writel_relaxed(val, tegra->regs + offset);
0226 }
0227 
0228 static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset)
0229 {
0230     return readl_relaxed(dev->regs + offset);
0231 }
0232 
0233 static void device_writel(struct tegra_devfreq_device *dev, u32 val,
0234               u32 offset)
0235 {
0236     writel_relaxed(val, dev->regs + offset);
0237 }
0238 
0239 static unsigned long do_percent(unsigned long long val, unsigned int pct)
0240 {
0241     val = val * pct;
0242     do_div(val, 100);
0243 
0244     /*
0245      * High freq + high boosting percent + large polling interval are
0246      * resulting in integer overflow when watermarks are calculated.
0247      */
0248     return min_t(u64, val, U32_MAX);
0249 }
0250 
0251 static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra,
0252                        struct tegra_devfreq_device *dev)
0253 {
0254     u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ;
0255     u32 band = avg_band_freq * tegra->devfreq->profile->polling_ms;
0256     u32 avg;
0257 
0258     avg = min(dev->avg_count, U32_MAX - band);
0259     device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK);
0260 
0261     avg = max(dev->avg_count, band);
0262     device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK);
0263 }
0264 
0265 static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra,
0266                        struct tegra_devfreq_device *dev)
0267 {
0268     u32 val = tegra->cur_freq * tegra->devfreq->profile->polling_ms;
0269 
0270     device_writel(dev, do_percent(val, dev->config->boost_up_threshold),
0271               ACTMON_DEV_UPPER_WMARK);
0272 
0273     device_writel(dev, do_percent(val, dev->config->boost_down_threshold),
0274               ACTMON_DEV_LOWER_WMARK);
0275 }
0276 
0277 static void actmon_isr_device(struct tegra_devfreq *tegra,
0278                   struct tegra_devfreq_device *dev)
0279 {
0280     u32 intr_status, dev_ctrl;
0281 
0282     dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT);
0283     tegra_devfreq_update_avg_wmark(tegra, dev);
0284 
0285     intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS);
0286     dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL);
0287 
0288     if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) {
0289         /*
0290          * new_boost = min(old_boost * up_coef + step, max_freq)
0291          */
0292         dev->boost_freq = do_percent(dev->boost_freq,
0293                          dev->config->boost_up_coeff);
0294         dev->boost_freq += ACTMON_BOOST_FREQ_STEP;
0295 
0296         dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
0297 
0298         if (dev->boost_freq >= tegra->max_freq) {
0299             dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
0300             dev->boost_freq = tegra->max_freq;
0301         }
0302     } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) {
0303         /*
0304          * new_boost = old_boost * down_coef
0305          * or 0 if (old_boost * down_coef < step / 2)
0306          */
0307         dev->boost_freq = do_percent(dev->boost_freq,
0308                          dev->config->boost_down_coeff);
0309 
0310         dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
0311 
0312         if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1)) {
0313             dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
0314             dev->boost_freq = 0;
0315         }
0316     }
0317 
0318     device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL);
0319 
0320     device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
0321 }
0322 
0323 static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra,
0324                         unsigned long cpu_freq)
0325 {
0326     unsigned int i;
0327     const struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios;
0328 
0329     for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) {
0330         if (cpu_freq >= ratio->cpu_freq) {
0331             if (ratio->emc_freq >= tegra->max_freq)
0332                 return tegra->max_freq;
0333             else
0334                 return ratio->emc_freq;
0335         }
0336     }
0337 
0338     return 0;
0339 }
0340 
0341 static unsigned long actmon_device_target_freq(struct tegra_devfreq *tegra,
0342                            struct tegra_devfreq_device *dev)
0343 {
0344     unsigned int avg_sustain_coef;
0345     unsigned long target_freq;
0346 
0347     target_freq = dev->avg_count / tegra->devfreq->profile->polling_ms;
0348     avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold;
0349     target_freq = do_percent(target_freq, avg_sustain_coef);
0350 
0351     return target_freq;
0352 }
0353 
0354 static void actmon_update_target(struct tegra_devfreq *tegra,
0355                  struct tegra_devfreq_device *dev)
0356 {
0357     unsigned long cpu_freq = 0;
0358     unsigned long static_cpu_emc_freq = 0;
0359 
0360     dev->target_freq = actmon_device_target_freq(tegra, dev);
0361 
0362     if (dev->config->avg_dependency_threshold &&
0363         dev->config->avg_dependency_threshold <= dev->target_freq) {
0364         cpu_freq = cpufreq_quick_get(0);
0365         static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
0366 
0367         dev->target_freq += dev->boost_freq;
0368         dev->target_freq = max(dev->target_freq, static_cpu_emc_freq);
0369     } else {
0370         dev->target_freq += dev->boost_freq;
0371     }
0372 }
0373 
0374 static irqreturn_t actmon_thread_isr(int irq, void *data)
0375 {
0376     struct tegra_devfreq *tegra = data;
0377     bool handled = false;
0378     unsigned int i;
0379     u32 val;
0380 
0381     mutex_lock(&tegra->devfreq->lock);
0382 
0383     val = actmon_readl(tegra, ACTMON_GLB_STATUS);
0384     for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
0385         if (val & tegra->devices[i].config->irq_mask) {
0386             actmon_isr_device(tegra, tegra->devices + i);
0387             handled = true;
0388         }
0389     }
0390 
0391     if (handled)
0392         update_devfreq(tegra->devfreq);
0393 
0394     mutex_unlock(&tegra->devfreq->lock);
0395 
0396     return handled ? IRQ_HANDLED : IRQ_NONE;
0397 }
0398 
0399 static int tegra_actmon_clk_notify_cb(struct notifier_block *nb,
0400                       unsigned long action, void *ptr)
0401 {
0402     struct clk_notifier_data *data = ptr;
0403     struct tegra_devfreq *tegra;
0404     struct tegra_devfreq_device *dev;
0405     unsigned int i;
0406 
0407     if (action != POST_RATE_CHANGE)
0408         return NOTIFY_OK;
0409 
0410     tegra = container_of(nb, struct tegra_devfreq, clk_rate_change_nb);
0411 
0412     tegra->cur_freq = data->new_rate / KHZ;
0413 
0414     for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
0415         dev = &tegra->devices[i];
0416 
0417         tegra_devfreq_update_wmark(tegra, dev);
0418     }
0419 
0420     return NOTIFY_OK;
0421 }
0422 
0423 static void tegra_actmon_delayed_update(struct work_struct *work)
0424 {
0425     struct tegra_devfreq *tegra = container_of(work, struct tegra_devfreq,
0426                            cpufreq_update_work.work);
0427 
0428     mutex_lock(&tegra->devfreq->lock);
0429     update_devfreq(tegra->devfreq);
0430     mutex_unlock(&tegra->devfreq->lock);
0431 }
0432 
0433 static unsigned long
0434 tegra_actmon_cpufreq_contribution(struct tegra_devfreq *tegra,
0435                   unsigned int cpu_freq)
0436 {
0437     struct tegra_devfreq_device *actmon_dev = &tegra->devices[MCCPU];
0438     unsigned long static_cpu_emc_freq, dev_freq;
0439 
0440     dev_freq = actmon_device_target_freq(tegra, actmon_dev);
0441 
0442     /* check whether CPU's freq is taken into account at all */
0443     if (dev_freq < actmon_dev->config->avg_dependency_threshold)
0444         return 0;
0445 
0446     static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
0447 
0448     if (dev_freq + actmon_dev->boost_freq >= static_cpu_emc_freq)
0449         return 0;
0450 
0451     return static_cpu_emc_freq;
0452 }
0453 
0454 static int tegra_actmon_cpu_notify_cb(struct notifier_block *nb,
0455                       unsigned long action, void *ptr)
0456 {
0457     struct cpufreq_freqs *freqs = ptr;
0458     struct tegra_devfreq *tegra;
0459     unsigned long old, new, delay;
0460 
0461     if (action != CPUFREQ_POSTCHANGE)
0462         return NOTIFY_OK;
0463 
0464     tegra = container_of(nb, struct tegra_devfreq, cpu_rate_change_nb);
0465 
0466     /*
0467      * Quickly check whether CPU frequency should be taken into account
0468      * at all, without blocking CPUFreq's core.
0469      */
0470     if (mutex_trylock(&tegra->devfreq->lock)) {
0471         old = tegra_actmon_cpufreq_contribution(tegra, freqs->old);
0472         new = tegra_actmon_cpufreq_contribution(tegra, freqs->new);
0473         mutex_unlock(&tegra->devfreq->lock);
0474 
0475         /*
0476          * If CPU's frequency shouldn't be taken into account at
0477          * the moment, then there is no need to update the devfreq's
0478          * state because ISR will re-check CPU's frequency on the
0479          * next interrupt.
0480          */
0481         if (old == new)
0482             return NOTIFY_OK;
0483     }
0484 
0485     /*
0486      * CPUFreq driver should support CPUFREQ_ASYNC_NOTIFICATION in order
0487      * to allow asynchronous notifications. This means we can't block
0488      * here for too long, otherwise CPUFreq's core will complain with a
0489      * warning splat.
0490      */
0491     delay = msecs_to_jiffies(ACTMON_SAMPLING_PERIOD);
0492     schedule_delayed_work(&tegra->cpufreq_update_work, delay);
0493 
0494     return NOTIFY_OK;
0495 }
0496 
0497 static void tegra_actmon_configure_device(struct tegra_devfreq *tegra,
0498                       struct tegra_devfreq_device *dev)
0499 {
0500     u32 val = 0;
0501 
0502     /* reset boosting on governor's restart */
0503     dev->boost_freq = 0;
0504 
0505     dev->target_freq = tegra->cur_freq;
0506 
0507     dev->avg_count = tegra->cur_freq * tegra->devfreq->profile->polling_ms;
0508     device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG);
0509 
0510     tegra_devfreq_update_avg_wmark(tegra, dev);
0511     tegra_devfreq_update_wmark(tegra, dev);
0512 
0513     device_writel(dev, tegra->soc->count_weight, ACTMON_DEV_COUNT_WEIGHT);
0514     device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
0515 
0516     val |= ACTMON_DEV_CTRL_ENB_PERIODIC;
0517     val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1)
0518         << ACTMON_DEV_CTRL_K_VAL_SHIFT;
0519     val |= (ACTMON_BELOW_WMARK_WINDOW - 1)
0520         << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT;
0521     val |= (ACTMON_ABOVE_WMARK_WINDOW - 1)
0522         << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT;
0523     val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
0524     val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
0525     val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
0526     val |= ACTMON_DEV_CTRL_ENB;
0527 
0528     device_writel(dev, val, ACTMON_DEV_CTRL);
0529 }
0530 
0531 static void tegra_actmon_stop_devices(struct tegra_devfreq *tegra)
0532 {
0533     struct tegra_devfreq_device *dev = tegra->devices;
0534     unsigned int i;
0535 
0536     for (i = 0; i < ARRAY_SIZE(tegra->devices); i++, dev++) {
0537         device_writel(dev, ACTMON_DEV_CTRL_STOP, ACTMON_DEV_CTRL);
0538         device_writel(dev, ACTMON_INTR_STATUS_CLEAR,
0539                   ACTMON_DEV_INTR_STATUS);
0540     }
0541 }
0542 
0543 static int tegra_actmon_resume(struct tegra_devfreq *tegra)
0544 {
0545     unsigned int i;
0546     int err;
0547 
0548     if (!tegra->devfreq->profile->polling_ms || !tegra->started)
0549         return 0;
0550 
0551     actmon_writel(tegra, tegra->devfreq->profile->polling_ms - 1,
0552               ACTMON_GLB_PERIOD_CTRL);
0553 
0554     /*
0555      * CLK notifications are needed in order to reconfigure the upper
0556      * consecutive watermark in accordance to the actual clock rate
0557      * to avoid unnecessary upper interrupts.
0558      */
0559     err = clk_notifier_register(tegra->emc_clock,
0560                     &tegra->clk_rate_change_nb);
0561     if (err) {
0562         dev_err(tegra->devfreq->dev.parent,
0563             "Failed to register rate change notifier\n");
0564         return err;
0565     }
0566 
0567     tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ;
0568 
0569     for (i = 0; i < ARRAY_SIZE(tegra->devices); i++)
0570         tegra_actmon_configure_device(tegra, &tegra->devices[i]);
0571 
0572     /*
0573      * We are estimating CPU's memory bandwidth requirement based on
0574      * amount of memory accesses and system's load, judging by CPU's
0575      * frequency. We also don't want to receive events about CPU's
0576      * frequency transaction when governor is stopped, hence notifier
0577      * is registered dynamically.
0578      */
0579     err = cpufreq_register_notifier(&tegra->cpu_rate_change_nb,
0580                     CPUFREQ_TRANSITION_NOTIFIER);
0581     if (err) {
0582         dev_err(tegra->devfreq->dev.parent,
0583             "Failed to register rate change notifier: %d\n", err);
0584         goto err_stop;
0585     }
0586 
0587     enable_irq(tegra->irq);
0588 
0589     return 0;
0590 
0591 err_stop:
0592     tegra_actmon_stop_devices(tegra);
0593 
0594     clk_notifier_unregister(tegra->emc_clock, &tegra->clk_rate_change_nb);
0595 
0596     return err;
0597 }
0598 
0599 static int tegra_actmon_start(struct tegra_devfreq *tegra)
0600 {
0601     int ret = 0;
0602 
0603     if (!tegra->started) {
0604         tegra->started = true;
0605 
0606         ret = tegra_actmon_resume(tegra);
0607         if (ret)
0608             tegra->started = false;
0609     }
0610 
0611     return ret;
0612 }
0613 
0614 static void tegra_actmon_pause(struct tegra_devfreq *tegra)
0615 {
0616     if (!tegra->devfreq->profile->polling_ms || !tegra->started)
0617         return;
0618 
0619     disable_irq(tegra->irq);
0620 
0621     cpufreq_unregister_notifier(&tegra->cpu_rate_change_nb,
0622                     CPUFREQ_TRANSITION_NOTIFIER);
0623 
0624     cancel_delayed_work_sync(&tegra->cpufreq_update_work);
0625 
0626     tegra_actmon_stop_devices(tegra);
0627 
0628     clk_notifier_unregister(tegra->emc_clock, &tegra->clk_rate_change_nb);
0629 }
0630 
0631 static void tegra_actmon_stop(struct tegra_devfreq *tegra)
0632 {
0633     tegra_actmon_pause(tegra);
0634     tegra->started = false;
0635 }
0636 
0637 static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
0638                 u32 flags)
0639 {
0640     struct dev_pm_opp *opp;
0641     int ret;
0642 
0643     opp = devfreq_recommended_opp(dev, freq, flags);
0644     if (IS_ERR(opp)) {
0645         dev_err(dev, "Failed to find opp for %lu Hz\n", *freq);
0646         return PTR_ERR(opp);
0647     }
0648 
0649     ret = dev_pm_opp_set_opp(dev, opp);
0650     dev_pm_opp_put(opp);
0651 
0652     return ret;
0653 }
0654 
0655 static int tegra_devfreq_get_dev_status(struct device *dev,
0656                     struct devfreq_dev_status *stat)
0657 {
0658     struct tegra_devfreq *tegra = dev_get_drvdata(dev);
0659     struct tegra_devfreq_device *actmon_dev;
0660     unsigned long cur_freq;
0661 
0662     cur_freq = READ_ONCE(tegra->cur_freq);
0663 
0664     /* To be used by the tegra governor */
0665     stat->private_data = tegra;
0666 
0667     /* The below are to be used by the other governors */
0668     stat->current_frequency = cur_freq * KHZ;
0669 
0670     actmon_dev = &tegra->devices[MCALL];
0671 
0672     /* Number of cycles spent on memory access */
0673     stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT);
0674 
0675     /* The bus can be considered to be saturated way before 100% */
0676     stat->busy_time *= 100 / BUS_SATURATION_RATIO;
0677 
0678     /* Number of cycles in a sampling period */
0679     stat->total_time = tegra->devfreq->profile->polling_ms * cur_freq;
0680 
0681     stat->busy_time = min(stat->busy_time, stat->total_time);
0682 
0683     return 0;
0684 }
0685 
0686 static struct devfreq_dev_profile tegra_devfreq_profile = {
0687     .polling_ms = ACTMON_SAMPLING_PERIOD,
0688     .target     = tegra_devfreq_target,
0689     .get_dev_status = tegra_devfreq_get_dev_status,
0690     .is_cooling_device = true,
0691 };
0692 
0693 static int tegra_governor_get_target(struct devfreq *devfreq,
0694                      unsigned long *freq)
0695 {
0696     struct devfreq_dev_status *stat;
0697     struct tegra_devfreq *tegra;
0698     struct tegra_devfreq_device *dev;
0699     unsigned long target_freq = 0;
0700     unsigned int i;
0701     int err;
0702 
0703     err = devfreq_update_stats(devfreq);
0704     if (err)
0705         return err;
0706 
0707     stat = &devfreq->last_status;
0708 
0709     tegra = stat->private_data;
0710 
0711     for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
0712         dev = &tegra->devices[i];
0713 
0714         actmon_update_target(tegra, dev);
0715 
0716         target_freq = max(target_freq, dev->target_freq);
0717     }
0718 
0719     /*
0720      * tegra-devfreq driver operates with KHz units, while OPP table
0721      * entries use Hz units. Hence we need to convert the units for the
0722      * devfreq core.
0723      */
0724     *freq = target_freq * KHZ;
0725 
0726     return 0;
0727 }
0728 
0729 static int tegra_governor_event_handler(struct devfreq *devfreq,
0730                     unsigned int event, void *data)
0731 {
0732     struct tegra_devfreq *tegra = dev_get_drvdata(devfreq->dev.parent);
0733     unsigned int *new_delay = data;
0734     int ret = 0;
0735 
0736     /*
0737      * Couple devfreq-device with the governor early because it is
0738      * needed at the moment of governor's start (used by ISR).
0739      */
0740     tegra->devfreq = devfreq;
0741 
0742     switch (event) {
0743     case DEVFREQ_GOV_START:
0744         devfreq_monitor_start(devfreq);
0745         ret = tegra_actmon_start(tegra);
0746         break;
0747 
0748     case DEVFREQ_GOV_STOP:
0749         tegra_actmon_stop(tegra);
0750         devfreq_monitor_stop(devfreq);
0751         break;
0752 
0753     case DEVFREQ_GOV_UPDATE_INTERVAL:
0754         /*
0755          * ACTMON hardware supports up to 256 milliseconds for the
0756          * sampling period.
0757          */
0758         if (*new_delay > 256) {
0759             ret = -EINVAL;
0760             break;
0761         }
0762 
0763         tegra_actmon_pause(tegra);
0764         devfreq_update_interval(devfreq, new_delay);
0765         ret = tegra_actmon_resume(tegra);
0766         break;
0767 
0768     case DEVFREQ_GOV_SUSPEND:
0769         tegra_actmon_stop(tegra);
0770         devfreq_monitor_suspend(devfreq);
0771         break;
0772 
0773     case DEVFREQ_GOV_RESUME:
0774         devfreq_monitor_resume(devfreq);
0775         ret = tegra_actmon_start(tegra);
0776         break;
0777     }
0778 
0779     return ret;
0780 }
0781 
0782 static struct devfreq_governor tegra_devfreq_governor = {
0783     .name = "tegra_actmon",
0784     .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL,
0785     .flags = DEVFREQ_GOV_FLAG_IMMUTABLE
0786         | DEVFREQ_GOV_FLAG_IRQ_DRIVEN,
0787     .get_target_freq = tegra_governor_get_target,
0788     .event_handler = tegra_governor_event_handler,
0789 };
0790 
0791 static void devm_tegra_devfreq_deinit_hw(void *data)
0792 {
0793     struct tegra_devfreq *tegra = data;
0794 
0795     reset_control_reset(tegra->reset);
0796     clk_disable_unprepare(tegra->clock);
0797 }
0798 
0799 static int devm_tegra_devfreq_init_hw(struct device *dev,
0800                       struct tegra_devfreq *tegra)
0801 {
0802     int err;
0803 
0804     err = clk_prepare_enable(tegra->clock);
0805     if (err) {
0806         dev_err(dev, "Failed to prepare and enable ACTMON clock\n");
0807         return err;
0808     }
0809 
0810     err = devm_add_action_or_reset(dev, devm_tegra_devfreq_deinit_hw,
0811                        tegra);
0812     if (err)
0813         return err;
0814 
0815     err = reset_control_reset(tegra->reset);
0816     if (err) {
0817         dev_err(dev, "Failed to reset hardware: %d\n", err);
0818         return err;
0819     }
0820 
0821     return err;
0822 }
0823 
0824 static int tegra_devfreq_config_clks_nop(struct device *dev,
0825                      struct opp_table *opp_table,
0826                      struct dev_pm_opp *opp, void *data,
0827                      bool scaling_down)
0828 {
0829     /* We want to skip clk configuration via dev_pm_opp_set_opp() */
0830     return 0;
0831 }
0832 
0833 static int tegra_devfreq_probe(struct platform_device *pdev)
0834 {
0835     u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
0836     struct tegra_devfreq_device *dev;
0837     struct tegra_devfreq *tegra;
0838     struct devfreq *devfreq;
0839     unsigned int i;
0840     long rate;
0841     int err;
0842     const char *clk_names[] = { "actmon", NULL };
0843     struct dev_pm_opp_config config = {
0844         .supported_hw = &hw_version,
0845         .supported_hw_count = 1,
0846         .clk_names = clk_names,
0847         .config_clks = tegra_devfreq_config_clks_nop,
0848     };
0849 
0850     tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
0851     if (!tegra)
0852         return -ENOMEM;
0853 
0854     tegra->soc = of_device_get_match_data(&pdev->dev);
0855 
0856     tegra->regs = devm_platform_ioremap_resource(pdev, 0);
0857     if (IS_ERR(tegra->regs))
0858         return PTR_ERR(tegra->regs);
0859 
0860     tegra->reset = devm_reset_control_get(&pdev->dev, "actmon");
0861     if (IS_ERR(tegra->reset)) {
0862         dev_err(&pdev->dev, "Failed to get reset\n");
0863         return PTR_ERR(tegra->reset);
0864     }
0865 
0866     tegra->clock = devm_clk_get(&pdev->dev, "actmon");
0867     if (IS_ERR(tegra->clock)) {
0868         dev_err(&pdev->dev, "Failed to get actmon clock\n");
0869         return PTR_ERR(tegra->clock);
0870     }
0871 
0872     tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
0873     if (IS_ERR(tegra->emc_clock))
0874         return dev_err_probe(&pdev->dev, PTR_ERR(tegra->emc_clock),
0875                      "Failed to get emc clock\n");
0876 
0877     err = platform_get_irq(pdev, 0);
0878     if (err < 0)
0879         return err;
0880 
0881     tegra->irq = err;
0882 
0883     irq_set_status_flags(tegra->irq, IRQ_NOAUTOEN);
0884 
0885     err = devm_request_threaded_irq(&pdev->dev, tegra->irq, NULL,
0886                     actmon_thread_isr, IRQF_ONESHOT,
0887                     "tegra-devfreq", tegra);
0888     if (err) {
0889         dev_err(&pdev->dev, "Interrupt request failed: %d\n", err);
0890         return err;
0891     }
0892 
0893     err = devm_pm_opp_set_config(&pdev->dev, &config);
0894     if (err) {
0895         dev_err(&pdev->dev, "Failed to set OPP config: %d\n", err);
0896         return err;
0897     }
0898 
0899     err = devm_pm_opp_of_add_table_indexed(&pdev->dev, 0);
0900     if (err) {
0901         dev_err(&pdev->dev, "Failed to add OPP table: %d\n", err);
0902         return err;
0903     }
0904 
0905     err = devm_tegra_devfreq_init_hw(&pdev->dev, tegra);
0906     if (err)
0907         return err;
0908 
0909     rate = clk_round_rate(tegra->emc_clock, ULONG_MAX);
0910     if (rate <= 0) {
0911         dev_err(&pdev->dev, "Failed to round clock rate: %ld\n", rate);
0912         return rate ?: -EINVAL;
0913     }
0914 
0915     tegra->max_freq = rate / KHZ;
0916 
0917     for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
0918         dev = tegra->devices + i;
0919         dev->config = tegra->soc->configs + i;
0920         dev->regs = tegra->regs + dev->config->offset;
0921     }
0922 
0923     platform_set_drvdata(pdev, tegra);
0924 
0925     tegra->clk_rate_change_nb.notifier_call = tegra_actmon_clk_notify_cb;
0926     tegra->cpu_rate_change_nb.notifier_call = tegra_actmon_cpu_notify_cb;
0927 
0928     INIT_DELAYED_WORK(&tegra->cpufreq_update_work,
0929               tegra_actmon_delayed_update);
0930 
0931     err = devm_devfreq_add_governor(&pdev->dev, &tegra_devfreq_governor);
0932     if (err) {
0933         dev_err(&pdev->dev, "Failed to add governor: %d\n", err);
0934         return err;
0935     }
0936 
0937     tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock);
0938 
0939     devfreq = devm_devfreq_add_device(&pdev->dev, &tegra_devfreq_profile,
0940                       "tegra_actmon", NULL);
0941     if (IS_ERR(devfreq)) {
0942         dev_err(&pdev->dev, "Failed to add device: %pe\n", devfreq);
0943         return PTR_ERR(devfreq);
0944     }
0945 
0946     return 0;
0947 }
0948 
0949 static const struct tegra_devfreq_soc_data tegra124_soc = {
0950     .configs = tegra124_device_configs,
0951 
0952     /*
0953      * Activity counter is incremented every 256 memory transactions,
0954      * and each transaction takes 4 EMC clocks.
0955      */
0956     .count_weight = 4 * 256,
0957 };
0958 
0959 static const struct tegra_devfreq_soc_data tegra30_soc = {
0960     .configs = tegra30_device_configs,
0961     .count_weight = 2 * 256,
0962 };
0963 
0964 static const struct of_device_id tegra_devfreq_of_match[] = {
0965     { .compatible = "nvidia,tegra30-actmon",  .data = &tegra30_soc, },
0966     { .compatible = "nvidia,tegra124-actmon", .data = &tegra124_soc, },
0967     { },
0968 };
0969 
0970 MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match);
0971 
0972 static struct platform_driver tegra_devfreq_driver = {
0973     .probe  = tegra_devfreq_probe,
0974     .driver = {
0975         .name = "tegra-devfreq",
0976         .of_match_table = tegra_devfreq_of_match,
0977     },
0978 };
0979 module_platform_driver(tegra_devfreq_driver);
0980 
0981 MODULE_LICENSE("GPL v2");
0982 MODULE_DESCRIPTION("Tegra devfreq driver");
0983 MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>");
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