drivers/devfreq/rk3399_dmc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
0004  * Author: Lin Huang <hl@rock-chips.com>
0005  */
0006
0007 #include <linux/arm-smccc.h>
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/devfreq.h>
0012 #include <linux/devfreq-event.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_opp.h>
0019 #include <linux/regmap.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/rwsem.h>
0022 #include <linux/suspend.h>
0023
0024 #include <soc/rockchip/pm_domains.h>
0025 #include <soc/rockchip/rk3399_grf.h>
0026 #include <soc/rockchip/rockchip_sip.h>
0027
0028 #define NS_TO_CYCLE(NS, MHz)                (((NS) * (MHz)) / NSEC_PER_USEC)
0029
0030 #define RK3399_SET_ODT_PD_0_SR_IDLE         GENMASK(7, 0)
0031 #define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE     GENMASK(15, 8)
0032 #define RK3399_SET_ODT_PD_0_STANDBY_IDLE        GENMASK(31, 16)
0033
0034 #define RK3399_SET_ODT_PD_1_PD_IDLE         GENMASK(11, 0)
0035 #define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE      GENMASK(27, 16)
0036
0037 #define RK3399_SET_ODT_PD_2_ODT_ENABLE          BIT(0)
0038
0039 struct rk3399_dmcfreq {
0040     struct device *dev;
0041     struct devfreq *devfreq;
0042     struct devfreq_dev_profile profile;
0043     struct devfreq_simple_ondemand_data ondemand_data;
0044     struct clk *dmc_clk;
0045     struct devfreq_event_dev *edev;
0046     struct mutex lock;
0047     struct regulator *vdd_center;
0048     struct regmap *regmap_pmu;
0049     unsigned long rate, target_rate;
0050     unsigned long volt, target_volt;
0051     unsigned int odt_dis_freq;
0052
0053     unsigned int pd_idle_ns;
0054     unsigned int sr_idle_ns;
0055     unsigned int sr_mc_gate_idle_ns;
0056     unsigned int srpd_lite_idle_ns;
0057     unsigned int standby_idle_ns;
0058     unsigned int ddr3_odt_dis_freq;
0059     unsigned int lpddr3_odt_dis_freq;
0060     unsigned int lpddr4_odt_dis_freq;
0061
0062     unsigned int pd_idle_dis_freq;
0063     unsigned int sr_idle_dis_freq;
0064     unsigned int sr_mc_gate_idle_dis_freq;
0065     unsigned int srpd_lite_idle_dis_freq;
0066     unsigned int standby_idle_dis_freq;
0067 };
0068
0069 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
0070                  u32 flags)
0071 {
0072     struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
0073     struct dev_pm_opp *opp;
0074     unsigned long old_clk_rate = dmcfreq->rate;
0075     unsigned long target_volt, target_rate;
0076     unsigned int ddrcon_mhz;
0077     struct arm_smccc_res res;
0078     int err;
0079
0080     u32 odt_pd_arg0 = 0;
0081     u32 odt_pd_arg1 = 0;
0082     u32 odt_pd_arg2 = 0;
0083
0084     opp = devfreq_recommended_opp(dev, freq, flags);
0085     if (IS_ERR(opp))
0086         return PTR_ERR(opp);
0087
0088     target_rate = dev_pm_opp_get_freq(opp);
0089     target_volt = dev_pm_opp_get_voltage(opp);
0090     dev_pm_opp_put(opp);
0091
0092     if (dmcfreq->rate == target_rate)
0093         return 0;
0094
0095     mutex_lock(&dmcfreq->lock);
0096
0097     /*
0098      * Ensure power-domain transitions don't interfere with ARM Trusted
0099      * Firmware power-domain idling.
0100      */
0101     err = rockchip_pmu_block();
0102     if (err) {
0103         dev_err(dev, "Failed to block PMU: %d\n", err);
0104         goto out_unlock;
0105     }
0106
0107     /*
0108      * Some idle parameters may be based on the DDR controller clock, which
0109      * is half of the DDR frequency.
0110      * pd_idle and standby_idle are based on the controller clock cycle.
0111      * sr_idle_cycle, sr_mc_gate_idle_cycle, and srpd_lite_idle_cycle
0112      * are based on the 1024 controller clock cycle
0113      */
0114     ddrcon_mhz = target_rate / USEC_PER_SEC / 2;
0115
0116     u32p_replace_bits(&odt_pd_arg1,
0117               NS_TO_CYCLE(dmcfreq->pd_idle_ns, ddrcon_mhz),
0118               RK3399_SET_ODT_PD_1_PD_IDLE);
0119     u32p_replace_bits(&odt_pd_arg0,
0120               NS_TO_CYCLE(dmcfreq->standby_idle_ns, ddrcon_mhz),
0121               RK3399_SET_ODT_PD_0_STANDBY_IDLE);
0122     u32p_replace_bits(&odt_pd_arg0,
0123               DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_idle_ns,
0124                            ddrcon_mhz), 1024),
0125               RK3399_SET_ODT_PD_0_SR_IDLE);
0126     u32p_replace_bits(&odt_pd_arg0,
0127               DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_mc_gate_idle_ns,
0128                            ddrcon_mhz), 1024),
0129               RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE);
0130     u32p_replace_bits(&odt_pd_arg1,
0131               DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->srpd_lite_idle_ns,
0132                            ddrcon_mhz), 1024),
0133               RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE);
0134
0135     if (dmcfreq->regmap_pmu) {
0136         if (target_rate >= dmcfreq->sr_idle_dis_freq)
0137             odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_IDLE;
0138
0139         if (target_rate >= dmcfreq->sr_mc_gate_idle_dis_freq)
0140             odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE;
0141
0142         if (target_rate >= dmcfreq->standby_idle_dis_freq)
0143             odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_STANDBY_IDLE;
0144
0145         if (target_rate >= dmcfreq->pd_idle_dis_freq)
0146             odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_PD_IDLE;
0147
0148         if (target_rate >= dmcfreq->srpd_lite_idle_dis_freq)
0149             odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE;
0150
0151         if (target_rate >= dmcfreq->odt_dis_freq)
0152             odt_pd_arg2 |= RK3399_SET_ODT_PD_2_ODT_ENABLE;
0153
0154         /*
0155          * This makes a SMC call to the TF-A to set the DDR PD
0156          * (power-down) timings and to enable or disable the
0157          * ODT (on-die termination) resistors.
0158          */
0159         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, odt_pd_arg0, odt_pd_arg1,
0160                   ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, odt_pd_arg2,
0161                   0, 0, 0, &res);
0162     }
0163
0164     /*
0165      * If frequency scaling from low to high, adjust voltage first.
0166      * If frequency scaling from high to low, adjust frequency first.
0167      */
0168     if (old_clk_rate < target_rate) {
0169         err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
0170                         target_volt);
0171         if (err) {
0172             dev_err(dev, "Cannot set voltage %lu uV\n",
0173                 target_volt);
0174             goto out;
0175         }
0176     }
0177
0178     err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
0179     if (err) {
0180         dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
0181             err);
0182         regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
0183                       dmcfreq->volt);
0184         goto out;
0185     }
0186
0187     /*
0188      * Check the dpll rate,
0189      * There only two result we will get,
0190      * 1. Ddr frequency scaling fail, we still get the old rate.
0191      * 2. Ddr frequency scaling sucessful, we get the rate we set.
0192      */
0193     dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
0194
0195     /* If get the incorrect rate, set voltage to old value. */
0196     if (dmcfreq->rate != target_rate) {
0197         dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
0198             target_rate, dmcfreq->rate);
0199         regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
0200                       dmcfreq->volt);
0201         goto out;
0202     } else if (old_clk_rate > target_rate)
0203         err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
0204                         target_volt);
0205     if (err)
0206         dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
0207
0208     dmcfreq->rate = target_rate;
0209     dmcfreq->volt = target_volt;
0210
0211 out:
0212     rockchip_pmu_unblock();
0213 out_unlock:
0214     mutex_unlock(&dmcfreq->lock);
0215     return err;
0216 }
0217
0218 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
0219                      struct devfreq_dev_status *stat)
0220 {
0221     struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
0222     struct devfreq_event_data edata;
0223     int ret = 0;
0224
0225     ret = devfreq_event_get_event(dmcfreq->edev, &edata);
0226     if (ret < 0)
0227         return ret;
0228
0229     stat->current_frequency = dmcfreq->rate;
0230     stat->busy_time = edata.load_count;
0231     stat->total_time = edata.total_count;
0232
0233     return ret;
0234 }
0235
0236 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
0237 {
0238     struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
0239
0240     *freq = dmcfreq->rate;
0241
0242     return 0;
0243 }
0244
0245 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
0246 {
0247     struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
0248     int ret = 0;
0249
0250     ret = devfreq_event_disable_edev(dmcfreq->edev);
0251     if (ret < 0) {
0252         dev_err(dev, "failed to disable the devfreq-event devices\n");
0253         return ret;
0254     }
0255
0256     ret = devfreq_suspend_device(dmcfreq->devfreq);
0257     if (ret < 0) {
0258         dev_err(dev, "failed to suspend the devfreq devices\n");
0259         return ret;
0260     }
0261
0262     return 0;
0263 }
0264
0265 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
0266 {
0267     struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
0268     int ret = 0;
0269
0270     ret = devfreq_event_enable_edev(dmcfreq->edev);
0271     if (ret < 0) {
0272         dev_err(dev, "failed to enable the devfreq-event devices\n");
0273         return ret;
0274     }
0275
0276     ret = devfreq_resume_device(dmcfreq->devfreq);
0277     if (ret < 0) {
0278         dev_err(dev, "failed to resume the devfreq devices\n");
0279         return ret;
0280     }
0281     return ret;
0282 }
0283
0284 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
0285              rk3399_dmcfreq_resume);
0286
0287 static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data,
0288                    struct device_node *np)
0289 {
0290     int ret = 0;
0291
0292     /*
0293      * These are all optional, and serve as minimum bounds. Give them large
0294      * (i.e., never "disabled") values if the DT doesn't specify one.
0295      */
0296     data->pd_idle_dis_freq =
0297         data->sr_idle_dis_freq =
0298         data->sr_mc_gate_idle_dis_freq =
0299         data->srpd_lite_idle_dis_freq =
0300         data->standby_idle_dis_freq = UINT_MAX;
0301
0302     ret |= of_property_read_u32(np, "rockchip,pd-idle-ns",
0303                     &data->pd_idle_ns);
0304     ret |= of_property_read_u32(np, "rockchip,sr-idle-ns",
0305                     &data->sr_idle_ns);
0306     ret |= of_property_read_u32(np, "rockchip,sr-mc-gate-idle-ns",
0307                     &data->sr_mc_gate_idle_ns);
0308     ret |= of_property_read_u32(np, "rockchip,srpd-lite-idle-ns",
0309                     &data->srpd_lite_idle_ns);
0310     ret |= of_property_read_u32(np, "rockchip,standby-idle-ns",
0311                     &data->standby_idle_ns);
0312     ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
0313                     &data->ddr3_odt_dis_freq);
0314     ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
0315                     &data->lpddr3_odt_dis_freq);
0316     ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
0317                     &data->lpddr4_odt_dis_freq);
0318
0319     ret |= of_property_read_u32(np, "rockchip,pd-idle-dis-freq-hz",
0320                     &data->pd_idle_dis_freq);
0321     ret |= of_property_read_u32(np, "rockchip,sr-idle-dis-freq-hz",
0322                     &data->sr_idle_dis_freq);
0323     ret |= of_property_read_u32(np, "rockchip,sr-mc-gate-idle-dis-freq-hz",
0324                     &data->sr_mc_gate_idle_dis_freq);
0325     ret |= of_property_read_u32(np, "rockchip,srpd-lite-idle-dis-freq-hz",
0326                     &data->srpd_lite_idle_dis_freq);
0327     ret |= of_property_read_u32(np, "rockchip,standby-idle-dis-freq-hz",
0328                     &data->standby_idle_dis_freq);
0329
0330     return ret;
0331 }
0332
0333 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
0334 {
0335     struct arm_smccc_res res;
0336     struct device *dev = &pdev->dev;
0337     struct device_node *np = pdev->dev.of_node, *node;
0338     struct rk3399_dmcfreq *data;
0339     int ret;
0340     struct dev_pm_opp *opp;
0341     u32 ddr_type;
0342     u32 val;
0343
0344     data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
0345     if (!data)
0346         return -ENOMEM;
0347
0348     mutex_init(&data->lock);
0349
0350     data->vdd_center = devm_regulator_get(dev, "center");
0351     if (IS_ERR(data->vdd_center))
0352         return dev_err_probe(dev, PTR_ERR(data->vdd_center),
0353                      "Cannot get the regulator \"center\"\n");
0354
0355     data->dmc_clk = devm_clk_get(dev, "dmc_clk");
0356     if (IS_ERR(data->dmc_clk))
0357         return dev_err_probe(dev, PTR_ERR(data->dmc_clk),
0358                      "Cannot get the clk dmc_clk\n");
0359
0360     data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
0361     if (IS_ERR(data->edev))
0362         return -EPROBE_DEFER;
0363
0364     ret = devfreq_event_enable_edev(data->edev);
0365     if (ret < 0) {
0366         dev_err(dev, "failed to enable devfreq-event devices\n");
0367         return ret;
0368     }
0369
0370     rk3399_dmcfreq_of_props(data, np);
0371
0372     node = of_parse_phandle(np, "rockchip,pmu", 0);
0373     if (!node)
0374         goto no_pmu;
0375
0376     data->regmap_pmu = syscon_node_to_regmap(node);
0377     of_node_put(node);
0378     if (IS_ERR(data->regmap_pmu)) {
0379         ret = PTR_ERR(data->regmap_pmu);
0380         goto err_edev;
0381     }
0382
0383     regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
0384     ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
0385             RK3399_PMUGRF_DDRTYPE_MASK;
0386
0387     switch (ddr_type) {
0388     case RK3399_PMUGRF_DDRTYPE_DDR3:
0389         data->odt_dis_freq = data->ddr3_odt_dis_freq;
0390         break;
0391     case RK3399_PMUGRF_DDRTYPE_LPDDR3:
0392         data->odt_dis_freq = data->lpddr3_odt_dis_freq;
0393         break;
0394     case RK3399_PMUGRF_DDRTYPE_LPDDR4:
0395         data->odt_dis_freq = data->lpddr4_odt_dis_freq;
0396         break;
0397     default:
0398         ret = -EINVAL;
0399         goto err_edev;
0400     }
0401
0402 no_pmu:
0403     arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
0404               ROCKCHIP_SIP_CONFIG_DRAM_INIT,
0405               0, 0, 0, 0, &res);
0406
0407     /*
0408      * We add a devfreq driver to our parent since it has a device tree node
0409      * with operating points.
0410      */
0411     if (devm_pm_opp_of_add_table(dev)) {
0412         dev_err(dev, "Invalid operating-points in device tree.\n");
0413         ret = -EINVAL;
0414         goto err_edev;
0415     }
0416
0417     data->ondemand_data.upthreshold = 25;
0418     data->ondemand_data.downdifferential = 15;
0419
0420     data->rate = clk_get_rate(data->dmc_clk);
0421
0422     opp = devfreq_recommended_opp(dev, &data->rate, 0);
0423     if (IS_ERR(opp)) {
0424         ret = PTR_ERR(opp);
0425         goto err_edev;
0426     }
0427
0428     data->rate = dev_pm_opp_get_freq(opp);
0429     data->volt = dev_pm_opp_get_voltage(opp);
0430     dev_pm_opp_put(opp);
0431
0432     data->profile = (struct devfreq_dev_profile) {
0433         .polling_ms = 200,
0434         .target     = rk3399_dmcfreq_target,
0435         .get_dev_status = rk3399_dmcfreq_get_dev_status,
0436         .get_cur_freq   = rk3399_dmcfreq_get_cur_freq,
0437         .initial_freq   = data->rate,
0438     };
0439
0440     data->devfreq = devm_devfreq_add_device(dev,
0441                        &data->profile,
0442                        DEVFREQ_GOV_SIMPLE_ONDEMAND,
0443                        &data->ondemand_data);
0444     if (IS_ERR(data->devfreq)) {
0445         ret = PTR_ERR(data->devfreq);
0446         goto err_edev;
0447     }
0448
0449     devm_devfreq_register_opp_notifier(dev, data->devfreq);
0450
0451     data->dev = dev;
0452     platform_set_drvdata(pdev, data);
0453
0454     return 0;
0455
0456 err_edev:
0457     devfreq_event_disable_edev(data->edev);
0458
0459     return ret;
0460 }
0461
0462 static int rk3399_dmcfreq_remove(struct platform_device *pdev)
0463 {
0464     struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
0465
0466     devfreq_event_disable_edev(dmcfreq->edev);
0467
0468     return 0;
0469 }
0470
0471 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
0472     { .compatible = "rockchip,rk3399-dmc" },
0473     { },
0474 };
0475 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
0476
0477 static struct platform_driver rk3399_dmcfreq_driver = {
0478     .probe  = rk3399_dmcfreq_probe,
0479     .remove = rk3399_dmcfreq_remove,
0480     .driver = {
0481         .name   = "rk3399-dmc-freq",
0482         .pm = &rk3399_dmcfreq_pm,
0483         .of_match_table = rk3399dmc_devfreq_of_match,
0484     },
0485 };
0486 module_platform_driver(rk3399_dmcfreq_driver);
0487
0488 MODULE_LICENSE("GPL v2");
0489 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
0490 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");