devfreq/event/exynos-ppmu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * exynos_ppmu.h - Exynos PPMU header file
0004  *
0005  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
0006  * Author : Chanwoo Choi <cw00.choi@samsung.com>
0007  */
0008
0009 #ifndef __EXYNOS_PPMU_H__
0010 #define __EXYNOS_PPMU_H__
0011
0012 enum ppmu_state {
0013     PPMU_DISABLE = 0,
0014     PPMU_ENABLE,
0015 };
0016
0017 enum ppmu_counter {
0018     PPMU_PMNCNT0 = 0,
0019     PPMU_PMNCNT1,
0020     PPMU_PMNCNT2,
0021     PPMU_PMNCNT3,
0022
0023     PPMU_PMNCNT_MAX,
0024 };
0025
0026 /***
0027  * PPMUv1.1 Definitions
0028  */
0029 enum ppmu_event_type {
0030     PPMU_RO_BUSY_CYCLE_CNT  = 0x0,
0031     PPMU_WO_BUSY_CYCLE_CNT  = 0x1,
0032     PPMU_RW_BUSY_CYCLE_CNT  = 0x2,
0033     PPMU_RO_REQUEST_CNT = 0x3,
0034     PPMU_WO_REQUEST_CNT = 0x4,
0035     PPMU_RO_DATA_CNT    = 0x5,
0036     PPMU_WO_DATA_CNT    = 0x6,
0037     PPMU_RO_LATENCY     = 0x12,
0038     PPMU_WO_LATENCY     = 0x16,
0039 };
0040
0041 enum ppmu_reg {
0042     /* PPC control register */
0043     PPMU_PMNC       = 0x00,
0044     PPMU_CNTENS     = 0x10,
0045     PPMU_CNTENC     = 0x20,
0046     PPMU_INTENS     = 0x30,
0047     PPMU_INTENC     = 0x40,
0048     PPMU_FLAG       = 0x50,
0049
0050     /* Cycle Counter and Performance Event Counter Register */
0051     PPMU_CCNT       = 0x100,
0052     PPMU_PMCNT0     = 0x110,
0053     PPMU_PMCNT1     = 0x120,
0054     PPMU_PMCNT2     = 0x130,
0055     PPMU_PMCNT3_HIGH    = 0x140,
0056     PPMU_PMCNT3_LOW     = 0x150,
0057
0058     /* Bus Event Generator */
0059     PPMU_BEVT0SEL       = 0x1000,
0060     PPMU_BEVT1SEL       = 0x1100,
0061     PPMU_BEVT2SEL       = 0x1200,
0062     PPMU_BEVT3SEL       = 0x1300,
0063     PPMU_COUNTER_RESET  = 0x1810,
0064     PPMU_READ_OVERFLOW_CNT  = 0x1810,
0065     PPMU_READ_UNDERFLOW_CNT = 0x1814,
0066     PPMU_WRITE_OVERFLOW_CNT = 0x1850,
0067     PPMU_WRITE_UNDERFLOW_CNT = 0x1854,
0068     PPMU_READ_PENDING_CNT   = 0x1880,
0069     PPMU_WRITE_PENDING_CNT  = 0x1884
0070 };
0071
0072 /* PMNC register */
0073 #define PPMU_PMNC_CC_RESET_SHIFT    2
0074 #define PPMU_PMNC_COUNTER_RESET_SHIFT   1
0075 #define PPMU_PMNC_ENABLE_SHIFT      0
0076 #define PPMU_PMNC_START_MODE_MASK   BIT(16)
0077 #define PPMU_PMNC_CC_DIVIDER_MASK   BIT(3)
0078 #define PPMU_PMNC_CC_RESET_MASK     BIT(2)
0079 #define PPMU_PMNC_COUNTER_RESET_MASK    BIT(1)
0080 #define PPMU_PMNC_ENABLE_MASK       BIT(0)
0081
0082 /* CNTENS/CNTENC/INTENS/INTENC/FLAG register */
0083 #define PPMU_CCNT_MASK          BIT(31)
0084 #define PPMU_PMCNT3_MASK        BIT(3)
0085 #define PPMU_PMCNT2_MASK        BIT(2)
0086 #define PPMU_PMCNT1_MASK        BIT(1)
0087 #define PPMU_PMCNT0_MASK        BIT(0)
0088
0089 /* PPMU_PMNCTx/PPMU_BETxSEL registers */
0090 #define PPMU_PMNCT(x)           (PPMU_PMCNT0 + (0x10 * x))
0091 #define PPMU_BEVTxSEL(x)        (PPMU_BEVT0SEL + (0x100 * x))
0092
0093 /***
0094  * PPMU_V2.0 definitions
0095  */
0096 enum ppmu_v2_mode {
0097     PPMU_V2_MODE_MANUAL = 0,
0098     PPMU_V2_MODE_AUTO = 1,
0099     PPMU_V2_MODE_CIG = 2,   /* CIG (Conditional Interrupt Generation) */
0100 };
0101
0102 enum ppmu_v2_event_type {
0103     PPMU_V2_RO_DATA_CNT = 0x4,
0104     PPMU_V2_WO_DATA_CNT = 0x5,
0105
0106     PPMU_V2_EVT3_RW_DATA_CNT = 0x22,    /* Only for Event3 */
0107 };
0108
0109 enum ppmu_V2_reg {
0110     /* PPC control register */
0111     PPMU_V2_PMNC        = 0x04,
0112     PPMU_V2_CNTENS      = 0x08,
0113     PPMU_V2_CNTENC      = 0x0c,
0114     PPMU_V2_INTENS      = 0x10,
0115     PPMU_V2_INTENC      = 0x14,
0116     PPMU_V2_FLAG        = 0x18,
0117
0118     /* Cycle Counter and Performance Event Counter Register */
0119     PPMU_V2_CCNT        = 0x48,
0120     PPMU_V2_PMCNT0      = 0x34,
0121     PPMU_V2_PMCNT1      = 0x38,
0122     PPMU_V2_PMCNT2      = 0x3c,
0123     PPMU_V2_PMCNT3_LOW  = 0x40,
0124     PPMU_V2_PMCNT3_HIGH = 0x44,
0125
0126     /* Bus Event Generator */
0127     PPMU_V2_CIG_CFG0        = 0x1c,
0128     PPMU_V2_CIG_CFG1        = 0x20,
0129     PPMU_V2_CIG_CFG2        = 0x24,
0130     PPMU_V2_CIG_RESULT  = 0x28,
0131     PPMU_V2_CNT_RESET   = 0x2c,
0132     PPMU_V2_CNT_AUTO        = 0x30,
0133     PPMU_V2_CH_EV0_TYPE = 0x200,
0134     PPMU_V2_CH_EV1_TYPE = 0x204,
0135     PPMU_V2_CH_EV2_TYPE = 0x208,
0136     PPMU_V2_CH_EV3_TYPE = 0x20c,
0137     PPMU_V2_SM_ID_V     = 0x220,
0138     PPMU_V2_SM_ID_A     = 0x224,
0139     PPMU_V2_SM_OTHERS_V = 0x228,
0140     PPMU_V2_SM_OTHERS_A = 0x22c,
0141     PPMU_V2_INTERRUPT_RESET = 0x260,
0142 };
0143
0144 /* PMNC register */
0145 #define PPMU_V2_PMNC_START_MODE_SHIFT   20
0146 #define PPMU_V2_PMNC_START_MODE_MASK    (0x3 << PPMU_V2_PMNC_START_MODE_SHIFT)
0147
0148 #define PPMU_PMNC_CC_RESET_SHIFT    2
0149 #define PPMU_PMNC_COUNTER_RESET_SHIFT   1
0150 #define PPMU_PMNC_ENABLE_SHIFT      0
0151 #define PPMU_PMNC_START_MODE_MASK   BIT(16)
0152 #define PPMU_PMNC_CC_DIVIDER_MASK   BIT(3)
0153 #define PPMU_PMNC_CC_RESET_MASK     BIT(2)
0154 #define PPMU_PMNC_COUNTER_RESET_MASK    BIT(1)
0155 #define PPMU_PMNC_ENABLE_MASK       BIT(0)
0156
0157 #define PPMU_V2_PMNCT(x)        (PPMU_V2_PMCNT0 + (0x4 * x))
0158 #define PPMU_V2_CH_EVx_TYPE(x)      (PPMU_V2_CH_EV0_TYPE + (0x4 * x))
0159
0160 #endif /* __EXYNOS_PPMU_H__ */