0001 # SPDX-License-Identifier: GPL-2.0-only
0002 menuconfig PM_DEVFREQ
0003 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
0004 select SRCU
0005 select PM_OPP
0006 help
0007 A device may have a list of frequencies and voltages available.
0008 devfreq, a generic DVFS framework can be registered for a device
0009 in order to let the governor provided to devfreq choose an
0010 operating frequency based on the device driver's policy.
0011
0012 Each device may have its own governor and policy. Devfreq can
0013 reevaluate the device state periodically and/or based on the
0014 notification to "nb", a notifier block, of devfreq.
0015
0016 Like some CPUs with CPUfreq, a device may have multiple clocks.
0017 However, because the clock frequencies of a single device are
0018 determined by the single device's state, an instance of devfreq
0019 is attached to a single device and returns a "representative"
0020 clock frequency of the device, which is also attached
0021 to a device by 1-to-1. The device registering devfreq takes the
0022 responsibility to "interpret" the representative frequency and
0023 to set its every clock accordingly with the "target" callback
0024 given to devfreq.
0025
0026 When OPP is used with the devfreq device, it is recommended to
0027 register devfreq's nb to the OPP's notifier head. If OPP is
0028 used with the devfreq device, you may use OPP helper
0029 functions defined in devfreq.h.
0030
0031 if PM_DEVFREQ
0032
0033 comment "DEVFREQ Governors"
0034
0035 config DEVFREQ_GOV_SIMPLE_ONDEMAND
0036 tristate "Simple Ondemand"
0037 help
0038 Chooses frequency based on the recent load on the device. Works
0039 similar as ONDEMAND governor of CPUFREQ does. A device with
0040 Simple-Ondemand should be able to provide busy/total counter
0041 values that imply the usage rate. A device may provide tuned
0042 values to the governor with data field at devfreq_add_device().
0043
0044 config DEVFREQ_GOV_PERFORMANCE
0045 tristate "Performance"
0046 help
0047 Sets the frequency at the maximum available frequency.
0048 This governor always returns UINT_MAX as frequency so that
0049 the DEVFREQ framework returns the highest frequency available
0050 at any time.
0051
0052 config DEVFREQ_GOV_POWERSAVE
0053 tristate "Powersave"
0054 help
0055 Sets the frequency at the minimum available frequency.
0056 This governor always returns 0 as frequency so that
0057 the DEVFREQ framework returns the lowest frequency available
0058 at any time.
0059
0060 config DEVFREQ_GOV_USERSPACE
0061 tristate "Userspace"
0062 help
0063 Sets the frequency at the user specified one.
0064 This governor returns the user configured frequency if there
0065 has been an input to /sys/devices/.../userspace/set_freq.
0066 Otherwise, the governor does not change the frequency
0067 given at the initialization.
0068
0069 config DEVFREQ_GOV_PASSIVE
0070 tristate "Passive"
0071 help
0072 Sets the frequency based on the frequency of its parent devfreq
0073 device. This governor does not change the frequency by itself
0074 through sysfs entries. The passive governor recommends that
0075 devfreq device uses the OPP table to get the frequency/voltage.
0076
0077 comment "DEVFREQ Drivers"
0078
0079 config ARM_EXYNOS_BUS_DEVFREQ
0080 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
0081 depends on ARCH_EXYNOS || COMPILE_TEST
0082 select DEVFREQ_GOV_SIMPLE_ONDEMAND
0083 select DEVFREQ_GOV_PASSIVE
0084 select DEVFREQ_EVENT_EXYNOS_PPMU
0085 select PM_DEVFREQ_EVENT
0086 help
0087 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
0088 Memory bus has one more group of memory bus (e.g, MIF and INT block).
0089 Each memory bus group could contain many memoby bus block. It reads
0090 PPMU counters of memory controllers by using DEVFREQ-event device
0091 and adjusts the operating frequencies and voltages with OPP support.
0092 This does not yet operate with optimal voltages.
0093
0094 config ARM_IMX_BUS_DEVFREQ
0095 tristate "i.MX Generic Bus DEVFREQ Driver"
0096 depends on ARCH_MXC || COMPILE_TEST
0097 select DEVFREQ_GOV_USERSPACE
0098 help
0099 This adds the generic DEVFREQ driver for i.MX interconnects. It
0100 allows adjusting NIC/NOC frequency.
0101
0102 config ARM_IMX8M_DDRC_DEVFREQ
0103 tristate "i.MX8M DDRC DEVFREQ Driver"
0104 depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
0105 (COMPILE_TEST && HAVE_ARM_SMCCC)
0106 select DEVFREQ_GOV_USERSPACE
0107 help
0108 This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
0109 adjusting DRAM frequency.
0110
0111 config ARM_TEGRA_DEVFREQ
0112 tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
0113 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
0114 ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
0115 ARCH_TEGRA_210_SOC || \
0116 COMPILE_TEST
0117 depends on COMMON_CLK
0118 help
0119 This adds the DEVFREQ driver for the Tegra family of SoCs.
0120 It reads ACTMON counters of memory controllers and adjusts the
0121 operating frequencies and voltages with OPP support.
0122
0123 config ARM_MEDIATEK_CCI_DEVFREQ
0124 tristate "MEDIATEK CCI DEVFREQ Driver"
0125 depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
0126 select DEVFREQ_GOV_PASSIVE
0127 help
0128 This adds a devfreq driver for MediaTek Cache Coherent Interconnect
0129 which is shared the same regulators with the cpu cluster. It can track
0130 buck voltages and update a proper CCI frequency. Use the notification
0131 to get the regulator status.
0132
0133 config ARM_RK3399_DMC_DEVFREQ
0134 tristate "ARM RK3399 DMC DEVFREQ Driver"
0135 depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
0136 (COMPILE_TEST && HAVE_ARM_SMCCC)
0137 select DEVFREQ_EVENT_ROCKCHIP_DFI
0138 select DEVFREQ_GOV_SIMPLE_ONDEMAND
0139 select PM_DEVFREQ_EVENT
0140 help
0141 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
0142 It sets the frequency for the memory controller and reads the usage counts
0143 from hardware.
0144
0145 config ARM_SUN8I_A33_MBUS_DEVFREQ
0146 tristate "sun8i/sun50i MBUS DEVFREQ Driver"
0147 depends on ARCH_SUNXI || COMPILE_TEST
0148 depends on COMMON_CLK
0149 select DEVFREQ_GOV_SIMPLE_ONDEMAND
0150 help
0151 This adds the DEVFREQ driver for the MBUS controller in some
0152 Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
0153
0154 source "drivers/devfreq/event/Kconfig"
0155
0156 endif # PM_DEVFREQ
