drivers/cxl/cxlpci.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
0003 #ifndef __CXL_PCI_H__
0004 #define __CXL_PCI_H__
0005 #include <linux/pci.h>
0006 #include "cxl.h"
0007
0008 #define CXL_MEMORY_PROGIF   0x10
0009
0010 /*
0011  * See section 8.1 Configuration Space Registers in the CXL 2.0
0012  * Specification. Names are taken straight from the specification with "CXL" and
0013  * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
0014  */
0015 #define PCI_DVSEC_HEADER1_LENGTH_MASK   GENMASK(31, 20)
0016 #define PCI_DVSEC_VENDOR_ID_CXL     0x1E98
0017
0018 /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
0019 #define CXL_DVSEC_PCIE_DEVICE                   0
0020 #define   CXL_DVSEC_CAP_OFFSET      0xA
0021 #define     CXL_DVSEC_MEM_CAPABLE   BIT(2)
0022 #define     CXL_DVSEC_HDM_COUNT_MASK    GENMASK(5, 4)
0023 #define   CXL_DVSEC_CTRL_OFFSET     0xC
0024 #define     CXL_DVSEC_MEM_ENABLE    BIT(2)
0025 #define   CXL_DVSEC_RANGE_SIZE_HIGH(i)  (0x18 + (i * 0x10))
0026 #define   CXL_DVSEC_RANGE_SIZE_LOW(i)   (0x1C + (i * 0x10))
0027 #define     CXL_DVSEC_MEM_INFO_VALID    BIT(0)
0028 #define     CXL_DVSEC_MEM_ACTIVE    BIT(1)
0029 #define     CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28)
0030 #define   CXL_DVSEC_RANGE_BASE_HIGH(i)  (0x20 + (i * 0x10))
0031 #define   CXL_DVSEC_RANGE_BASE_LOW(i)   (0x24 + (i * 0x10))
0032 #define     CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28)
0033
0034 /* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
0035 #define CXL_DVSEC_FUNCTION_MAP                  2
0036
0037 /* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
0038 #define CXL_DVSEC_PORT_EXTENSIONS               3
0039
0040 /* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
0041 #define CXL_DVSEC_PORT_GPF                  4
0042
0043 /* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
0044 #define CXL_DVSEC_DEVICE_GPF                    5
0045
0046 /* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
0047 #define CXL_DVSEC_PCIE_FLEXBUS_PORT             7
0048
0049 /* CXL 2.0 8.1.9: Register Locator DVSEC */
0050 #define CXL_DVSEC_REG_LOCATOR                   8
0051 #define   CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET           0xC
0052 #define     CXL_DVSEC_REG_LOCATOR_BIR_MASK          GENMASK(2, 0)
0053 #define     CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK         GENMASK(15, 8)
0054 #define     CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK        GENMASK(31, 16)
0055
0056 /* Register Block Identifier (RBI) */
0057 enum cxl_regloc_type {
0058     CXL_REGLOC_RBI_EMPTY = 0,
0059     CXL_REGLOC_RBI_COMPONENT,
0060     CXL_REGLOC_RBI_VIRT,
0061     CXL_REGLOC_RBI_MEMDEV,
0062     CXL_REGLOC_RBI_TYPES
0063 };
0064
0065 static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
0066                          struct cxl_register_map *map)
0067 {
0068     if (map->block_offset == U64_MAX)
0069         return CXL_RESOURCE_NONE;
0070
0071     return pci_resource_start(pdev, map->barno) + map->block_offset;
0072 }
0073
0074 int devm_cxl_port_enumerate_dports(struct cxl_port *port);
0075 struct cxl_dev_state;
0076 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
0077 void read_cdat_data(struct cxl_port *port);
0078 #endif /* __CXL_PCI_H__ */