0001 # SPDX-License-Identifier: GPL-2.0-only
0002 menuconfig CXL_BUS
0003 tristate "CXL (Compute Express Link) Devices Support"
0004 depends on PCI
0005 select PCI_DOE
0006 help
0007 CXL is a bus that is electrically compatible with PCI Express, but
0008 layers three protocols on that signalling (CXL.io, CXL.cache, and
0009 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
0010 locally, the CXL.mem protocol allows devices to be fully coherent
0011 memory targets, the CXL.io protocol is equivalent to PCI Express.
0012 Say 'y' to enable support for the configuration and management of
0013 devices supporting these protocols.
0014
0015 if CXL_BUS
0016
0017 config CXL_PCI
0018 tristate "PCI manageability"
0019 default CXL_BUS
0020 help
0021 The CXL specification defines a "CXL memory device" sub-class in the
0022 PCI "memory controller" base class of devices. Device's identified by
0023 this class code provide support for volatile and / or persistent
0024 memory to be mapped into the system address map (Host-managed Device
0025 Memory (HDM)).
0026
0027 Say 'y/m' to enable a driver that will attach to CXL memory expander
0028 devices enumerated by the memory device class code for configuration
0029 and management primarily via the mailbox interface. See Chapter 2.3
0030 Type 3 CXL Device in the CXL 2.0 specification for more details.
0031
0032 If unsure say 'm'.
0033
0034 config CXL_MEM_RAW_COMMANDS
0035 bool "RAW Command Interface for Memory Devices"
0036 depends on CXL_PCI
0037 help
0038 Enable CXL RAW command interface.
0039
0040 The CXL driver ioctl interface may assign a kernel ioctl command
0041 number for each specification defined opcode. At any given point in
0042 time the number of opcodes that the specification defines and a device
0043 may implement may exceed the kernel's set of associated ioctl function
0044 numbers. The mismatch is either by omission, specification is too new,
0045 or by design. When prototyping new hardware, or developing / debugging
0046 the driver it is useful to be able to submit any possible command to
0047 the hardware, even commands that may crash the kernel due to their
0048 potential impact to memory currently in use by the kernel.
0049
0050 If developing CXL hardware or the driver say Y, otherwise say N.
0051
0052 config CXL_ACPI
0053 tristate "CXL ACPI: Platform Support"
0054 depends on ACPI
0055 default CXL_BUS
0056 select ACPI_TABLE_LIB
0057 help
0058 Enable support for host managed device memory (HDM) resources
0059 published by a platform's ACPI CXL memory layout description. See
0060 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
0061 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
0062 (https://www.computeexpresslink.org/spec-landing). The CXL core
0063 consumes these resource to publish the root of a cxl_port decode
0064 hierarchy to map regions that represent System RAM, or Persistent
0065 Memory regions to be managed by LIBNVDIMM.
0066
0067 If unsure say 'm'.
0068
0069 config CXL_PMEM
0070 tristate "CXL PMEM: Persistent Memory Support"
0071 depends on LIBNVDIMM
0072 default CXL_BUS
0073 help
0074 In addition to typical memory resources a platform may also advertise
0075 support for persistent memory attached via CXL. This support is
0076 managed via a bridge driver from CXL to the LIBNVDIMM system
0077 subsystem. Say 'y/m' to enable support for enumerating and
0078 provisioning the persistent memory capacity of CXL memory expanders.
0079
0080 If unsure say 'm'.
0081
0082 config CXL_MEM
0083 tristate "CXL: Memory Expansion"
0084 depends on CXL_PCI
0085 default CXL_BUS
0086 help
0087 The CXL.mem protocol allows a device to act as a provider of "System
0088 RAM" and/or "Persistent Memory" that is fully coherent as if the
0089 memory were attached to the typical CPU memory controller. This is
0090 known as HDM "Host-managed Device Memory".
0091
0092 Say 'y/m' to enable a driver that will attach to CXL.mem devices for
0093 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
0094 specification for a detailed description of HDM.
0095
0096 If unsure say 'm'.
0097
0098 config CXL_PORT
0099 default CXL_BUS
0100 tristate
0101
0102 config CXL_SUSPEND
0103 def_bool y
0104 depends on SUSPEND && CXL_MEM
0105
0106 config CXL_REGION
0107 bool
0108 default CXL_BUS
0109 # For MAX_PHYSMEM_BITS
0110 depends on SPARSEMEM
0111 select MEMREGION
0112 select GET_FREE_REGION
0113
0114 endif
