drivers/crypto/talitos.h

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 /*
0003  * Freescale SEC (talitos) device register and descriptor header defines
0004  *
0005  * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
0006  */
0007
0008 #define TALITOS_TIMEOUT 100000
0009 #define TALITOS1_MAX_DATA_LEN 32768
0010 #define TALITOS2_MAX_DATA_LEN 65535
0011
0012 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
0013 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
0014 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
0015
0016 /* descriptor pointer entry */
0017 struct talitos_ptr {
0018     union {
0019         struct {        /* SEC2 format */
0020             __be16 len;     /* length */
0021             u8 j_extent;    /* jump to sg link table and/or extent*/
0022             u8 eptr;        /* extended address */
0023         };
0024         struct {            /* SEC1 format */
0025             __be16 res;
0026             __be16 len1;    /* length */
0027         };
0028     };
0029     __be32 ptr;     /* address */
0030 };
0031
0032 /* descriptor */
0033 struct talitos_desc {
0034     __be32 hdr;                     /* header high bits */
0035     union {
0036         __be32 hdr_lo;      /* header low bits */
0037         __be32 hdr1;        /* header for SEC1 */
0038     };
0039     struct talitos_ptr ptr[7];      /* ptr/len pair array */
0040     __be32 next_desc;       /* next descriptor (SEC1) */
0041 };
0042
0043 #define TALITOS_DESC_SIZE   (sizeof(struct talitos_desc) - sizeof(__be32))
0044
0045 /*
0046  * talitos_edesc - s/w-extended descriptor
0047  * @src_nents: number of segments in input scatterlist
0048  * @dst_nents: number of segments in output scatterlist
0049  * @iv_dma: dma address of iv for checking continuity and link table
0050  * @dma_len: length of dma mapped link_tbl space
0051  * @dma_link_tbl: bus physical address of link_tbl/buf
0052  * @desc: h/w descriptor
0053  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
0054  * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
0055  *
0056  * if decrypting (with authcheck), or either one of src_nents or dst_nents
0057  * is greater than 1, an integrity check value is concatenated to the end
0058  * of link_tbl data
0059  */
0060 struct talitos_edesc {
0061     int src_nents;
0062     int dst_nents;
0063     dma_addr_t iv_dma;
0064     int dma_len;
0065     dma_addr_t dma_link_tbl;
0066     struct talitos_desc desc;
0067     union {
0068         struct talitos_ptr link_tbl[0];
0069         u8 buf[0];
0070     };
0071 };
0072
0073 /**
0074  * talitos_request - descriptor submission request
0075  * @desc: descriptor pointer (kernel virtual)
0076  * @dma_desc: descriptor's physical bus address
0077  * @callback: whom to call when descriptor processing is done
0078  * @context: caller context (optional)
0079  */
0080 struct talitos_request {
0081     struct talitos_desc *desc;
0082     dma_addr_t dma_desc;
0083     void (*callback) (struct device *dev, struct talitos_desc *desc,
0084               void *context, int error);
0085     void *context;
0086 };
0087
0088 /* per-channel fifo management */
0089 struct talitos_channel {
0090     void __iomem *reg;
0091
0092     /* request fifo */
0093     struct talitos_request *fifo;
0094
0095     /* number of requests pending in channel h/w fifo */
0096     atomic_t submit_count ____cacheline_aligned;
0097
0098     /* request submission (head) lock */
0099     spinlock_t head_lock ____cacheline_aligned;
0100     /* index to next free descriptor request */
0101     int head;
0102
0103     /* request release (tail) lock */
0104     spinlock_t tail_lock ____cacheline_aligned;
0105     /* index to next in-progress/done descriptor request */
0106     int tail;
0107 };
0108
0109 struct talitos_private {
0110     struct device *dev;
0111     struct platform_device *ofdev;
0112     void __iomem *reg;
0113     void __iomem *reg_deu;
0114     void __iomem *reg_aesu;
0115     void __iomem *reg_mdeu;
0116     void __iomem *reg_afeu;
0117     void __iomem *reg_rngu;
0118     void __iomem *reg_pkeu;
0119     void __iomem *reg_keu;
0120     void __iomem *reg_crcu;
0121     int irq[2];
0122
0123     /* SEC global registers lock  */
0124     spinlock_t reg_lock ____cacheline_aligned;
0125
0126     /* SEC version geometry (from device tree node) */
0127     unsigned int num_channels;
0128     unsigned int chfifo_len;
0129     unsigned int exec_units;
0130     unsigned int desc_types;
0131
0132     /* SEC Compatibility info */
0133     unsigned long features;
0134
0135     /*
0136      * length of the request fifo
0137      * fifo_len is chfifo_len rounded up to next power of 2
0138      * so we can use bitwise ops to wrap
0139      */
0140     unsigned int fifo_len;
0141
0142     struct talitos_channel *chan;
0143
0144     /* next channel to be assigned next incoming descriptor */
0145     atomic_t last_chan ____cacheline_aligned;
0146
0147     /* request callback tasklet */
0148     struct tasklet_struct done_task[2];
0149
0150     /* list of registered algorithms */
0151     struct list_head alg_list;
0152
0153     /* hwrng device */
0154     struct hwrng rng;
0155     bool rng_registered;
0156 };
0157
0158 /* .features flag */
0159 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
0160 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
0161 #define TALITOS_FTR_SHA224_HWINIT 0x00000004
0162 #define TALITOS_FTR_HMAC_OK 0x00000008
0163 #define TALITOS_FTR_SEC1 0x00000010
0164
0165 /*
0166  * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
0167  * defined, we check the features which are set according to the device tree.
0168  * Otherwise, we answer true or false directly
0169  */
0170 static inline bool has_ftr_sec1(struct talitos_private *priv)
0171 {
0172     if (IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1) &&
0173         IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS2))
0174         return priv->features & TALITOS_FTR_SEC1;
0175
0176     return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1);
0177 }
0178
0179 /*
0180  * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
0181  */
0182
0183 #define ISR1_FORMAT(x)          (((x) << 28) | ((x) << 16))
0184 #define ISR2_FORMAT(x)          (((x) << 4) | (x))
0185
0186 /* global register offset addresses */
0187 #define TALITOS_MCR         0x1030  /* master control register */
0188 #define   TALITOS_MCR_RCA0      (1 << 15) /* remap channel 0 */
0189 #define   TALITOS_MCR_RCA1      (1 << 14) /* remap channel 1 */
0190 #define   TALITOS_MCR_RCA2      (1 << 13) /* remap channel 2 */
0191 #define   TALITOS_MCR_RCA3      (1 << 12) /* remap channel 3 */
0192 #define   TALITOS1_MCR_SWR      0x1000000     /* s/w reset */
0193 #define   TALITOS2_MCR_SWR      0x1     /* s/w reset */
0194 #define TALITOS_MCR_LO          0x1034
0195 #define TALITOS_IMR         0x1008  /* interrupt mask register */
0196 /* enable channel IRQs */
0197 #define   TALITOS1_IMR_INIT     ISR1_FORMAT(0xf)
0198 #define   TALITOS1_IMR_DONE     ISR1_FORMAT(0x5) /* done IRQs */
0199 /* enable channel IRQs */
0200 #define   TALITOS2_IMR_INIT     (ISR2_FORMAT(0xf) | 0x10000)
0201 #define   TALITOS2_IMR_DONE     ISR1_FORMAT(0x5) /* done IRQs */
0202 #define TALITOS_IMR_LO          0x100C
0203 #define   TALITOS1_IMR_LO_INIT      0x2000000 /* allow RNGU error IRQs */
0204 #define   TALITOS2_IMR_LO_INIT      0x20000 /* allow RNGU error IRQs */
0205 #define TALITOS_ISR         0x1010  /* interrupt status register */
0206 #define   TALITOS1_ISR_4CHERR       ISR1_FORMAT(0xa) /* 4 ch errors mask */
0207 #define   TALITOS1_ISR_4CHDONE      ISR1_FORMAT(0x5) /* 4 ch done mask */
0208 #define   TALITOS1_ISR_CH_0_ERR     (2 << 28) /* ch 0 errors mask */
0209 #define   TALITOS1_ISR_CH_0_DONE    (1 << 28) /* ch 0 done mask */
0210 #define   TALITOS1_ISR_TEA_ERR      0x00000040
0211 #define   TALITOS2_ISR_4CHERR       ISR2_FORMAT(0xa) /* 4 ch errors mask */
0212 #define   TALITOS2_ISR_4CHDONE      ISR2_FORMAT(0x5) /* 4 ch done mask */
0213 #define   TALITOS2_ISR_CH_0_ERR     2 /* ch 0 errors mask */
0214 #define   TALITOS2_ISR_CH_0_DONE    1 /* ch 0 done mask */
0215 #define   TALITOS2_ISR_CH_0_2_ERR   ISR2_FORMAT(0x2) /* ch 0, 2 err mask */
0216 #define   TALITOS2_ISR_CH_0_2_DONE  ISR2_FORMAT(0x1) /* ch 0, 2 done mask */
0217 #define   TALITOS2_ISR_CH_1_3_ERR   ISR2_FORMAT(0x8) /* ch 1, 3 err mask */
0218 #define   TALITOS2_ISR_CH_1_3_DONE  ISR2_FORMAT(0x4) /* ch 1, 3 done mask */
0219 #define TALITOS_ISR_LO          0x1014
0220 #define TALITOS_ICR         0x1018  /* interrupt clear register */
0221 #define TALITOS_ICR_LO          0x101C
0222
0223 /* channel register address stride */
0224 #define TALITOS_CH_BASE_OFFSET      0x1000  /* default channel map base */
0225 #define TALITOS1_CH_STRIDE      0x1000
0226 #define TALITOS2_CH_STRIDE      0x100
0227
0228 /* channel configuration register  */
0229 #define TALITOS_CCCR            0x8
0230 #define   TALITOS2_CCCR_CONT        0x2    /* channel continue on SEC2 */
0231 #define   TALITOS2_CCCR_RESET       0x1    /* channel reset on SEC2 */
0232 #define TALITOS_CCCR_LO         0xc
0233 #define   TALITOS_CCCR_LO_IWSE      0x80   /* chan. ICCR writeback enab. */
0234 #define   TALITOS_CCCR_LO_EAE       0x20   /* extended address enable */
0235 #define   TALITOS_CCCR_LO_CDWE      0x10   /* chan. done writeback enab. */
0236 #define   TALITOS_CCCR_LO_NE        0x8    /* fetch next descriptor enab. */
0237 #define   TALITOS_CCCR_LO_NT        0x4    /* notification type */
0238 #define   TALITOS_CCCR_LO_CDIE      0x2    /* channel done IRQ enable */
0239 #define   TALITOS1_CCCR_LO_RESET    0x1    /* channel reset on SEC1 */
0240
0241 /* CCPSR: channel pointer status register */
0242 #define TALITOS_CCPSR           0x10
0243 #define TALITOS_CCPSR_LO        0x14
0244 #define   TALITOS_CCPSR_LO_DOF      0x8000 /* double FF write oflow error */
0245 #define   TALITOS_CCPSR_LO_SOF      0x4000 /* single FF write oflow error */
0246 #define   TALITOS_CCPSR_LO_MDTE     0x2000 /* master data transfer error */
0247 #define   TALITOS_CCPSR_LO_SGDLZ    0x1000 /* s/g data len zero error */
0248 #define   TALITOS_CCPSR_LO_FPZ      0x0800 /* fetch ptr zero error */
0249 #define   TALITOS_CCPSR_LO_IDH      0x0400 /* illegal desc hdr error */
0250 #define   TALITOS_CCPSR_LO_IEU      0x0200 /* invalid EU error */
0251 #define   TALITOS_CCPSR_LO_EU       0x0100 /* EU error detected */
0252 #define   TALITOS_CCPSR_LO_GB       0x0080 /* gather boundary error */
0253 #define   TALITOS_CCPSR_LO_GRL      0x0040 /* gather return/length error */
0254 #define   TALITOS_CCPSR_LO_SB       0x0020 /* scatter boundary error */
0255 #define   TALITOS_CCPSR_LO_SRL      0x0010 /* scatter return/length error */
0256
0257 /* channel fetch fifo register */
0258 #define TALITOS_FF          0x48
0259 #define TALITOS_FF_LO           0x4c
0260
0261 /* current descriptor pointer register */
0262 #define TALITOS_CDPR            0x40
0263 #define TALITOS_CDPR_LO         0x44
0264
0265 /* descriptor buffer register */
0266 #define TALITOS_DESCBUF         0x80
0267 #define TALITOS_DESCBUF_LO      0x84
0268
0269 /* gather link table */
0270 #define TALITOS_GATHER          0xc0
0271 #define TALITOS_GATHER_LO       0xc4
0272
0273 /* scatter link table */
0274 #define TALITOS_SCATTER         0xe0
0275 #define TALITOS_SCATTER_LO      0xe4
0276
0277 /* execution unit registers base */
0278 #define TALITOS2_DEU            0x2000
0279 #define TALITOS2_AESU           0x4000
0280 #define TALITOS2_MDEU           0x6000
0281 #define TALITOS2_AFEU           0x8000
0282 #define TALITOS2_RNGU           0xa000
0283 #define TALITOS2_PKEU           0xc000
0284 #define TALITOS2_KEU            0xe000
0285 #define TALITOS2_CRCU           0xf000
0286
0287 #define TALITOS12_AESU          0x4000
0288 #define TALITOS12_DEU           0x5000
0289 #define TALITOS12_MDEU          0x6000
0290
0291 #define TALITOS10_AFEU          0x8000
0292 #define TALITOS10_DEU           0xa000
0293 #define TALITOS10_MDEU          0xc000
0294 #define TALITOS10_RNGU          0xe000
0295 #define TALITOS10_PKEU          0x10000
0296 #define TALITOS10_AESU          0x12000
0297
0298 /* execution unit interrupt status registers */
0299 #define TALITOS_EUDSR           0x10    /* data size */
0300 #define TALITOS_EUDSR_LO        0x14
0301 #define TALITOS_EURCR           0x18 /* reset control*/
0302 #define TALITOS_EURCR_LO        0x1c
0303 #define TALITOS_EUSR            0x28 /* rng status */
0304 #define TALITOS_EUSR_LO         0x2c
0305 #define TALITOS_EUISR           0x30
0306 #define TALITOS_EUISR_LO        0x34
0307 #define TALITOS_EUICR           0x38 /* int. control */
0308 #define TALITOS_EUICR_LO        0x3c
0309 #define TALITOS_EU_FIFO         0x800 /* output FIFO */
0310 #define TALITOS_EU_FIFO_LO      0x804 /* output FIFO */
0311 /* DES unit */
0312 #define   TALITOS1_DEUICR_KPE       0x00200000 /* Key Parity Error */
0313 /* message digest unit */
0314 #define   TALITOS_MDEUICR_LO_ICE    0x4000 /* integrity check IRQ enable */
0315 /* random number unit */
0316 #define   TALITOS_RNGUSR_LO_RD      0x1 /* reset done */
0317 #define   TALITOS_RNGUSR_LO_OFL     0xff0000/* output FIFO length */
0318 #define   TALITOS_RNGURCR_LO_SR     0x1 /* software reset */
0319
0320 #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256   0x28
0321 #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512     0x48
0322
0323 /*
0324  * talitos descriptor header (hdr) bits
0325  */
0326
0327 /* written back when done */
0328 #define DESC_HDR_DONE           cpu_to_be32(0xff000000)
0329 #define DESC_HDR_LO_ICCR1_MASK      cpu_to_be32(0x00180000)
0330 #define DESC_HDR_LO_ICCR1_PASS      cpu_to_be32(0x00080000)
0331 #define DESC_HDR_LO_ICCR1_FAIL      cpu_to_be32(0x00100000)
0332
0333 /* primary execution unit select */
0334 #define DESC_HDR_SEL0_MASK      cpu_to_be32(0xf0000000)
0335 #define DESC_HDR_SEL0_AFEU      cpu_to_be32(0x10000000)
0336 #define DESC_HDR_SEL0_DEU       cpu_to_be32(0x20000000)
0337 #define DESC_HDR_SEL0_MDEUA     cpu_to_be32(0x30000000)
0338 #define DESC_HDR_SEL0_MDEUB     cpu_to_be32(0xb0000000)
0339 #define DESC_HDR_SEL0_RNG       cpu_to_be32(0x40000000)
0340 #define DESC_HDR_SEL0_PKEU      cpu_to_be32(0x50000000)
0341 #define DESC_HDR_SEL0_AESU      cpu_to_be32(0x60000000)
0342 #define DESC_HDR_SEL0_KEU       cpu_to_be32(0x70000000)
0343 #define DESC_HDR_SEL0_CRCU      cpu_to_be32(0x80000000)
0344
0345 /* primary execution unit mode (MODE0) and derivatives */
0346 #define DESC_HDR_MODE0_ENCRYPT      cpu_to_be32(0x00100000)
0347 #define DESC_HDR_MODE0_AESU_MASK    cpu_to_be32(0x00600000)
0348 #define DESC_HDR_MODE0_AESU_CBC     cpu_to_be32(0x00200000)
0349 #define DESC_HDR_MODE0_AESU_CTR     cpu_to_be32(0x00600000)
0350 #define DESC_HDR_MODE0_DEU_CBC      cpu_to_be32(0x00400000)
0351 #define DESC_HDR_MODE0_DEU_3DES     cpu_to_be32(0x00200000)
0352 #define DESC_HDR_MODE0_MDEU_CONT    cpu_to_be32(0x08000000)
0353 #define DESC_HDR_MODE0_MDEU_INIT    cpu_to_be32(0x01000000)
0354 #define DESC_HDR_MODE0_MDEU_HMAC    cpu_to_be32(0x00800000)
0355 #define DESC_HDR_MODE0_MDEU_PAD     cpu_to_be32(0x00400000)
0356 #define DESC_HDR_MODE0_MDEU_SHA224  cpu_to_be32(0x00300000)
0357 #define DESC_HDR_MODE0_MDEU_MD5     cpu_to_be32(0x00200000)
0358 #define DESC_HDR_MODE0_MDEU_SHA256  cpu_to_be32(0x00100000)
0359 #define DESC_HDR_MODE0_MDEU_SHA1    cpu_to_be32(0x00000000)
0360 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
0361 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
0362 #define DESC_HDR_MODE0_MDEU_MD5_HMAC    (DESC_HDR_MODE0_MDEU_MD5 | \
0363                      DESC_HDR_MODE0_MDEU_HMAC)
0364 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
0365                      DESC_HDR_MODE0_MDEU_HMAC)
0366 #define DESC_HDR_MODE0_MDEU_SHA1_HMAC   (DESC_HDR_MODE0_MDEU_SHA1 | \
0367                      DESC_HDR_MODE0_MDEU_HMAC)
0368
0369 /* secondary execution unit select (SEL1) */
0370 #define DESC_HDR_SEL1_MASK      cpu_to_be32(0x000f0000)
0371 #define DESC_HDR_SEL1_MDEUA     cpu_to_be32(0x00030000)
0372 #define DESC_HDR_SEL1_MDEUB     cpu_to_be32(0x000b0000)
0373 #define DESC_HDR_SEL1_CRCU      cpu_to_be32(0x00080000)
0374
0375 /* secondary execution unit mode (MODE1) and derivatives */
0376 #define DESC_HDR_MODE1_MDEU_CICV    cpu_to_be32(0x00004000)
0377 #define DESC_HDR_MODE1_MDEU_INIT    cpu_to_be32(0x00001000)
0378 #define DESC_HDR_MODE1_MDEU_HMAC    cpu_to_be32(0x00000800)
0379 #define DESC_HDR_MODE1_MDEU_PAD     cpu_to_be32(0x00000400)
0380 #define DESC_HDR_MODE1_MDEU_SHA224  cpu_to_be32(0x00000300)
0381 #define DESC_HDR_MODE1_MDEU_MD5     cpu_to_be32(0x00000200)
0382 #define DESC_HDR_MODE1_MDEU_SHA256  cpu_to_be32(0x00000100)
0383 #define DESC_HDR_MODE1_MDEU_SHA1    cpu_to_be32(0x00000000)
0384 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
0385 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
0386 #define DESC_HDR_MODE1_MDEU_MD5_HMAC    (DESC_HDR_MODE1_MDEU_MD5 | \
0387                      DESC_HDR_MODE1_MDEU_HMAC)
0388 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
0389                      DESC_HDR_MODE1_MDEU_HMAC)
0390 #define DESC_HDR_MODE1_MDEU_SHA1_HMAC   (DESC_HDR_MODE1_MDEU_SHA1 | \
0391                      DESC_HDR_MODE1_MDEU_HMAC)
0392 #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
0393                      DESC_HDR_MODE1_MDEU_HMAC)
0394 #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC    (DESC_HDR_MODE1_MDEUB_SHA384 | \
0395                          DESC_HDR_MODE1_MDEU_HMAC)
0396 #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC    (DESC_HDR_MODE1_MDEUB_SHA512 | \
0397                          DESC_HDR_MODE1_MDEU_HMAC)
0398
0399 /* direction of overall data flow (DIR) */
0400 #define DESC_HDR_DIR_INBOUND        cpu_to_be32(0x00000002)
0401
0402 /* request done notification (DN) */
0403 #define DESC_HDR_DONE_NOTIFY        cpu_to_be32(0x00000001)
0404
0405 /* descriptor types */
0406 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP     cpu_to_be32(0 << 3)
0407 #define DESC_HDR_TYPE_IPSEC_ESP         cpu_to_be32(1 << 3)
0408 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU   cpu_to_be32(2 << 3)
0409 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU    cpu_to_be32(4 << 3)
0410
0411 /* link table extent field bits */
0412 #define DESC_PTR_LNKTBL_JUMP            0x80
0413 #define DESC_PTR_LNKTBL_RET         0x02
0414 #define DESC_PTR_LNKTBL_NEXT            0x01