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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * This file is part of STM32 Crypto driver for Linux.
0004  *
0005  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0006  * Author(s): Lionel DEBIEVE <lionel.debieve@st.com> for STMicroelectronics.
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/crypto.h>
0011 #include <linux/delay.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/dmaengine.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/of_device.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/reset.h>
0023 
0024 #include <crypto/engine.h>
0025 #include <crypto/hash.h>
0026 #include <crypto/md5.h>
0027 #include <crypto/scatterwalk.h>
0028 #include <crypto/sha1.h>
0029 #include <crypto/sha2.h>
0030 #include <crypto/internal/hash.h>
0031 
0032 #define HASH_CR             0x00
0033 #define HASH_DIN            0x04
0034 #define HASH_STR            0x08
0035 #define HASH_IMR            0x20
0036 #define HASH_SR             0x24
0037 #define HASH_CSR(x)         (0x0F8 + ((x) * 0x04))
0038 #define HASH_HREG(x)            (0x310 + ((x) * 0x04))
0039 #define HASH_HWCFGR         0x3F0
0040 #define HASH_VER            0x3F4
0041 #define HASH_ID             0x3F8
0042 
0043 /* Control Register */
0044 #define HASH_CR_INIT            BIT(2)
0045 #define HASH_CR_DMAE            BIT(3)
0046 #define HASH_CR_DATATYPE_POS        4
0047 #define HASH_CR_MODE            BIT(6)
0048 #define HASH_CR_MDMAT           BIT(13)
0049 #define HASH_CR_DMAA            BIT(14)
0050 #define HASH_CR_LKEY            BIT(16)
0051 
0052 #define HASH_CR_ALGO_SHA1       0x0
0053 #define HASH_CR_ALGO_MD5        0x80
0054 #define HASH_CR_ALGO_SHA224     0x40000
0055 #define HASH_CR_ALGO_SHA256     0x40080
0056 
0057 /* Interrupt */
0058 #define HASH_DINIE          BIT(0)
0059 #define HASH_DCIE           BIT(1)
0060 
0061 /* Interrupt Mask */
0062 #define HASH_MASK_CALC_COMPLETION   BIT(0)
0063 #define HASH_MASK_DATA_INPUT        BIT(1)
0064 
0065 /* Context swap register */
0066 #define HASH_CSR_REGISTER_NUMBER    53
0067 
0068 /* Status Flags */
0069 #define HASH_SR_DATA_INPUT_READY    BIT(0)
0070 #define HASH_SR_OUTPUT_READY        BIT(1)
0071 #define HASH_SR_DMA_ACTIVE      BIT(2)
0072 #define HASH_SR_BUSY            BIT(3)
0073 
0074 /* STR Register */
0075 #define HASH_STR_NBLW_MASK      GENMASK(4, 0)
0076 #define HASH_STR_DCAL           BIT(8)
0077 
0078 #define HASH_FLAGS_INIT         BIT(0)
0079 #define HASH_FLAGS_OUTPUT_READY     BIT(1)
0080 #define HASH_FLAGS_CPU          BIT(2)
0081 #define HASH_FLAGS_DMA_READY        BIT(3)
0082 #define HASH_FLAGS_DMA_ACTIVE       BIT(4)
0083 #define HASH_FLAGS_HMAC_INIT        BIT(5)
0084 #define HASH_FLAGS_HMAC_FINAL       BIT(6)
0085 #define HASH_FLAGS_HMAC_KEY     BIT(7)
0086 
0087 #define HASH_FLAGS_FINAL        BIT(15)
0088 #define HASH_FLAGS_FINUP        BIT(16)
0089 #define HASH_FLAGS_ALGO_MASK        GENMASK(21, 18)
0090 #define HASH_FLAGS_MD5          BIT(18)
0091 #define HASH_FLAGS_SHA1         BIT(19)
0092 #define HASH_FLAGS_SHA224       BIT(20)
0093 #define HASH_FLAGS_SHA256       BIT(21)
0094 #define HASH_FLAGS_ERRORS       BIT(22)
0095 #define HASH_FLAGS_HMAC         BIT(23)
0096 
0097 #define HASH_OP_UPDATE          1
0098 #define HASH_OP_FINAL           2
0099 
0100 enum stm32_hash_data_format {
0101     HASH_DATA_32_BITS       = 0x0,
0102     HASH_DATA_16_BITS       = 0x1,
0103     HASH_DATA_8_BITS        = 0x2,
0104     HASH_DATA_1_BIT         = 0x3
0105 };
0106 
0107 #define HASH_BUFLEN         256
0108 #define HASH_LONG_KEY           64
0109 #define HASH_MAX_KEY_SIZE       (SHA256_BLOCK_SIZE * 8)
0110 #define HASH_QUEUE_LENGTH       16
0111 #define HASH_DMA_THRESHOLD      50
0112 
0113 #define HASH_AUTOSUSPEND_DELAY      50
0114 
0115 struct stm32_hash_ctx {
0116     struct crypto_engine_ctx enginectx;
0117     struct stm32_hash_dev   *hdev;
0118     unsigned long       flags;
0119 
0120     u8          key[HASH_MAX_KEY_SIZE];
0121     int         keylen;
0122 };
0123 
0124 struct stm32_hash_request_ctx {
0125     struct stm32_hash_dev   *hdev;
0126     unsigned long       flags;
0127     unsigned long       op;
0128 
0129     u8 digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32));
0130     size_t          digcnt;
0131     size_t          bufcnt;
0132     size_t          buflen;
0133 
0134     /* DMA */
0135     struct scatterlist  *sg;
0136     unsigned int        offset;
0137     unsigned int        total;
0138     struct scatterlist  sg_key;
0139 
0140     dma_addr_t      dma_addr;
0141     size_t          dma_ct;
0142     int         nents;
0143 
0144     u8          data_type;
0145 
0146     u8 buffer[HASH_BUFLEN] __aligned(sizeof(u32));
0147 
0148     /* Export Context */
0149     u32         *hw_context;
0150 };
0151 
0152 struct stm32_hash_algs_info {
0153     struct ahash_alg    *algs_list;
0154     size_t          size;
0155 };
0156 
0157 struct stm32_hash_pdata {
0158     struct stm32_hash_algs_info *algs_info;
0159     size_t              algs_info_size;
0160 };
0161 
0162 struct stm32_hash_dev {
0163     struct list_head    list;
0164     struct device       *dev;
0165     struct clk      *clk;
0166     struct reset_control    *rst;
0167     void __iomem        *io_base;
0168     phys_addr_t     phys_base;
0169     u32         dma_mode;
0170     u32         dma_maxburst;
0171 
0172     struct ahash_request    *req;
0173     struct crypto_engine    *engine;
0174 
0175     int         err;
0176     unsigned long       flags;
0177 
0178     struct dma_chan     *dma_lch;
0179     struct completion   dma_completion;
0180 
0181     const struct stm32_hash_pdata   *pdata;
0182 };
0183 
0184 struct stm32_hash_drv {
0185     struct list_head    dev_list;
0186     spinlock_t      lock; /* List protection access */
0187 };
0188 
0189 static struct stm32_hash_drv stm32_hash = {
0190     .dev_list = LIST_HEAD_INIT(stm32_hash.dev_list),
0191     .lock = __SPIN_LOCK_UNLOCKED(stm32_hash.lock),
0192 };
0193 
0194 static void stm32_hash_dma_callback(void *param);
0195 
0196 static inline u32 stm32_hash_read(struct stm32_hash_dev *hdev, u32 offset)
0197 {
0198     return readl_relaxed(hdev->io_base + offset);
0199 }
0200 
0201 static inline void stm32_hash_write(struct stm32_hash_dev *hdev,
0202                     u32 offset, u32 value)
0203 {
0204     writel_relaxed(value, hdev->io_base + offset);
0205 }
0206 
0207 static inline int stm32_hash_wait_busy(struct stm32_hash_dev *hdev)
0208 {
0209     u32 status;
0210 
0211     return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status,
0212                    !(status & HASH_SR_BUSY), 10, 10000);
0213 }
0214 
0215 static void stm32_hash_set_nblw(struct stm32_hash_dev *hdev, int length)
0216 {
0217     u32 reg;
0218 
0219     reg = stm32_hash_read(hdev, HASH_STR);
0220     reg &= ~(HASH_STR_NBLW_MASK);
0221     reg |= (8U * ((length) % 4U));
0222     stm32_hash_write(hdev, HASH_STR, reg);
0223 }
0224 
0225 static int stm32_hash_write_key(struct stm32_hash_dev *hdev)
0226 {
0227     struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
0228     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
0229     u32 reg;
0230     int keylen = ctx->keylen;
0231     void *key = ctx->key;
0232 
0233     if (keylen) {
0234         stm32_hash_set_nblw(hdev, keylen);
0235 
0236         while (keylen > 0) {
0237             stm32_hash_write(hdev, HASH_DIN, *(u32 *)key);
0238             keylen -= 4;
0239             key += 4;
0240         }
0241 
0242         reg = stm32_hash_read(hdev, HASH_STR);
0243         reg |= HASH_STR_DCAL;
0244         stm32_hash_write(hdev, HASH_STR, reg);
0245 
0246         return -EINPROGRESS;
0247     }
0248 
0249     return 0;
0250 }
0251 
0252 static void stm32_hash_write_ctrl(struct stm32_hash_dev *hdev)
0253 {
0254     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
0255     struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
0256     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
0257 
0258     u32 reg = HASH_CR_INIT;
0259 
0260     if (!(hdev->flags & HASH_FLAGS_INIT)) {
0261         switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
0262         case HASH_FLAGS_MD5:
0263             reg |= HASH_CR_ALGO_MD5;
0264             break;
0265         case HASH_FLAGS_SHA1:
0266             reg |= HASH_CR_ALGO_SHA1;
0267             break;
0268         case HASH_FLAGS_SHA224:
0269             reg |= HASH_CR_ALGO_SHA224;
0270             break;
0271         case HASH_FLAGS_SHA256:
0272             reg |= HASH_CR_ALGO_SHA256;
0273             break;
0274         default:
0275             reg |= HASH_CR_ALGO_MD5;
0276         }
0277 
0278         reg |= (rctx->data_type << HASH_CR_DATATYPE_POS);
0279 
0280         if (rctx->flags & HASH_FLAGS_HMAC) {
0281             hdev->flags |= HASH_FLAGS_HMAC;
0282             reg |= HASH_CR_MODE;
0283             if (ctx->keylen > HASH_LONG_KEY)
0284                 reg |= HASH_CR_LKEY;
0285         }
0286 
0287         stm32_hash_write(hdev, HASH_IMR, HASH_DCIE);
0288 
0289         stm32_hash_write(hdev, HASH_CR, reg);
0290 
0291         hdev->flags |= HASH_FLAGS_INIT;
0292 
0293         dev_dbg(hdev->dev, "Write Control %x\n", reg);
0294     }
0295 }
0296 
0297 static void stm32_hash_append_sg(struct stm32_hash_request_ctx *rctx)
0298 {
0299     size_t count;
0300 
0301     while ((rctx->bufcnt < rctx->buflen) && rctx->total) {
0302         count = min(rctx->sg->length - rctx->offset, rctx->total);
0303         count = min(count, rctx->buflen - rctx->bufcnt);
0304 
0305         if (count <= 0) {
0306             if ((rctx->sg->length == 0) && !sg_is_last(rctx->sg)) {
0307                 rctx->sg = sg_next(rctx->sg);
0308                 continue;
0309             } else {
0310                 break;
0311             }
0312         }
0313 
0314         scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, rctx->sg,
0315                      rctx->offset, count, 0);
0316 
0317         rctx->bufcnt += count;
0318         rctx->offset += count;
0319         rctx->total -= count;
0320 
0321         if (rctx->offset == rctx->sg->length) {
0322             rctx->sg = sg_next(rctx->sg);
0323             if (rctx->sg)
0324                 rctx->offset = 0;
0325             else
0326                 rctx->total = 0;
0327         }
0328     }
0329 }
0330 
0331 static int stm32_hash_xmit_cpu(struct stm32_hash_dev *hdev,
0332                    const u8 *buf, size_t length, int final)
0333 {
0334     unsigned int count, len32;
0335     const u32 *buffer = (const u32 *)buf;
0336     u32 reg;
0337 
0338     if (final)
0339         hdev->flags |= HASH_FLAGS_FINAL;
0340 
0341     len32 = DIV_ROUND_UP(length, sizeof(u32));
0342 
0343     dev_dbg(hdev->dev, "%s: length: %zd, final: %x len32 %i\n",
0344         __func__, length, final, len32);
0345 
0346     hdev->flags |= HASH_FLAGS_CPU;
0347 
0348     stm32_hash_write_ctrl(hdev);
0349 
0350     if (stm32_hash_wait_busy(hdev))
0351         return -ETIMEDOUT;
0352 
0353     if ((hdev->flags & HASH_FLAGS_HMAC) &&
0354         (!(hdev->flags & HASH_FLAGS_HMAC_KEY))) {
0355         hdev->flags |= HASH_FLAGS_HMAC_KEY;
0356         stm32_hash_write_key(hdev);
0357         if (stm32_hash_wait_busy(hdev))
0358             return -ETIMEDOUT;
0359     }
0360 
0361     for (count = 0; count < len32; count++)
0362         stm32_hash_write(hdev, HASH_DIN, buffer[count]);
0363 
0364     if (final) {
0365         stm32_hash_set_nblw(hdev, length);
0366         reg = stm32_hash_read(hdev, HASH_STR);
0367         reg |= HASH_STR_DCAL;
0368         stm32_hash_write(hdev, HASH_STR, reg);
0369         if (hdev->flags & HASH_FLAGS_HMAC) {
0370             if (stm32_hash_wait_busy(hdev))
0371                 return -ETIMEDOUT;
0372             stm32_hash_write_key(hdev);
0373         }
0374         return -EINPROGRESS;
0375     }
0376 
0377     return 0;
0378 }
0379 
0380 static int stm32_hash_update_cpu(struct stm32_hash_dev *hdev)
0381 {
0382     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
0383     int bufcnt, err = 0, final;
0384 
0385     dev_dbg(hdev->dev, "%s flags %lx\n", __func__, rctx->flags);
0386 
0387     final = (rctx->flags & HASH_FLAGS_FINUP);
0388 
0389     while ((rctx->total >= rctx->buflen) ||
0390            (rctx->bufcnt + rctx->total >= rctx->buflen)) {
0391         stm32_hash_append_sg(rctx);
0392         bufcnt = rctx->bufcnt;
0393         rctx->bufcnt = 0;
0394         err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt, 0);
0395     }
0396 
0397     stm32_hash_append_sg(rctx);
0398 
0399     if (final) {
0400         bufcnt = rctx->bufcnt;
0401         rctx->bufcnt = 0;
0402         err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt,
0403                       (rctx->flags & HASH_FLAGS_FINUP));
0404     }
0405 
0406     return err;
0407 }
0408 
0409 static int stm32_hash_xmit_dma(struct stm32_hash_dev *hdev,
0410                    struct scatterlist *sg, int length, int mdma)
0411 {
0412     struct dma_async_tx_descriptor *in_desc;
0413     dma_cookie_t cookie;
0414     u32 reg;
0415     int err;
0416 
0417     in_desc = dmaengine_prep_slave_sg(hdev->dma_lch, sg, 1,
0418                       DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT |
0419                       DMA_CTRL_ACK);
0420     if (!in_desc) {
0421         dev_err(hdev->dev, "dmaengine_prep_slave error\n");
0422         return -ENOMEM;
0423     }
0424 
0425     reinit_completion(&hdev->dma_completion);
0426     in_desc->callback = stm32_hash_dma_callback;
0427     in_desc->callback_param = hdev;
0428 
0429     hdev->flags |= HASH_FLAGS_FINAL;
0430     hdev->flags |= HASH_FLAGS_DMA_ACTIVE;
0431 
0432     reg = stm32_hash_read(hdev, HASH_CR);
0433 
0434     if (mdma)
0435         reg |= HASH_CR_MDMAT;
0436     else
0437         reg &= ~HASH_CR_MDMAT;
0438 
0439     reg |= HASH_CR_DMAE;
0440 
0441     stm32_hash_write(hdev, HASH_CR, reg);
0442 
0443     stm32_hash_set_nblw(hdev, length);
0444 
0445     cookie = dmaengine_submit(in_desc);
0446     err = dma_submit_error(cookie);
0447     if (err)
0448         return -ENOMEM;
0449 
0450     dma_async_issue_pending(hdev->dma_lch);
0451 
0452     if (!wait_for_completion_timeout(&hdev->dma_completion,
0453                      msecs_to_jiffies(100)))
0454         err = -ETIMEDOUT;
0455 
0456     if (dma_async_is_tx_complete(hdev->dma_lch, cookie,
0457                      NULL, NULL) != DMA_COMPLETE)
0458         err = -ETIMEDOUT;
0459 
0460     if (err) {
0461         dev_err(hdev->dev, "DMA Error %i\n", err);
0462         dmaengine_terminate_all(hdev->dma_lch);
0463         return err;
0464     }
0465 
0466     return -EINPROGRESS;
0467 }
0468 
0469 static void stm32_hash_dma_callback(void *param)
0470 {
0471     struct stm32_hash_dev *hdev = param;
0472 
0473     complete(&hdev->dma_completion);
0474 
0475     hdev->flags |= HASH_FLAGS_DMA_READY;
0476 }
0477 
0478 static int stm32_hash_hmac_dma_send(struct stm32_hash_dev *hdev)
0479 {
0480     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
0481     struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
0482     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
0483     int err;
0484 
0485     if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode == 1)) {
0486         err = stm32_hash_write_key(hdev);
0487         if (stm32_hash_wait_busy(hdev))
0488             return -ETIMEDOUT;
0489     } else {
0490         if (!(hdev->flags & HASH_FLAGS_HMAC_KEY))
0491             sg_init_one(&rctx->sg_key, ctx->key,
0492                     ALIGN(ctx->keylen, sizeof(u32)));
0493 
0494         rctx->dma_ct = dma_map_sg(hdev->dev, &rctx->sg_key, 1,
0495                       DMA_TO_DEVICE);
0496         if (rctx->dma_ct == 0) {
0497             dev_err(hdev->dev, "dma_map_sg error\n");
0498             return -ENOMEM;
0499         }
0500 
0501         err = stm32_hash_xmit_dma(hdev, &rctx->sg_key, ctx->keylen, 0);
0502 
0503         dma_unmap_sg(hdev->dev, &rctx->sg_key, 1, DMA_TO_DEVICE);
0504     }
0505 
0506     return err;
0507 }
0508 
0509 static int stm32_hash_dma_init(struct stm32_hash_dev *hdev)
0510 {
0511     struct dma_slave_config dma_conf;
0512     struct dma_chan *chan;
0513     int err;
0514 
0515     memset(&dma_conf, 0, sizeof(dma_conf));
0516 
0517     dma_conf.direction = DMA_MEM_TO_DEV;
0518     dma_conf.dst_addr = hdev->phys_base + HASH_DIN;
0519     dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0520     dma_conf.src_maxburst = hdev->dma_maxburst;
0521     dma_conf.dst_maxburst = hdev->dma_maxburst;
0522     dma_conf.device_fc = false;
0523 
0524     chan = dma_request_chan(hdev->dev, "in");
0525     if (IS_ERR(chan))
0526         return PTR_ERR(chan);
0527 
0528     hdev->dma_lch = chan;
0529 
0530     err = dmaengine_slave_config(hdev->dma_lch, &dma_conf);
0531     if (err) {
0532         dma_release_channel(hdev->dma_lch);
0533         hdev->dma_lch = NULL;
0534         dev_err(hdev->dev, "Couldn't configure DMA slave.\n");
0535         return err;
0536     }
0537 
0538     init_completion(&hdev->dma_completion);
0539 
0540     return 0;
0541 }
0542 
0543 static int stm32_hash_dma_send(struct stm32_hash_dev *hdev)
0544 {
0545     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
0546     struct scatterlist sg[1], *tsg;
0547     int err = 0, len = 0, reg, ncp = 0;
0548     unsigned int i;
0549     u32 *buffer = (void *)rctx->buffer;
0550 
0551     rctx->sg = hdev->req->src;
0552     rctx->total = hdev->req->nbytes;
0553 
0554     rctx->nents = sg_nents(rctx->sg);
0555 
0556     if (rctx->nents < 0)
0557         return -EINVAL;
0558 
0559     stm32_hash_write_ctrl(hdev);
0560 
0561     if (hdev->flags & HASH_FLAGS_HMAC) {
0562         err = stm32_hash_hmac_dma_send(hdev);
0563         if (err != -EINPROGRESS)
0564             return err;
0565     }
0566 
0567     for_each_sg(rctx->sg, tsg, rctx->nents, i) {
0568         len = sg->length;
0569 
0570         sg[0] = *tsg;
0571         if (sg_is_last(sg)) {
0572             if (hdev->dma_mode == 1) {
0573                 len = (ALIGN(sg->length, 16) - 16);
0574 
0575                 ncp = sg_pcopy_to_buffer(
0576                     rctx->sg, rctx->nents,
0577                     rctx->buffer, sg->length - len,
0578                     rctx->total - sg->length + len);
0579 
0580                 sg->length = len;
0581             } else {
0582                 if (!(IS_ALIGNED(sg->length, sizeof(u32)))) {
0583                     len = sg->length;
0584                     sg->length = ALIGN(sg->length,
0585                                sizeof(u32));
0586                 }
0587             }
0588         }
0589 
0590         rctx->dma_ct = dma_map_sg(hdev->dev, sg, 1,
0591                       DMA_TO_DEVICE);
0592         if (rctx->dma_ct == 0) {
0593             dev_err(hdev->dev, "dma_map_sg error\n");
0594             return -ENOMEM;
0595         }
0596 
0597         err = stm32_hash_xmit_dma(hdev, sg, len,
0598                       !sg_is_last(sg));
0599 
0600         dma_unmap_sg(hdev->dev, sg, 1, DMA_TO_DEVICE);
0601 
0602         if (err == -ENOMEM)
0603             return err;
0604     }
0605 
0606     if (hdev->dma_mode == 1) {
0607         if (stm32_hash_wait_busy(hdev))
0608             return -ETIMEDOUT;
0609         reg = stm32_hash_read(hdev, HASH_CR);
0610         reg &= ~HASH_CR_DMAE;
0611         reg |= HASH_CR_DMAA;
0612         stm32_hash_write(hdev, HASH_CR, reg);
0613 
0614         if (ncp) {
0615             memset(buffer + ncp, 0,
0616                    DIV_ROUND_UP(ncp, sizeof(u32)) - ncp);
0617             writesl(hdev->io_base + HASH_DIN, buffer,
0618                 DIV_ROUND_UP(ncp, sizeof(u32)));
0619         }
0620         stm32_hash_set_nblw(hdev, ncp);
0621         reg = stm32_hash_read(hdev, HASH_STR);
0622         reg |= HASH_STR_DCAL;
0623         stm32_hash_write(hdev, HASH_STR, reg);
0624         err = -EINPROGRESS;
0625     }
0626 
0627     if (hdev->flags & HASH_FLAGS_HMAC) {
0628         if (stm32_hash_wait_busy(hdev))
0629             return -ETIMEDOUT;
0630         err = stm32_hash_hmac_dma_send(hdev);
0631     }
0632 
0633     return err;
0634 }
0635 
0636 static struct stm32_hash_dev *stm32_hash_find_dev(struct stm32_hash_ctx *ctx)
0637 {
0638     struct stm32_hash_dev *hdev = NULL, *tmp;
0639 
0640     spin_lock_bh(&stm32_hash.lock);
0641     if (!ctx->hdev) {
0642         list_for_each_entry(tmp, &stm32_hash.dev_list, list) {
0643             hdev = tmp;
0644             break;
0645         }
0646         ctx->hdev = hdev;
0647     } else {
0648         hdev = ctx->hdev;
0649     }
0650 
0651     spin_unlock_bh(&stm32_hash.lock);
0652 
0653     return hdev;
0654 }
0655 
0656 static bool stm32_hash_dma_aligned_data(struct ahash_request *req)
0657 {
0658     struct scatterlist *sg;
0659     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
0660     struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
0661     int i;
0662 
0663     if (req->nbytes <= HASH_DMA_THRESHOLD)
0664         return false;
0665 
0666     if (sg_nents(req->src) > 1) {
0667         if (hdev->dma_mode == 1)
0668             return false;
0669         for_each_sg(req->src, sg, sg_nents(req->src), i) {
0670             if ((!IS_ALIGNED(sg->length, sizeof(u32))) &&
0671                 (!sg_is_last(sg)))
0672                 return false;
0673         }
0674     }
0675 
0676     if (req->src->offset % 4)
0677         return false;
0678 
0679     return true;
0680 }
0681 
0682 static int stm32_hash_init(struct ahash_request *req)
0683 {
0684     struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
0685     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
0686     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0687     struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
0688 
0689     rctx->hdev = hdev;
0690 
0691     rctx->flags = HASH_FLAGS_CPU;
0692 
0693     rctx->digcnt = crypto_ahash_digestsize(tfm);
0694     switch (rctx->digcnt) {
0695     case MD5_DIGEST_SIZE:
0696         rctx->flags |= HASH_FLAGS_MD5;
0697         break;
0698     case SHA1_DIGEST_SIZE:
0699         rctx->flags |= HASH_FLAGS_SHA1;
0700         break;
0701     case SHA224_DIGEST_SIZE:
0702         rctx->flags |= HASH_FLAGS_SHA224;
0703         break;
0704     case SHA256_DIGEST_SIZE:
0705         rctx->flags |= HASH_FLAGS_SHA256;
0706         break;
0707     default:
0708         return -EINVAL;
0709     }
0710 
0711     rctx->bufcnt = 0;
0712     rctx->buflen = HASH_BUFLEN;
0713     rctx->total = 0;
0714     rctx->offset = 0;
0715     rctx->data_type = HASH_DATA_8_BITS;
0716 
0717     memset(rctx->buffer, 0, HASH_BUFLEN);
0718 
0719     if (ctx->flags & HASH_FLAGS_HMAC)
0720         rctx->flags |= HASH_FLAGS_HMAC;
0721 
0722     dev_dbg(hdev->dev, "%s Flags %lx\n", __func__, rctx->flags);
0723 
0724     return 0;
0725 }
0726 
0727 static int stm32_hash_update_req(struct stm32_hash_dev *hdev)
0728 {
0729     return stm32_hash_update_cpu(hdev);
0730 }
0731 
0732 static int stm32_hash_final_req(struct stm32_hash_dev *hdev)
0733 {
0734     struct ahash_request *req = hdev->req;
0735     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0736     int err;
0737     int buflen = rctx->bufcnt;
0738 
0739     rctx->bufcnt = 0;
0740 
0741     if (!(rctx->flags & HASH_FLAGS_CPU))
0742         err = stm32_hash_dma_send(hdev);
0743     else
0744         err = stm32_hash_xmit_cpu(hdev, rctx->buffer, buflen, 1);
0745 
0746 
0747     return err;
0748 }
0749 
0750 static void stm32_hash_copy_hash(struct ahash_request *req)
0751 {
0752     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0753     __be32 *hash = (void *)rctx->digest;
0754     unsigned int i, hashsize;
0755 
0756     switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
0757     case HASH_FLAGS_MD5:
0758         hashsize = MD5_DIGEST_SIZE;
0759         break;
0760     case HASH_FLAGS_SHA1:
0761         hashsize = SHA1_DIGEST_SIZE;
0762         break;
0763     case HASH_FLAGS_SHA224:
0764         hashsize = SHA224_DIGEST_SIZE;
0765         break;
0766     case HASH_FLAGS_SHA256:
0767         hashsize = SHA256_DIGEST_SIZE;
0768         break;
0769     default:
0770         return;
0771     }
0772 
0773     for (i = 0; i < hashsize / sizeof(u32); i++)
0774         hash[i] = cpu_to_be32(stm32_hash_read(rctx->hdev,
0775                               HASH_HREG(i)));
0776 }
0777 
0778 static int stm32_hash_finish(struct ahash_request *req)
0779 {
0780     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0781 
0782     if (!req->result)
0783         return -EINVAL;
0784 
0785     memcpy(req->result, rctx->digest, rctx->digcnt);
0786 
0787     return 0;
0788 }
0789 
0790 static void stm32_hash_finish_req(struct ahash_request *req, int err)
0791 {
0792     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0793     struct stm32_hash_dev *hdev = rctx->hdev;
0794 
0795     if (!err && (HASH_FLAGS_FINAL & hdev->flags)) {
0796         stm32_hash_copy_hash(req);
0797         err = stm32_hash_finish(req);
0798         hdev->flags &= ~(HASH_FLAGS_FINAL | HASH_FLAGS_CPU |
0799                  HASH_FLAGS_INIT | HASH_FLAGS_DMA_READY |
0800                  HASH_FLAGS_OUTPUT_READY | HASH_FLAGS_HMAC |
0801                  HASH_FLAGS_HMAC_INIT | HASH_FLAGS_HMAC_FINAL |
0802                  HASH_FLAGS_HMAC_KEY);
0803     } else {
0804         rctx->flags |= HASH_FLAGS_ERRORS;
0805     }
0806 
0807     pm_runtime_mark_last_busy(hdev->dev);
0808     pm_runtime_put_autosuspend(hdev->dev);
0809 
0810     crypto_finalize_hash_request(hdev->engine, req, err);
0811 }
0812 
0813 static int stm32_hash_hw_init(struct stm32_hash_dev *hdev,
0814                   struct stm32_hash_request_ctx *rctx)
0815 {
0816     pm_runtime_get_sync(hdev->dev);
0817 
0818     if (!(HASH_FLAGS_INIT & hdev->flags)) {
0819         stm32_hash_write(hdev, HASH_CR, HASH_CR_INIT);
0820         stm32_hash_write(hdev, HASH_STR, 0);
0821         stm32_hash_write(hdev, HASH_DIN, 0);
0822         stm32_hash_write(hdev, HASH_IMR, 0);
0823         hdev->err = 0;
0824     }
0825 
0826     return 0;
0827 }
0828 
0829 static int stm32_hash_one_request(struct crypto_engine *engine, void *areq);
0830 static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq);
0831 
0832 static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
0833                    struct ahash_request *req)
0834 {
0835     return crypto_transfer_hash_request_to_engine(hdev->engine, req);
0836 }
0837 
0838 static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq)
0839 {
0840     struct ahash_request *req = container_of(areq, struct ahash_request,
0841                          base);
0842     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
0843     struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
0844     struct stm32_hash_request_ctx *rctx;
0845 
0846     if (!hdev)
0847         return -ENODEV;
0848 
0849     hdev->req = req;
0850 
0851     rctx = ahash_request_ctx(req);
0852 
0853     dev_dbg(hdev->dev, "processing new req, op: %lu, nbytes %d\n",
0854         rctx->op, req->nbytes);
0855 
0856     return stm32_hash_hw_init(hdev, rctx);
0857 }
0858 
0859 static int stm32_hash_one_request(struct crypto_engine *engine, void *areq)
0860 {
0861     struct ahash_request *req = container_of(areq, struct ahash_request,
0862                          base);
0863     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
0864     struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
0865     struct stm32_hash_request_ctx *rctx;
0866     int err = 0;
0867 
0868     if (!hdev)
0869         return -ENODEV;
0870 
0871     hdev->req = req;
0872 
0873     rctx = ahash_request_ctx(req);
0874 
0875     if (rctx->op == HASH_OP_UPDATE)
0876         err = stm32_hash_update_req(hdev);
0877     else if (rctx->op == HASH_OP_FINAL)
0878         err = stm32_hash_final_req(hdev);
0879 
0880     if (err != -EINPROGRESS)
0881     /* done task will not finish it, so do it here */
0882         stm32_hash_finish_req(req, err);
0883 
0884     return 0;
0885 }
0886 
0887 static int stm32_hash_enqueue(struct ahash_request *req, unsigned int op)
0888 {
0889     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0890     struct stm32_hash_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
0891     struct stm32_hash_dev *hdev = ctx->hdev;
0892 
0893     rctx->op = op;
0894 
0895     return stm32_hash_handle_queue(hdev, req);
0896 }
0897 
0898 static int stm32_hash_update(struct ahash_request *req)
0899 {
0900     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0901 
0902     if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU))
0903         return 0;
0904 
0905     rctx->total = req->nbytes;
0906     rctx->sg = req->src;
0907     rctx->offset = 0;
0908 
0909     if ((rctx->bufcnt + rctx->total < rctx->buflen)) {
0910         stm32_hash_append_sg(rctx);
0911         return 0;
0912     }
0913 
0914     return stm32_hash_enqueue(req, HASH_OP_UPDATE);
0915 }
0916 
0917 static int stm32_hash_final(struct ahash_request *req)
0918 {
0919     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0920 
0921     rctx->flags |= HASH_FLAGS_FINUP;
0922 
0923     return stm32_hash_enqueue(req, HASH_OP_FINAL);
0924 }
0925 
0926 static int stm32_hash_finup(struct ahash_request *req)
0927 {
0928     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0929     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
0930     struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
0931     int err1, err2;
0932 
0933     rctx->flags |= HASH_FLAGS_FINUP;
0934 
0935     if (hdev->dma_lch && stm32_hash_dma_aligned_data(req))
0936         rctx->flags &= ~HASH_FLAGS_CPU;
0937 
0938     err1 = stm32_hash_update(req);
0939 
0940     if (err1 == -EINPROGRESS || err1 == -EBUSY)
0941         return err1;
0942 
0943     /*
0944      * final() has to be always called to cleanup resources
0945      * even if update() failed, except EINPROGRESS
0946      */
0947     err2 = stm32_hash_final(req);
0948 
0949     return err1 ?: err2;
0950 }
0951 
0952 static int stm32_hash_digest(struct ahash_request *req)
0953 {
0954     return stm32_hash_init(req) ?: stm32_hash_finup(req);
0955 }
0956 
0957 static int stm32_hash_export(struct ahash_request *req, void *out)
0958 {
0959     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0960     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
0961     struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
0962     u32 *preg;
0963     unsigned int i;
0964 
0965     pm_runtime_get_sync(hdev->dev);
0966 
0967     while ((stm32_hash_read(hdev, HASH_SR) & HASH_SR_BUSY))
0968         cpu_relax();
0969 
0970     rctx->hw_context = kmalloc_array(3 + HASH_CSR_REGISTER_NUMBER,
0971                      sizeof(u32),
0972                      GFP_KERNEL);
0973 
0974     preg = rctx->hw_context;
0975 
0976     *preg++ = stm32_hash_read(hdev, HASH_IMR);
0977     *preg++ = stm32_hash_read(hdev, HASH_STR);
0978     *preg++ = stm32_hash_read(hdev, HASH_CR);
0979     for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
0980         *preg++ = stm32_hash_read(hdev, HASH_CSR(i));
0981 
0982     pm_runtime_mark_last_busy(hdev->dev);
0983     pm_runtime_put_autosuspend(hdev->dev);
0984 
0985     memcpy(out, rctx, sizeof(*rctx));
0986 
0987     return 0;
0988 }
0989 
0990 static int stm32_hash_import(struct ahash_request *req, const void *in)
0991 {
0992     struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
0993     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
0994     struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
0995     const u32 *preg = in;
0996     u32 reg;
0997     unsigned int i;
0998 
0999     memcpy(rctx, in, sizeof(*rctx));
1000 
1001     preg = rctx->hw_context;
1002 
1003     pm_runtime_get_sync(hdev->dev);
1004 
1005     stm32_hash_write(hdev, HASH_IMR, *preg++);
1006     stm32_hash_write(hdev, HASH_STR, *preg++);
1007     stm32_hash_write(hdev, HASH_CR, *preg);
1008     reg = *preg++ | HASH_CR_INIT;
1009     stm32_hash_write(hdev, HASH_CR, reg);
1010 
1011     for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
1012         stm32_hash_write(hdev, HASH_CSR(i), *preg++);
1013 
1014     pm_runtime_mark_last_busy(hdev->dev);
1015     pm_runtime_put_autosuspend(hdev->dev);
1016 
1017     kfree(rctx->hw_context);
1018 
1019     return 0;
1020 }
1021 
1022 static int stm32_hash_setkey(struct crypto_ahash *tfm,
1023                  const u8 *key, unsigned int keylen)
1024 {
1025     struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
1026 
1027     if (keylen <= HASH_MAX_KEY_SIZE) {
1028         memcpy(ctx->key, key, keylen);
1029         ctx->keylen = keylen;
1030     } else {
1031         return -ENOMEM;
1032     }
1033 
1034     return 0;
1035 }
1036 
1037 static int stm32_hash_cra_init_algs(struct crypto_tfm *tfm,
1038                     const char *algs_hmac_name)
1039 {
1040     struct stm32_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1041 
1042     crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1043                  sizeof(struct stm32_hash_request_ctx));
1044 
1045     ctx->keylen = 0;
1046 
1047     if (algs_hmac_name)
1048         ctx->flags |= HASH_FLAGS_HMAC;
1049 
1050     ctx->enginectx.op.do_one_request = stm32_hash_one_request;
1051     ctx->enginectx.op.prepare_request = stm32_hash_prepare_req;
1052     ctx->enginectx.op.unprepare_request = NULL;
1053     return 0;
1054 }
1055 
1056 static int stm32_hash_cra_init(struct crypto_tfm *tfm)
1057 {
1058     return stm32_hash_cra_init_algs(tfm, NULL);
1059 }
1060 
1061 static int stm32_hash_cra_md5_init(struct crypto_tfm *tfm)
1062 {
1063     return stm32_hash_cra_init_algs(tfm, "md5");
1064 }
1065 
1066 static int stm32_hash_cra_sha1_init(struct crypto_tfm *tfm)
1067 {
1068     return stm32_hash_cra_init_algs(tfm, "sha1");
1069 }
1070 
1071 static int stm32_hash_cra_sha224_init(struct crypto_tfm *tfm)
1072 {
1073     return stm32_hash_cra_init_algs(tfm, "sha224");
1074 }
1075 
1076 static int stm32_hash_cra_sha256_init(struct crypto_tfm *tfm)
1077 {
1078     return stm32_hash_cra_init_algs(tfm, "sha256");
1079 }
1080 
1081 static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
1082 {
1083     struct stm32_hash_dev *hdev = dev_id;
1084 
1085     if (HASH_FLAGS_CPU & hdev->flags) {
1086         if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
1087             hdev->flags &= ~HASH_FLAGS_OUTPUT_READY;
1088             goto finish;
1089         }
1090     } else if (HASH_FLAGS_DMA_READY & hdev->flags) {
1091         if (HASH_FLAGS_DMA_ACTIVE & hdev->flags) {
1092             hdev->flags &= ~HASH_FLAGS_DMA_ACTIVE;
1093                 goto finish;
1094         }
1095     }
1096 
1097     return IRQ_HANDLED;
1098 
1099 finish:
1100     /* Finish current request */
1101     stm32_hash_finish_req(hdev->req, 0);
1102 
1103     return IRQ_HANDLED;
1104 }
1105 
1106 static irqreturn_t stm32_hash_irq_handler(int irq, void *dev_id)
1107 {
1108     struct stm32_hash_dev *hdev = dev_id;
1109     u32 reg;
1110 
1111     reg = stm32_hash_read(hdev, HASH_SR);
1112     if (reg & HASH_SR_OUTPUT_READY) {
1113         reg &= ~HASH_SR_OUTPUT_READY;
1114         stm32_hash_write(hdev, HASH_SR, reg);
1115         hdev->flags |= HASH_FLAGS_OUTPUT_READY;
1116         /* Disable IT*/
1117         stm32_hash_write(hdev, HASH_IMR, 0);
1118         return IRQ_WAKE_THREAD;
1119     }
1120 
1121     return IRQ_NONE;
1122 }
1123 
1124 static struct ahash_alg algs_md5_sha1[] = {
1125     {
1126         .init = stm32_hash_init,
1127         .update = stm32_hash_update,
1128         .final = stm32_hash_final,
1129         .finup = stm32_hash_finup,
1130         .digest = stm32_hash_digest,
1131         .export = stm32_hash_export,
1132         .import = stm32_hash_import,
1133         .halg = {
1134             .digestsize = MD5_DIGEST_SIZE,
1135             .statesize = sizeof(struct stm32_hash_request_ctx),
1136             .base = {
1137                 .cra_name = "md5",
1138                 .cra_driver_name = "stm32-md5",
1139                 .cra_priority = 200,
1140                 .cra_flags = CRYPTO_ALG_ASYNC |
1141                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1142                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1143                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1144                 .cra_alignmask = 3,
1145                 .cra_init = stm32_hash_cra_init,
1146                 .cra_module = THIS_MODULE,
1147             }
1148         }
1149     },
1150     {
1151         .init = stm32_hash_init,
1152         .update = stm32_hash_update,
1153         .final = stm32_hash_final,
1154         .finup = stm32_hash_finup,
1155         .digest = stm32_hash_digest,
1156         .export = stm32_hash_export,
1157         .import = stm32_hash_import,
1158         .setkey = stm32_hash_setkey,
1159         .halg = {
1160             .digestsize = MD5_DIGEST_SIZE,
1161             .statesize = sizeof(struct stm32_hash_request_ctx),
1162             .base = {
1163                 .cra_name = "hmac(md5)",
1164                 .cra_driver_name = "stm32-hmac-md5",
1165                 .cra_priority = 200,
1166                 .cra_flags = CRYPTO_ALG_ASYNC |
1167                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1168                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1169                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1170                 .cra_alignmask = 3,
1171                 .cra_init = stm32_hash_cra_md5_init,
1172                 .cra_module = THIS_MODULE,
1173             }
1174         }
1175     },
1176     {
1177         .init = stm32_hash_init,
1178         .update = stm32_hash_update,
1179         .final = stm32_hash_final,
1180         .finup = stm32_hash_finup,
1181         .digest = stm32_hash_digest,
1182         .export = stm32_hash_export,
1183         .import = stm32_hash_import,
1184         .halg = {
1185             .digestsize = SHA1_DIGEST_SIZE,
1186             .statesize = sizeof(struct stm32_hash_request_ctx),
1187             .base = {
1188                 .cra_name = "sha1",
1189                 .cra_driver_name = "stm32-sha1",
1190                 .cra_priority = 200,
1191                 .cra_flags = CRYPTO_ALG_ASYNC |
1192                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1193                 .cra_blocksize = SHA1_BLOCK_SIZE,
1194                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1195                 .cra_alignmask = 3,
1196                 .cra_init = stm32_hash_cra_init,
1197                 .cra_module = THIS_MODULE,
1198             }
1199         }
1200     },
1201     {
1202         .init = stm32_hash_init,
1203         .update = stm32_hash_update,
1204         .final = stm32_hash_final,
1205         .finup = stm32_hash_finup,
1206         .digest = stm32_hash_digest,
1207         .export = stm32_hash_export,
1208         .import = stm32_hash_import,
1209         .setkey = stm32_hash_setkey,
1210         .halg = {
1211             .digestsize = SHA1_DIGEST_SIZE,
1212             .statesize = sizeof(struct stm32_hash_request_ctx),
1213             .base = {
1214                 .cra_name = "hmac(sha1)",
1215                 .cra_driver_name = "stm32-hmac-sha1",
1216                 .cra_priority = 200,
1217                 .cra_flags = CRYPTO_ALG_ASYNC |
1218                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1219                 .cra_blocksize = SHA1_BLOCK_SIZE,
1220                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1221                 .cra_alignmask = 3,
1222                 .cra_init = stm32_hash_cra_sha1_init,
1223                 .cra_module = THIS_MODULE,
1224             }
1225         }
1226     },
1227 };
1228 
1229 static struct ahash_alg algs_sha224_sha256[] = {
1230     {
1231         .init = stm32_hash_init,
1232         .update = stm32_hash_update,
1233         .final = stm32_hash_final,
1234         .finup = stm32_hash_finup,
1235         .digest = stm32_hash_digest,
1236         .export = stm32_hash_export,
1237         .import = stm32_hash_import,
1238         .halg = {
1239             .digestsize = SHA224_DIGEST_SIZE,
1240             .statesize = sizeof(struct stm32_hash_request_ctx),
1241             .base = {
1242                 .cra_name = "sha224",
1243                 .cra_driver_name = "stm32-sha224",
1244                 .cra_priority = 200,
1245                 .cra_flags = CRYPTO_ALG_ASYNC |
1246                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1247                 .cra_blocksize = SHA224_BLOCK_SIZE,
1248                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1249                 .cra_alignmask = 3,
1250                 .cra_init = stm32_hash_cra_init,
1251                 .cra_module = THIS_MODULE,
1252             }
1253         }
1254     },
1255     {
1256         .init = stm32_hash_init,
1257         .update = stm32_hash_update,
1258         .final = stm32_hash_final,
1259         .finup = stm32_hash_finup,
1260         .digest = stm32_hash_digest,
1261         .setkey = stm32_hash_setkey,
1262         .export = stm32_hash_export,
1263         .import = stm32_hash_import,
1264         .halg = {
1265             .digestsize = SHA224_DIGEST_SIZE,
1266             .statesize = sizeof(struct stm32_hash_request_ctx),
1267             .base = {
1268                 .cra_name = "hmac(sha224)",
1269                 .cra_driver_name = "stm32-hmac-sha224",
1270                 .cra_priority = 200,
1271                 .cra_flags = CRYPTO_ALG_ASYNC |
1272                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1273                 .cra_blocksize = SHA224_BLOCK_SIZE,
1274                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1275                 .cra_alignmask = 3,
1276                 .cra_init = stm32_hash_cra_sha224_init,
1277                 .cra_module = THIS_MODULE,
1278             }
1279         }
1280     },
1281     {
1282         .init = stm32_hash_init,
1283         .update = stm32_hash_update,
1284         .final = stm32_hash_final,
1285         .finup = stm32_hash_finup,
1286         .digest = stm32_hash_digest,
1287         .export = stm32_hash_export,
1288         .import = stm32_hash_import,
1289         .halg = {
1290             .digestsize = SHA256_DIGEST_SIZE,
1291             .statesize = sizeof(struct stm32_hash_request_ctx),
1292             .base = {
1293                 .cra_name = "sha256",
1294                 .cra_driver_name = "stm32-sha256",
1295                 .cra_priority = 200,
1296                 .cra_flags = CRYPTO_ALG_ASYNC |
1297                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1298                 .cra_blocksize = SHA256_BLOCK_SIZE,
1299                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1300                 .cra_alignmask = 3,
1301                 .cra_init = stm32_hash_cra_init,
1302                 .cra_module = THIS_MODULE,
1303             }
1304         }
1305     },
1306     {
1307         .init = stm32_hash_init,
1308         .update = stm32_hash_update,
1309         .final = stm32_hash_final,
1310         .finup = stm32_hash_finup,
1311         .digest = stm32_hash_digest,
1312         .export = stm32_hash_export,
1313         .import = stm32_hash_import,
1314         .setkey = stm32_hash_setkey,
1315         .halg = {
1316             .digestsize = SHA256_DIGEST_SIZE,
1317             .statesize = sizeof(struct stm32_hash_request_ctx),
1318             .base = {
1319                 .cra_name = "hmac(sha256)",
1320                 .cra_driver_name = "stm32-hmac-sha256",
1321                 .cra_priority = 200,
1322                 .cra_flags = CRYPTO_ALG_ASYNC |
1323                     CRYPTO_ALG_KERN_DRIVER_ONLY,
1324                 .cra_blocksize = SHA256_BLOCK_SIZE,
1325                 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1326                 .cra_alignmask = 3,
1327                 .cra_init = stm32_hash_cra_sha256_init,
1328                 .cra_module = THIS_MODULE,
1329             }
1330         }
1331     },
1332 };
1333 
1334 static int stm32_hash_register_algs(struct stm32_hash_dev *hdev)
1335 {
1336     unsigned int i, j;
1337     int err;
1338 
1339     for (i = 0; i < hdev->pdata->algs_info_size; i++) {
1340         for (j = 0; j < hdev->pdata->algs_info[i].size; j++) {
1341             err = crypto_register_ahash(
1342                 &hdev->pdata->algs_info[i].algs_list[j]);
1343             if (err)
1344                 goto err_algs;
1345         }
1346     }
1347 
1348     return 0;
1349 err_algs:
1350     dev_err(hdev->dev, "Algo %d : %d failed\n", i, j);
1351     for (; i--; ) {
1352         for (; j--;)
1353             crypto_unregister_ahash(
1354                 &hdev->pdata->algs_info[i].algs_list[j]);
1355     }
1356 
1357     return err;
1358 }
1359 
1360 static int stm32_hash_unregister_algs(struct stm32_hash_dev *hdev)
1361 {
1362     unsigned int i, j;
1363 
1364     for (i = 0; i < hdev->pdata->algs_info_size; i++) {
1365         for (j = 0; j < hdev->pdata->algs_info[i].size; j++)
1366             crypto_unregister_ahash(
1367                 &hdev->pdata->algs_info[i].algs_list[j]);
1368     }
1369 
1370     return 0;
1371 }
1372 
1373 static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f4[] = {
1374     {
1375         .algs_list  = algs_md5_sha1,
1376         .size       = ARRAY_SIZE(algs_md5_sha1),
1377     },
1378 };
1379 
1380 static const struct stm32_hash_pdata stm32_hash_pdata_stm32f4 = {
1381     .algs_info  = stm32_hash_algs_info_stm32f4,
1382     .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f4),
1383 };
1384 
1385 static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f7[] = {
1386     {
1387         .algs_list  = algs_md5_sha1,
1388         .size       = ARRAY_SIZE(algs_md5_sha1),
1389     },
1390     {
1391         .algs_list  = algs_sha224_sha256,
1392         .size       = ARRAY_SIZE(algs_sha224_sha256),
1393     },
1394 };
1395 
1396 static const struct stm32_hash_pdata stm32_hash_pdata_stm32f7 = {
1397     .algs_info  = stm32_hash_algs_info_stm32f7,
1398     .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f7),
1399 };
1400 
1401 static const struct of_device_id stm32_hash_of_match[] = {
1402     {
1403         .compatible = "st,stm32f456-hash",
1404         .data = &stm32_hash_pdata_stm32f4,
1405     },
1406     {
1407         .compatible = "st,stm32f756-hash",
1408         .data = &stm32_hash_pdata_stm32f7,
1409     },
1410     {},
1411 };
1412 
1413 MODULE_DEVICE_TABLE(of, stm32_hash_of_match);
1414 
1415 static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev,
1416                    struct device *dev)
1417 {
1418     hdev->pdata = of_device_get_match_data(dev);
1419     if (!hdev->pdata) {
1420         dev_err(dev, "no compatible OF match\n");
1421         return -EINVAL;
1422     }
1423 
1424     if (of_property_read_u32(dev->of_node, "dma-maxburst",
1425                  &hdev->dma_maxburst)) {
1426         dev_info(dev, "dma-maxburst not specified, using 0\n");
1427         hdev->dma_maxburst = 0;
1428     }
1429 
1430     return 0;
1431 }
1432 
1433 static int stm32_hash_probe(struct platform_device *pdev)
1434 {
1435     struct stm32_hash_dev *hdev;
1436     struct device *dev = &pdev->dev;
1437     struct resource *res;
1438     int ret, irq;
1439 
1440     hdev = devm_kzalloc(dev, sizeof(*hdev), GFP_KERNEL);
1441     if (!hdev)
1442         return -ENOMEM;
1443 
1444     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1445     hdev->io_base = devm_ioremap_resource(dev, res);
1446     if (IS_ERR(hdev->io_base))
1447         return PTR_ERR(hdev->io_base);
1448 
1449     hdev->phys_base = res->start;
1450 
1451     ret = stm32_hash_get_of_match(hdev, dev);
1452     if (ret)
1453         return ret;
1454 
1455     irq = platform_get_irq(pdev, 0);
1456     if (irq < 0)
1457         return irq;
1458 
1459     ret = devm_request_threaded_irq(dev, irq, stm32_hash_irq_handler,
1460                     stm32_hash_irq_thread, IRQF_ONESHOT,
1461                     dev_name(dev), hdev);
1462     if (ret) {
1463         dev_err(dev, "Cannot grab IRQ\n");
1464         return ret;
1465     }
1466 
1467     hdev->clk = devm_clk_get(&pdev->dev, NULL);
1468     if (IS_ERR(hdev->clk))
1469         return dev_err_probe(dev, PTR_ERR(hdev->clk),
1470                      "failed to get clock for hash\n");
1471 
1472     ret = clk_prepare_enable(hdev->clk);
1473     if (ret) {
1474         dev_err(dev, "failed to enable hash clock (%d)\n", ret);
1475         return ret;
1476     }
1477 
1478     pm_runtime_set_autosuspend_delay(dev, HASH_AUTOSUSPEND_DELAY);
1479     pm_runtime_use_autosuspend(dev);
1480 
1481     pm_runtime_get_noresume(dev);
1482     pm_runtime_set_active(dev);
1483     pm_runtime_enable(dev);
1484 
1485     hdev->rst = devm_reset_control_get(&pdev->dev, NULL);
1486     if (IS_ERR(hdev->rst)) {
1487         if (PTR_ERR(hdev->rst) == -EPROBE_DEFER) {
1488             ret = -EPROBE_DEFER;
1489             goto err_reset;
1490         }
1491     } else {
1492         reset_control_assert(hdev->rst);
1493         udelay(2);
1494         reset_control_deassert(hdev->rst);
1495     }
1496 
1497     hdev->dev = dev;
1498 
1499     platform_set_drvdata(pdev, hdev);
1500 
1501     ret = stm32_hash_dma_init(hdev);
1502     switch (ret) {
1503     case 0:
1504         break;
1505     case -ENOENT:
1506         dev_dbg(dev, "DMA mode not available\n");
1507         break;
1508     default:
1509         goto err_dma;
1510     }
1511 
1512     spin_lock(&stm32_hash.lock);
1513     list_add_tail(&hdev->list, &stm32_hash.dev_list);
1514     spin_unlock(&stm32_hash.lock);
1515 
1516     /* Initialize crypto engine */
1517     hdev->engine = crypto_engine_alloc_init(dev, 1);
1518     if (!hdev->engine) {
1519         ret = -ENOMEM;
1520         goto err_engine;
1521     }
1522 
1523     ret = crypto_engine_start(hdev->engine);
1524     if (ret)
1525         goto err_engine_start;
1526 
1527     hdev->dma_mode = stm32_hash_read(hdev, HASH_HWCFGR);
1528 
1529     /* Register algos */
1530     ret = stm32_hash_register_algs(hdev);
1531     if (ret)
1532         goto err_algs;
1533 
1534     dev_info(dev, "Init HASH done HW ver %x DMA mode %u\n",
1535          stm32_hash_read(hdev, HASH_VER), hdev->dma_mode);
1536 
1537     pm_runtime_put_sync(dev);
1538 
1539     return 0;
1540 
1541 err_algs:
1542 err_engine_start:
1543     crypto_engine_exit(hdev->engine);
1544 err_engine:
1545     spin_lock(&stm32_hash.lock);
1546     list_del(&hdev->list);
1547     spin_unlock(&stm32_hash.lock);
1548 err_dma:
1549     if (hdev->dma_lch)
1550         dma_release_channel(hdev->dma_lch);
1551 err_reset:
1552     pm_runtime_disable(dev);
1553     pm_runtime_put_noidle(dev);
1554 
1555     clk_disable_unprepare(hdev->clk);
1556 
1557     return ret;
1558 }
1559 
1560 static int stm32_hash_remove(struct platform_device *pdev)
1561 {
1562     struct stm32_hash_dev *hdev;
1563     int ret;
1564 
1565     hdev = platform_get_drvdata(pdev);
1566     if (!hdev)
1567         return -ENODEV;
1568 
1569     ret = pm_runtime_resume_and_get(hdev->dev);
1570     if (ret < 0)
1571         return ret;
1572 
1573     stm32_hash_unregister_algs(hdev);
1574 
1575     crypto_engine_exit(hdev->engine);
1576 
1577     spin_lock(&stm32_hash.lock);
1578     list_del(&hdev->list);
1579     spin_unlock(&stm32_hash.lock);
1580 
1581     if (hdev->dma_lch)
1582         dma_release_channel(hdev->dma_lch);
1583 
1584     pm_runtime_disable(hdev->dev);
1585     pm_runtime_put_noidle(hdev->dev);
1586 
1587     clk_disable_unprepare(hdev->clk);
1588 
1589     return 0;
1590 }
1591 
1592 #ifdef CONFIG_PM
1593 static int stm32_hash_runtime_suspend(struct device *dev)
1594 {
1595     struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
1596 
1597     clk_disable_unprepare(hdev->clk);
1598 
1599     return 0;
1600 }
1601 
1602 static int stm32_hash_runtime_resume(struct device *dev)
1603 {
1604     struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
1605     int ret;
1606 
1607     ret = clk_prepare_enable(hdev->clk);
1608     if (ret) {
1609         dev_err(hdev->dev, "Failed to prepare_enable clock\n");
1610         return ret;
1611     }
1612 
1613     return 0;
1614 }
1615 #endif
1616 
1617 static const struct dev_pm_ops stm32_hash_pm_ops = {
1618     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1619                 pm_runtime_force_resume)
1620     SET_RUNTIME_PM_OPS(stm32_hash_runtime_suspend,
1621                stm32_hash_runtime_resume, NULL)
1622 };
1623 
1624 static struct platform_driver stm32_hash_driver = {
1625     .probe      = stm32_hash_probe,
1626     .remove     = stm32_hash_remove,
1627     .driver     = {
1628         .name   = "stm32-hash",
1629         .pm = &stm32_hash_pm_ops,
1630         .of_match_table = stm32_hash_of_match,
1631     }
1632 };
1633 
1634 module_platform_driver(stm32_hash_driver);
1635 
1636 MODULE_DESCRIPTION("STM32 SHA1/224/256 & MD5 (HMAC) hw accelerator driver");
1637 MODULE_AUTHOR("Lionel Debieve <lionel.debieve@st.com>");
1638 MODULE_LICENSE("GPL v2");
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