crypto/stm32/stm32-crc32.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) STMicroelectronics SA 2017
0004  * Author: Fabien Dessenne <fabien.dessenne@st.com>
0005  */
0006
0007 #include <linux/bitrev.h>
0008 #include <linux/clk.h>
0009 #include <linux/crc32.h>
0010 #include <linux/crc32poly.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/mod_devicetable.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017
0018 #include <crypto/internal/hash.h>
0019
0020 #include <asm/unaligned.h>
0021
0022 #define DRIVER_NAME             "stm32-crc32"
0023 #define CHKSUM_DIGEST_SIZE      4
0024 #define CHKSUM_BLOCK_SIZE       1
0025
0026 /* Registers */
0027 #define CRC_DR                  0x00000000
0028 #define CRC_CR                  0x00000008
0029 #define CRC_INIT                0x00000010
0030 #define CRC_POL                 0x00000014
0031
0032 /* Registers values */
0033 #define CRC_CR_RESET            BIT(0)
0034 #define CRC_CR_REV_IN_WORD      (BIT(6) | BIT(5))
0035 #define CRC_CR_REV_IN_BYTE      BIT(5)
0036 #define CRC_CR_REV_OUT          BIT(7)
0037 #define CRC32C_INIT_DEFAULT     0xFFFFFFFF
0038
0039 #define CRC_AUTOSUSPEND_DELAY   50
0040
0041 static unsigned int burst_size;
0042 module_param(burst_size, uint, 0644);
0043 MODULE_PARM_DESC(burst_size, "Select burst byte size (0 unlimited)");
0044
0045 struct stm32_crc {
0046     struct list_head list;
0047     struct device    *dev;
0048     void __iomem     *regs;
0049     struct clk       *clk;
0050     spinlock_t       lock;
0051 };
0052
0053 struct stm32_crc_list {
0054     struct list_head dev_list;
0055     spinlock_t       lock; /* protect dev_list */
0056 };
0057
0058 static struct stm32_crc_list crc_list = {
0059     .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
0060     .lock     = __SPIN_LOCK_UNLOCKED(crc_list.lock),
0061 };
0062
0063 struct stm32_crc_ctx {
0064     u32 key;
0065     u32 poly;
0066 };
0067
0068 struct stm32_crc_desc_ctx {
0069     u32    partial; /* crc32c: partial in first 4 bytes of that struct */
0070 };
0071
0072 static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
0073 {
0074     struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
0075
0076     mctx->key = 0;
0077     mctx->poly = CRC32_POLY_LE;
0078     return 0;
0079 }
0080
0081 static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
0082 {
0083     struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
0084
0085     mctx->key = CRC32C_INIT_DEFAULT;
0086     mctx->poly = CRC32C_POLY_LE;
0087     return 0;
0088 }
0089
0090 static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
0091                 unsigned int keylen)
0092 {
0093     struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
0094
0095     if (keylen != sizeof(u32))
0096         return -EINVAL;
0097
0098     mctx->key = get_unaligned_le32(key);
0099     return 0;
0100 }
0101
0102 static struct stm32_crc *stm32_crc_get_next_crc(void)
0103 {
0104     struct stm32_crc *crc;
0105
0106     spin_lock_bh(&crc_list.lock);
0107     crc = list_first_entry(&crc_list.dev_list, struct stm32_crc, list);
0108     if (crc)
0109         list_move_tail(&crc->list, &crc_list.dev_list);
0110     spin_unlock_bh(&crc_list.lock);
0111
0112     return crc;
0113 }
0114
0115 static int stm32_crc_init(struct shash_desc *desc)
0116 {
0117     struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
0118     struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
0119     struct stm32_crc *crc;
0120     unsigned long flags;
0121
0122     crc = stm32_crc_get_next_crc();
0123     if (!crc)
0124         return -ENODEV;
0125
0126     pm_runtime_get_sync(crc->dev);
0127
0128     spin_lock_irqsave(&crc->lock, flags);
0129
0130     /* Reset, set key, poly and configure in bit reverse mode */
0131     writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
0132     writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
0133     writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
0134                crc->regs + CRC_CR);
0135
0136     /* Store partial result */
0137     ctx->partial = readl_relaxed(crc->regs + CRC_DR);
0138
0139     spin_unlock_irqrestore(&crc->lock, flags);
0140
0141     pm_runtime_mark_last_busy(crc->dev);
0142     pm_runtime_put_autosuspend(crc->dev);
0143
0144     return 0;
0145 }
0146
0147 static int burst_update(struct shash_desc *desc, const u8 *d8,
0148             size_t length)
0149 {
0150     struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
0151     struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
0152     struct stm32_crc *crc;
0153
0154     crc = stm32_crc_get_next_crc();
0155     if (!crc)
0156         return -ENODEV;
0157
0158     pm_runtime_get_sync(crc->dev);
0159
0160     if (!spin_trylock(&crc->lock)) {
0161         /* Hardware is busy, calculate crc32 by software */
0162         if (mctx->poly == CRC32_POLY_LE)
0163             ctx->partial = crc32_le(ctx->partial, d8, length);
0164         else
0165             ctx->partial = __crc32c_le(ctx->partial, d8, length);
0166
0167         goto pm_out;
0168     }
0169
0170     /*
0171      * Restore previously calculated CRC for this context as init value
0172      * Restore polynomial configuration
0173      * Configure in register for word input data,
0174      * Configure out register in reversed bit mode data.
0175      */
0176     writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
0177     writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
0178     writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
0179                crc->regs + CRC_CR);
0180
0181     if (d8 != PTR_ALIGN(d8, sizeof(u32))) {
0182         /* Configure for byte data */
0183         writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
0184                    crc->regs + CRC_CR);
0185         while (d8 != PTR_ALIGN(d8, sizeof(u32)) && length) {
0186             writeb_relaxed(*d8++, crc->regs + CRC_DR);
0187             length--;
0188         }
0189         /* Configure for word data */
0190         writel_relaxed(CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
0191                    crc->regs + CRC_CR);
0192     }
0193
0194     for (; length >= sizeof(u32); d8 += sizeof(u32), length -= sizeof(u32))
0195         writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
0196
0197     if (length) {
0198         /* Configure for byte data */
0199         writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
0200                    crc->regs + CRC_CR);
0201         while (length--)
0202             writeb_relaxed(*d8++, crc->regs + CRC_DR);
0203     }
0204
0205     /* Store partial result */
0206     ctx->partial = readl_relaxed(crc->regs + CRC_DR);
0207
0208     spin_unlock(&crc->lock);
0209
0210 pm_out:
0211     pm_runtime_mark_last_busy(crc->dev);
0212     pm_runtime_put_autosuspend(crc->dev);
0213
0214     return 0;
0215 }
0216
0217 static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
0218                 unsigned int length)
0219 {
0220     const unsigned int burst_sz = burst_size;
0221     unsigned int rem_sz;
0222     const u8 *cur;
0223     size_t size;
0224     int ret;
0225
0226     if (!burst_sz)
0227         return burst_update(desc, d8, length);
0228
0229     /* Digest first bytes not 32bit aligned at first pass in the loop */
0230     size = min_t(size_t, length, burst_sz + (size_t)d8 -
0231                      ALIGN_DOWN((size_t)d8, sizeof(u32)));
0232     for (rem_sz = length, cur = d8; rem_sz;
0233          rem_sz -= size, cur += size, size = min(rem_sz, burst_sz)) {
0234         ret = burst_update(desc, cur, size);
0235         if (ret)
0236             return ret;
0237     }
0238
0239     return 0;
0240 }
0241
0242 static int stm32_crc_final(struct shash_desc *desc, u8 *out)
0243 {
0244     struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
0245     struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
0246
0247     /* Send computed CRC */
0248     put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
0249                ~ctx->partial : ctx->partial, out);
0250
0251     return 0;
0252 }
0253
0254 static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
0255                unsigned int length, u8 *out)
0256 {
0257     return stm32_crc_update(desc, data, length) ?:
0258            stm32_crc_final(desc, out);
0259 }
0260
0261 static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
0262                 unsigned int length, u8 *out)
0263 {
0264     return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
0265 }
0266
0267 static unsigned int refcnt;
0268 static DEFINE_MUTEX(refcnt_lock);
0269 static struct shash_alg algs[] = {
0270     /* CRC-32 */
0271     {
0272         .setkey         = stm32_crc_setkey,
0273         .init           = stm32_crc_init,
0274         .update         = stm32_crc_update,
0275         .final          = stm32_crc_final,
0276         .finup          = stm32_crc_finup,
0277         .digest         = stm32_crc_digest,
0278         .descsize       = sizeof(struct stm32_crc_desc_ctx),
0279         .digestsize     = CHKSUM_DIGEST_SIZE,
0280         .base           = {
0281             .cra_name               = "crc32",
0282             .cra_driver_name        = "stm32-crc32-crc32",
0283             .cra_priority           = 200,
0284             .cra_flags      = CRYPTO_ALG_OPTIONAL_KEY,
0285             .cra_blocksize          = CHKSUM_BLOCK_SIZE,
0286             .cra_alignmask          = 3,
0287             .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
0288             .cra_module             = THIS_MODULE,
0289             .cra_init               = stm32_crc32_cra_init,
0290         }
0291     },
0292     /* CRC-32Castagnoli */
0293     {
0294         .setkey         = stm32_crc_setkey,
0295         .init           = stm32_crc_init,
0296         .update         = stm32_crc_update,
0297         .final          = stm32_crc_final,
0298         .finup          = stm32_crc_finup,
0299         .digest         = stm32_crc_digest,
0300         .descsize       = sizeof(struct stm32_crc_desc_ctx),
0301         .digestsize     = CHKSUM_DIGEST_SIZE,
0302         .base           = {
0303             .cra_name               = "crc32c",
0304             .cra_driver_name        = "stm32-crc32-crc32c",
0305             .cra_priority           = 200,
0306             .cra_flags      = CRYPTO_ALG_OPTIONAL_KEY,
0307             .cra_blocksize          = CHKSUM_BLOCK_SIZE,
0308             .cra_alignmask          = 3,
0309             .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
0310             .cra_module             = THIS_MODULE,
0311             .cra_init               = stm32_crc32c_cra_init,
0312         }
0313     }
0314 };
0315
0316 static int stm32_crc_probe(struct platform_device *pdev)
0317 {
0318     struct device *dev = &pdev->dev;
0319     struct stm32_crc *crc;
0320     int ret;
0321
0322     crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
0323     if (!crc)
0324         return -ENOMEM;
0325
0326     crc->dev = dev;
0327
0328     crc->regs = devm_platform_ioremap_resource(pdev, 0);
0329     if (IS_ERR(crc->regs)) {
0330         dev_err(dev, "Cannot map CRC IO\n");
0331         return PTR_ERR(crc->regs);
0332     }
0333
0334     crc->clk = devm_clk_get(dev, NULL);
0335     if (IS_ERR(crc->clk)) {
0336         dev_err(dev, "Could not get clock\n");
0337         return PTR_ERR(crc->clk);
0338     }
0339
0340     ret = clk_prepare_enable(crc->clk);
0341     if (ret) {
0342         dev_err(crc->dev, "Failed to enable clock\n");
0343         return ret;
0344     }
0345
0346     pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
0347     pm_runtime_use_autosuspend(dev);
0348
0349     pm_runtime_get_noresume(dev);
0350     pm_runtime_set_active(dev);
0351     pm_runtime_irq_safe(dev);
0352     pm_runtime_enable(dev);
0353
0354     spin_lock_init(&crc->lock);
0355
0356     platform_set_drvdata(pdev, crc);
0357
0358     spin_lock(&crc_list.lock);
0359     list_add(&crc->list, &crc_list.dev_list);
0360     spin_unlock(&crc_list.lock);
0361
0362     mutex_lock(&refcnt_lock);
0363     if (!refcnt) {
0364         ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
0365         if (ret) {
0366             mutex_unlock(&refcnt_lock);
0367             dev_err(dev, "Failed to register\n");
0368             clk_disable_unprepare(crc->clk);
0369             return ret;
0370         }
0371     }
0372     refcnt++;
0373     mutex_unlock(&refcnt_lock);
0374
0375     dev_info(dev, "Initialized\n");
0376
0377     pm_runtime_put_sync(dev);
0378
0379     return 0;
0380 }
0381
0382 static int stm32_crc_remove(struct platform_device *pdev)
0383 {
0384     struct stm32_crc *crc = platform_get_drvdata(pdev);
0385     int ret = pm_runtime_get_sync(crc->dev);
0386
0387     if (ret < 0) {
0388         pm_runtime_put_noidle(crc->dev);
0389         return ret;
0390     }
0391
0392     spin_lock(&crc_list.lock);
0393     list_del(&crc->list);
0394     spin_unlock(&crc_list.lock);
0395
0396     mutex_lock(&refcnt_lock);
0397     if (!--refcnt)
0398         crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
0399     mutex_unlock(&refcnt_lock);
0400
0401     pm_runtime_disable(crc->dev);
0402     pm_runtime_put_noidle(crc->dev);
0403
0404     clk_disable_unprepare(crc->clk);
0405
0406     return 0;
0407 }
0408
0409 static int __maybe_unused stm32_crc_suspend(struct device *dev)
0410 {
0411     struct stm32_crc *crc = dev_get_drvdata(dev);
0412     int ret;
0413
0414     ret = pm_runtime_force_suspend(dev);
0415     if (ret)
0416         return ret;
0417
0418     clk_unprepare(crc->clk);
0419
0420     return 0;
0421 }
0422
0423 static int __maybe_unused stm32_crc_resume(struct device *dev)
0424 {
0425     struct stm32_crc *crc = dev_get_drvdata(dev);
0426     int ret;
0427
0428     ret = clk_prepare(crc->clk);
0429     if (ret) {
0430         dev_err(crc->dev, "Failed to prepare clock\n");
0431         return ret;
0432     }
0433
0434     return pm_runtime_force_resume(dev);
0435 }
0436
0437 static int __maybe_unused stm32_crc_runtime_suspend(struct device *dev)
0438 {
0439     struct stm32_crc *crc = dev_get_drvdata(dev);
0440
0441     clk_disable(crc->clk);
0442
0443     return 0;
0444 }
0445
0446 static int __maybe_unused stm32_crc_runtime_resume(struct device *dev)
0447 {
0448     struct stm32_crc *crc = dev_get_drvdata(dev);
0449     int ret;
0450
0451     ret = clk_enable(crc->clk);
0452     if (ret) {
0453         dev_err(crc->dev, "Failed to enable clock\n");
0454         return ret;
0455     }
0456
0457     return 0;
0458 }
0459
0460 static const struct dev_pm_ops stm32_crc_pm_ops = {
0461     SET_SYSTEM_SLEEP_PM_OPS(stm32_crc_suspend,
0462                 stm32_crc_resume)
0463     SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
0464                stm32_crc_runtime_resume, NULL)
0465 };
0466
0467 static const struct of_device_id stm32_dt_ids[] = {
0468     { .compatible = "st,stm32f7-crc", },
0469     {},
0470 };
0471 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
0472
0473 static struct platform_driver stm32_crc_driver = {
0474     .probe  = stm32_crc_probe,
0475     .remove = stm32_crc_remove,
0476     .driver = {
0477         .name           = DRIVER_NAME,
0478         .pm     = &stm32_crc_pm_ops,
0479         .of_match_table = stm32_dt_ids,
0480     },
0481 };
0482
0483 module_platform_driver(stm32_crc_driver);
0484
0485 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
0486 MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
0487 MODULE_LICENSE("GPL");