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0012 #ifndef _K3_SA2UL_
0013 #define _K3_SA2UL_
0014
0015 #include <crypto/aes.h>
0016 #include <crypto/sha1.h>
0017 #include <crypto/sha2.h>
0018
0019 #define SA_ENGINE_STATUS 0x0008
0020 #define SA_ENGINE_ENABLE_CONTROL 0x1000
0021
0022 struct sa_tfm_ctx;
0023
0024
0025
0026 #define SA_EEC_ENCSS_EN 0x00000001
0027 #define SA_EEC_AUTHSS_EN 0x00000002
0028 #define SA_EEC_TRNG_EN 0x00000008
0029 #define SA_EEC_PKA_EN 0x00000010
0030 #define SA_EEC_CTXCACH_EN 0x00000080
0031 #define SA_EEC_CPPI_PORT_IN_EN 0x00000200
0032 #define SA_EEC_CPPI_PORT_OUT_EN 0x00000800
0033
0034
0035
0036
0037
0038
0039 #define SA_REQ_SUBTYPE_ENC 0x0001
0040 #define SA_REQ_SUBTYPE_DEC 0x0002
0041 #define SA_REQ_SUBTYPE_SHIFT 16
0042 #define SA_REQ_SUBTYPE_MASK 0xffff
0043
0044
0045 #define SA_DMA_NUM_EPIB_WORDS 4
0046
0047
0048 #define SA_DMA_NUM_PS_WORDS 16
0049 #define NKEY_SZ 3
0050 #define MCI_SZ 27
0051
0052
0053
0054
0055
0056 #define SA_MAX_NUM_CTX 512
0057
0058
0059
0060
0061 #define SA_CTX_SIZE_TO_DMA_SIZE(ctx_sz) \
0062 ((ctx_sz) ? ((ctx_sz) / 32 - 1) : 0)
0063
0064 #define SA_CTX_ENC_KEY_OFFSET 32
0065 #define SA_CTX_ENC_AUX1_OFFSET 64
0066 #define SA_CTX_ENC_AUX2_OFFSET 96
0067 #define SA_CTX_ENC_AUX3_OFFSET 112
0068 #define SA_CTX_ENC_AUX4_OFFSET 128
0069
0070
0071 #define SA_ENG_ID_EM1 2
0072 #define SA_ENG_ID_EM2 3
0073 #define SA_ENG_ID_AM1 4
0074 #define SA_ENG_ID_AM2 5
0075 #define SA_ENG_ID_OUTPORT2 20
0076
0077
0078
0079
0080 #define SA_CMDL_OFFSET_NESC 0
0081 #define SA_CMDL_OFFSET_LABEL_LEN 1
0082
0083 #define SA_CMDL_OFFSET_DATA_LEN 2
0084 #define SA_CMDL_OFFSET_DATA_OFFSET 4
0085 #define SA_CMDL_OFFSET_OPTION_CTRL1 5
0086 #define SA_CMDL_OFFSET_OPTION_CTRL2 6
0087 #define SA_CMDL_OFFSET_OPTION_CTRL3 7
0088 #define SA_CMDL_OFFSET_OPTION_BYTE 8
0089
0090 #define SA_CMDL_HEADER_SIZE_BYTES 8
0091
0092 #define SA_CMDL_OPTION_BYTES_MAX_SIZE 72
0093 #define SA_CMDL_MAX_SIZE_BYTES (SA_CMDL_HEADER_SIZE_BYTES + \
0094 SA_CMDL_OPTION_BYTES_MAX_SIZE)
0095
0096
0097 #define SA_SW_INFO_FLAG_EVICT 0x0001
0098 #define SA_SW_INFO_FLAG_TEAR 0x0002
0099 #define SA_SW_INFO_FLAG_NOPD 0x0004
0100
0101
0102
0103
0104
0105
0106 #define SA_CTX_PE_PKT_TYPE_3GPP_AIR 0
0107 #define SA_CTX_PE_PKT_TYPE_SRTP 1
0108 #define SA_CTX_PE_PKT_TYPE_IPSEC_AH 2
0109
0110 #define SA_CTX_PE_PKT_TYPE_IPSEC_ESP 3
0111
0112 #define SA_CTX_PE_PKT_TYPE_NONE 4
0113 #define SA_CTX_ENC_TYPE1_SZ 64
0114 #define SA_CTX_ENC_TYPE2_SZ 96
0115
0116 #define SA_CTX_AUTH_TYPE1_SZ 64
0117 #define SA_CTX_AUTH_TYPE2_SZ 96
0118
0119 #define SA_CTX_PHP_PE_CTX_SZ 64
0120
0121 #define SA_CTX_MAX_SZ (64 + SA_CTX_ENC_TYPE2_SZ + SA_CTX_AUTH_TYPE2_SZ)
0122
0123
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0133
0134
0135 #define SA_CTX_DMA_SIZE_0 0
0136 #define SA_CTX_DMA_SIZE_64 1
0137 #define SA_CTX_DMA_SIZE_96 2
0138 #define SA_CTX_DMA_SIZE_128 3
0139
0140
0141
0142
0143
0144 #define SA_CTX_SCCTL_OWNER_OFFSET 0
0145
0146 #define SA_CTX_ENC_KEY_OFFSET 32
0147 #define SA_CTX_ENC_AUX1_OFFSET 64
0148 #define SA_CTX_ENC_AUX2_OFFSET 96
0149 #define SA_CTX_ENC_AUX3_OFFSET 112
0150 #define SA_CTX_ENC_AUX4_OFFSET 128
0151
0152 #define SA_SCCTL_FE_AUTH_ENC 0x65
0153 #define SA_SCCTL_FE_ENC 0x8D
0154
0155 #define SA_ALIGN_MASK (sizeof(u32) - 1)
0156 #define SA_ALIGNED __aligned(32)
0157
0158 #define SA_AUTH_SW_CTRL_MD5 1
0159 #define SA_AUTH_SW_CTRL_SHA1 2
0160 #define SA_AUTH_SW_CTRL_SHA224 3
0161 #define SA_AUTH_SW_CTRL_SHA256 4
0162 #define SA_AUTH_SW_CTRL_SHA384 5
0163 #define SA_AUTH_SW_CTRL_SHA512 6
0164
0165
0166 #define SA_MAX_DATA_SZ U16_MAX
0167
0168
0169
0170
0171
0172 #define SA_UNSAFE_DATA_SZ_MIN 240
0173 #define SA_UNSAFE_DATA_SZ_MAX 256
0174
0175 struct sa_match_data;
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0194 struct sa_crypto_data {
0195 void __iomem *base;
0196 const struct sa_match_data *match_data;
0197 struct platform_device *pdev;
0198 struct dma_pool *sc_pool;
0199 struct device *dev;
0200 spinlock_t scid_lock;
0201
0202 u16 sc_id_start;
0203 u16 sc_id_end;
0204 u16 sc_id;
0205 unsigned long ctx_bm[DIV_ROUND_UP(SA_MAX_NUM_CTX,
0206 BITS_PER_LONG)];
0207 struct sa_tfm_ctx *ctx;
0208 struct dma_chan *dma_rx1;
0209 struct dma_chan *dma_rx2;
0210 struct dma_chan *dma_tx;
0211 };
0212
0213
0214
0215
0216
0217
0218
0219 struct sa_cmdl_param_info {
0220 u16 index;
0221 u16 offset;
0222 u16 size;
0223 };
0224
0225
0226 #define SA_MAX_AUX_DATA_WORDS 8
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0246 struct sa_cmdl_upd_info {
0247 u16 flags;
0248 u16 submode;
0249 struct sa_cmdl_param_info enc_size;
0250 struct sa_cmdl_param_info enc_size2;
0251 struct sa_cmdl_param_info enc_offset;
0252 struct sa_cmdl_param_info enc_iv;
0253 struct sa_cmdl_param_info enc_iv2;
0254 struct sa_cmdl_param_info aad;
0255 struct sa_cmdl_param_info payload;
0256 struct sa_cmdl_param_info auth_size;
0257 struct sa_cmdl_param_info auth_size2;
0258 struct sa_cmdl_param_info auth_offset;
0259 struct sa_cmdl_param_info auth_iv;
0260 struct sa_cmdl_param_info aux_key_info;
0261 u32 aux_key[SA_MAX_AUX_DATA_WORDS];
0262 };
0263
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0266
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0268
0269
0270 #define SA_PSDATA_CTX_WORDS 4
0271
0272
0273 #define SA_MAX_CMDL_WORDS (SA_DMA_NUM_PS_WORDS - SA_PSDATA_CTX_WORDS)
0274
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0285 struct sa_ctx_info {
0286 u8 *sc;
0287 dma_addr_t sc_phys;
0288 u16 sc_id;
0289 u16 cmdl_size;
0290 u32 cmdl[SA_MAX_CMDL_WORDS];
0291 struct sa_cmdl_upd_info cmdl_upd_info;
0292
0293 u32 epib[SA_DMA_NUM_EPIB_WORDS];
0294 };
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0305
0306 struct sa_tfm_ctx {
0307 struct sa_crypto_data *dev_data;
0308 struct sa_ctx_info enc;
0309 struct sa_ctx_info dec;
0310 struct sa_ctx_info auth;
0311 int keylen;
0312 int iv_idx;
0313 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
0314 u8 authkey[SHA512_BLOCK_SIZE];
0315 struct crypto_shash *shash;
0316
0317 union {
0318 struct crypto_skcipher *skcipher;
0319 struct crypto_ahash *ahash;
0320 struct crypto_aead *aead;
0321 } fallback;
0322 };
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0329
0330 struct sa_sha_req_ctx {
0331 struct sa_crypto_data *dev_data;
0332 u32 cmdl[SA_MAX_CMDL_WORDS + SA_PSDATA_CTX_WORDS];
0333 struct ahash_request fallback_req;
0334 };
0335
0336 enum sa_submode {
0337 SA_MODE_GEN = 0,
0338 SA_MODE_CCM,
0339 SA_MODE_GCM,
0340 SA_MODE_GMAC
0341 };
0342
0343
0344 enum sa_ealg_id {
0345 SA_EALG_ID_NONE = 0,
0346 SA_EALG_ID_NULL,
0347 SA_EALG_ID_AES_CTR,
0348 SA_EALG_ID_AES_F8,
0349 SA_EALG_ID_AES_CBC,
0350 SA_EALG_ID_DES_CBC,
0351 SA_EALG_ID_3DES_CBC,
0352 SA_EALG_ID_CCM,
0353 SA_EALG_ID_GCM,
0354 SA_EALG_ID_AES_ECB,
0355 SA_EALG_ID_LAST
0356 };
0357
0358
0359 enum sa_aalg_id {
0360 SA_AALG_ID_NONE = 0,
0361 SA_AALG_ID_NULL = SA_EALG_ID_LAST,
0362 SA_AALG_ID_MD5,
0363 SA_AALG_ID_SHA1,
0364 SA_AALG_ID_SHA2_224,
0365 SA_AALG_ID_SHA2_256,
0366 SA_AALG_ID_SHA2_512,
0367 SA_AALG_ID_HMAC_MD5,
0368 SA_AALG_ID_HMAC_SHA1,
0369 SA_AALG_ID_HMAC_SHA2_224,
0370 SA_AALG_ID_HMAC_SHA2_256,
0371 SA_AALG_ID_GMAC,
0372 SA_AALG_ID_CMAC,
0373 SA_AALG_ID_CBC_MAC,
0374 SA_AALG_ID_AES_XCBC
0375 };
0376
0377
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0379
0380
0381 enum sa_eng_algo_id {
0382 SA_ENG_ALGO_ECB = 0,
0383 SA_ENG_ALGO_CBC,
0384 SA_ENG_ALGO_CFB,
0385 SA_ENG_ALGO_OFB,
0386 SA_ENG_ALGO_CTR,
0387 SA_ENG_ALGO_F8,
0388 SA_ENG_ALGO_F8F9,
0389 SA_ENG_ALGO_GCM,
0390 SA_ENG_ALGO_GMAC,
0391 SA_ENG_ALGO_CCM,
0392 SA_ENG_ALGO_CMAC,
0393 SA_ENG_ALGO_CBCMAC,
0394 SA_NUM_ENG_ALGOS
0395 };
0396
0397
0398
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0400
0401
0402 struct sa_eng_info {
0403 u8 eng_id;
0404 u16 sc_size;
0405 };
0406
0407 #endif