drivers/crypto/qcom-rng.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2017-18 Linaro Limited
0003 //
0004 // Based on msm-rng.c and downstream driver
0005
0006 #include <crypto/internal/rng.h>
0007 #include <linux/acpi.h>
0008 #include <linux/clk.h>
0009 #include <linux/crypto.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015
0016 /* Device specific register offsets */
0017 #define PRNG_DATA_OUT       0x0000
0018 #define PRNG_STATUS     0x0004
0019 #define PRNG_LFSR_CFG       0x0100
0020 #define PRNG_CONFIG     0x0104
0021
0022 /* Device specific register masks and config values */
0023 #define PRNG_LFSR_CFG_MASK  0x0000ffff
0024 #define PRNG_LFSR_CFG_CLOCKS    0x0000dddd
0025 #define PRNG_CONFIG_HW_ENABLE   BIT(1)
0026 #define PRNG_STATUS_DATA_AVAIL  BIT(0)
0027
0028 #define WORD_SZ         4
0029
0030 struct qcom_rng {
0031     struct mutex lock;
0032     void __iomem *base;
0033     struct clk *clk;
0034     unsigned int skip_init;
0035 };
0036
0037 struct qcom_rng_ctx {
0038     struct qcom_rng *rng;
0039 };
0040
0041 static struct qcom_rng *qcom_rng_dev;
0042
0043 static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
0044 {
0045     unsigned int currsize = 0;
0046     u32 val;
0047     int ret;
0048
0049     /* read random data from hardware */
0050     do {
0051         ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
0052                      val & PRNG_STATUS_DATA_AVAIL,
0053                      200, 10000);
0054         if (ret)
0055             return ret;
0056
0057         val = readl_relaxed(rng->base + PRNG_DATA_OUT);
0058         if (!val)
0059             return -EINVAL;
0060
0061         if ((max - currsize) >= WORD_SZ) {
0062             memcpy(data, &val, WORD_SZ);
0063             data += WORD_SZ;
0064             currsize += WORD_SZ;
0065         } else {
0066             /* copy only remaining bytes */
0067             memcpy(data, &val, max - currsize);
0068             break;
0069         }
0070     } while (currsize < max);
0071
0072     return 0;
0073 }
0074
0075 static int qcom_rng_generate(struct crypto_rng *tfm,
0076                  const u8 *src, unsigned int slen,
0077                  u8 *dstn, unsigned int dlen)
0078 {
0079     struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
0080     struct qcom_rng *rng = ctx->rng;
0081     int ret;
0082
0083     ret = clk_prepare_enable(rng->clk);
0084     if (ret)
0085         return ret;
0086
0087     mutex_lock(&rng->lock);
0088
0089     ret = qcom_rng_read(rng, dstn, dlen);
0090
0091     mutex_unlock(&rng->lock);
0092     clk_disable_unprepare(rng->clk);
0093
0094     return ret;
0095 }
0096
0097 static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
0098              unsigned int slen)
0099 {
0100     return 0;
0101 }
0102
0103 static int qcom_rng_enable(struct qcom_rng *rng)
0104 {
0105     u32 val;
0106     int ret;
0107
0108     ret = clk_prepare_enable(rng->clk);
0109     if (ret)
0110         return ret;
0111
0112     /* Enable PRNG only if it is not already enabled */
0113     val = readl_relaxed(rng->base + PRNG_CONFIG);
0114     if (val & PRNG_CONFIG_HW_ENABLE)
0115         goto already_enabled;
0116
0117     val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
0118     val &= ~PRNG_LFSR_CFG_MASK;
0119     val |= PRNG_LFSR_CFG_CLOCKS;
0120     writel(val, rng->base + PRNG_LFSR_CFG);
0121
0122     val = readl_relaxed(rng->base + PRNG_CONFIG);
0123     val |= PRNG_CONFIG_HW_ENABLE;
0124     writel(val, rng->base + PRNG_CONFIG);
0125
0126 already_enabled:
0127     clk_disable_unprepare(rng->clk);
0128
0129     return 0;
0130 }
0131
0132 static int qcom_rng_init(struct crypto_tfm *tfm)
0133 {
0134     struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);
0135
0136     ctx->rng = qcom_rng_dev;
0137
0138     if (!ctx->rng->skip_init)
0139         return qcom_rng_enable(ctx->rng);
0140
0141     return 0;
0142 }
0143
0144 static struct rng_alg qcom_rng_alg = {
0145     .generate   = qcom_rng_generate,
0146     .seed       = qcom_rng_seed,
0147     .seedsize   = 0,
0148     .base       = {
0149         .cra_name       = "stdrng",
0150         .cra_driver_name    = "qcom-rng",
0151         .cra_flags      = CRYPTO_ALG_TYPE_RNG,
0152         .cra_priority       = 300,
0153         .cra_ctxsize        = sizeof(struct qcom_rng_ctx),
0154         .cra_module     = THIS_MODULE,
0155         .cra_init       = qcom_rng_init,
0156     }
0157 };
0158
0159 static int qcom_rng_probe(struct platform_device *pdev)
0160 {
0161     struct qcom_rng *rng;
0162     int ret;
0163
0164     rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
0165     if (!rng)
0166         return -ENOMEM;
0167
0168     platform_set_drvdata(pdev, rng);
0169     mutex_init(&rng->lock);
0170
0171     rng->base = devm_platform_ioremap_resource(pdev, 0);
0172     if (IS_ERR(rng->base))
0173         return PTR_ERR(rng->base);
0174
0175     /* ACPI systems have clk already on, so skip clk_get */
0176     if (!has_acpi_companion(&pdev->dev)) {
0177         rng->clk = devm_clk_get(&pdev->dev, "core");
0178         if (IS_ERR(rng->clk))
0179             return PTR_ERR(rng->clk);
0180     }
0181
0182
0183     rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev);
0184
0185     qcom_rng_dev = rng;
0186     ret = crypto_register_rng(&qcom_rng_alg);
0187     if (ret) {
0188         dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
0189         qcom_rng_dev = NULL;
0190     }
0191
0192     return ret;
0193 }
0194
0195 static int qcom_rng_remove(struct platform_device *pdev)
0196 {
0197     crypto_unregister_rng(&qcom_rng_alg);
0198
0199     qcom_rng_dev = NULL;
0200
0201     return 0;
0202 }
0203
0204 #if IS_ENABLED(CONFIG_ACPI)
0205 static const struct acpi_device_id qcom_rng_acpi_match[] = {
0206     { .id = "QCOM8160", .driver_data = 1 },
0207     {}
0208 };
0209 MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
0210 #endif
0211
0212 static const struct of_device_id qcom_rng_of_match[] = {
0213     { .compatible = "qcom,prng", .data = (void *)0},
0214     { .compatible = "qcom,prng-ee", .data = (void *)1},
0215     {}
0216 };
0217 MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
0218
0219 static struct platform_driver qcom_rng_driver = {
0220     .probe = qcom_rng_probe,
0221     .remove =  qcom_rng_remove,
0222     .driver = {
0223         .name = KBUILD_MODNAME,
0224         .of_match_table = of_match_ptr(qcom_rng_of_match),
0225         .acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
0226     }
0227 };
0228 module_platform_driver(qcom_rng_driver);
0229
0230 MODULE_ALIAS("platform:" KBUILD_MODNAME);
0231 MODULE_DESCRIPTION("Qualcomm random number generator driver");
0232 MODULE_LICENSE("GPL v2");