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0006 #ifndef _DMA_H_
0007 #define _DMA_H_
0008
0009 #include <linux/dmaengine.h>
0010
0011
0012 #define QCE_BAM_BURST_SIZE 64
0013
0014 #define QCE_AUTHIV_REGS_CNT 16
0015 #define QCE_AUTH_BYTECOUNT_REGS_CNT 4
0016 #define QCE_CNTRIV_REGS_CNT 4
0017
0018 struct qce_result_dump {
0019 u32 auth_iv[QCE_AUTHIV_REGS_CNT];
0020 u32 auth_byte_count[QCE_AUTH_BYTECOUNT_REGS_CNT];
0021 u32 encr_cntr_iv[QCE_CNTRIV_REGS_CNT];
0022 u32 status;
0023 u32 status2;
0024 };
0025
0026 #define QCE_IGNORE_BUF_SZ (2 * QCE_BAM_BURST_SIZE)
0027 #define QCE_RESULT_BUF_SZ \
0028 ALIGN(sizeof(struct qce_result_dump), QCE_BAM_BURST_SIZE)
0029
0030 struct qce_dma_data {
0031 struct dma_chan *txchan;
0032 struct dma_chan *rxchan;
0033 struct qce_result_dump *result_buf;
0034 void *ignore_buf;
0035 };
0036
0037 int qce_dma_request(struct device *dev, struct qce_dma_data *dma);
0038 void qce_dma_release(struct qce_dma_data *dma);
0039 int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in,
0040 int in_ents, struct scatterlist *sg_out, int out_ents,
0041 dma_async_tx_callback cb, void *cb_param);
0042 void qce_dma_issue_pending(struct qce_dma_data *dma);
0043 int qce_dma_terminate_all(struct qce_dma_data *dma);
0044 struct scatterlist *
0045 qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add,
0046 unsigned int max_len);
0047
0048 #endif