Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
0002 /* Copyright(c) 2020 Intel Corporation */
0003 #ifndef ADF_GEN2_HW_DATA_H_
0004 #define ADF_GEN2_HW_DATA_H_
0005 
0006 #include "adf_accel_devices.h"
0007 #include "adf_cfg_common.h"
0008 
0009 /* Transport access */
0010 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
0011 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
0012 #define ADF_RING_CSR_RING_CONFIG    0x000
0013 #define ADF_RING_CSR_RING_LBASE     0x040
0014 #define ADF_RING_CSR_RING_UBASE     0x080
0015 #define ADF_RING_CSR_RING_HEAD      0x0C0
0016 #define ADF_RING_CSR_RING_TAIL      0x100
0017 #define ADF_RING_CSR_E_STAT     0x14C
0018 #define ADF_RING_CSR_INT_FLAG       0x170
0019 #define ADF_RING_CSR_INT_SRCSEL     0x174
0020 #define ADF_RING_CSR_INT_SRCSEL_2   0x178
0021 #define ADF_RING_CSR_INT_COL_EN     0x17C
0022 #define ADF_RING_CSR_INT_COL_CTL    0x180
0023 #define ADF_RING_CSR_INT_FLAG_AND_COL   0x184
0024 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
0025 #define ADF_RING_BUNDLE_SIZE        0x1000
0026 #define ADF_GEN2_RX_RINGS_OFFSET    8
0027 #define ADF_GEN2_TX_RINGS_MASK      0xFF
0028 
0029 #define BUILD_RING_BASE_ADDR(addr, size) \
0030     (((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
0031 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
0032     ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0033            ADF_RING_CSR_RING_HEAD + ((ring) << 2))
0034 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
0035     ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0036            ADF_RING_CSR_RING_TAIL + ((ring) << 2))
0037 #define READ_CSR_E_STAT(csr_base_addr, bank) \
0038     ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0039            ADF_RING_CSR_E_STAT)
0040 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
0041     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0042            ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
0043 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
0044 do { \
0045     u32 l_base = 0, u_base = 0; \
0046     l_base = (u32)((value) & 0xFFFFFFFF); \
0047     u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \
0048     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0049            ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \
0050     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0051            ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \
0052 } while (0)
0053 
0054 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
0055     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0056            ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
0057 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
0058     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0059            ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
0060 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
0061     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0062            ADF_RING_CSR_INT_FLAG, value)
0063 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
0064 do { \
0065     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0066     ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
0067     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0068     ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
0069 } while (0)
0070 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
0071     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0072            ADF_RING_CSR_INT_COL_EN, value)
0073 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
0074     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0075            ADF_RING_CSR_INT_COL_CTL, \
0076            ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
0077 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
0078     ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
0079            ADF_RING_CSR_INT_FLAG_AND_COL, value)
0080 
0081 /* AE to function map */
0082 #define AE2FUNCTION_MAP_A_OFFSET    (0x3A400 + 0x190)
0083 #define AE2FUNCTION_MAP_B_OFFSET    (0x3A400 + 0x310)
0084 #define AE2FUNCTION_MAP_REG_SIZE    4
0085 #define AE2FUNCTION_MAP_VALID       BIT(7)
0086 
0087 #define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \
0088     ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
0089            AE2FUNCTION_MAP_REG_SIZE * (index))
0090 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \
0091     ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
0092            AE2FUNCTION_MAP_REG_SIZE * (index), value)
0093 #define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \
0094     ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
0095            AE2FUNCTION_MAP_REG_SIZE * (index))
0096 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \
0097     ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
0098            AE2FUNCTION_MAP_REG_SIZE * (index), value)
0099 
0100 /* Admin Interface Offsets */
0101 #define ADF_ADMINMSGUR_OFFSET   (0x3A000 + 0x574)
0102 #define ADF_ADMINMSGLR_OFFSET   (0x3A000 + 0x578)
0103 #define ADF_MAILBOX_BASE_OFFSET 0x20970
0104 
0105 /* Arbiter configuration */
0106 #define ADF_ARB_OFFSET          0x30000
0107 #define ADF_ARB_WRK_2_SER_MAP_OFFSET    0x180
0108 #define ADF_ARB_CONFIG          (BIT(31) | BIT(6) | BIT(0))
0109 #define ADF_ARB_REG_SLOT        0x1000
0110 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
0111 
0112 #define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
0113     ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
0114     (ADF_ARB_REG_SLOT * (index)), value)
0115 
0116 /* Power gating */
0117 #define ADF_POWERGATE_DC        BIT(23)
0118 #define ADF_POWERGATE_PKE       BIT(24)
0119 
0120 /* Default ring mapping */
0121 #define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \
0122     (CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
0123      CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
0124      UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
0125        COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
0126 
0127 /* WDT timers
0128  *
0129  * Timeout is in cycles. Clock speed may vary across products but this
0130  * value should be a few milli-seconds.
0131  */
0132 #define ADF_SSM_WDT_DEFAULT_VALUE   0x200000
0133 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE   0x2000000
0134 #define ADF_SSMWDT_OFFSET       0x54
0135 #define ADF_SSMWDTPKE_OFFSET        0x58
0136 #define ADF_SSMWDT(i)       (ADF_SSMWDT_OFFSET + ((i) * 0x4000))
0137 #define ADF_SSMWDTPKE(i)    (ADF_SSMWDTPKE_OFFSET + ((i) * 0x4000))
0138 
0139 /* Error detection and correction */
0140 #define ADF_GEN2_AE_CTX_ENABLES(i)  ((i) * 0x1000 + 0x20818)
0141 #define ADF_GEN2_AE_MISC_CONTROL(i) ((i) * 0x1000 + 0x20960)
0142 #define ADF_GEN2_ENABLE_AE_ECC_ERR  BIT(28)
0143 #define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR  (BIT(24) | BIT(12))
0144 #define ADF_GEN2_UERRSSMSH(i)       ((i) * 0x4000 + 0x18)
0145 #define ADF_GEN2_CERRSSMSH(i)       ((i) * 0x4000 + 0x10)
0146 #define ADF_GEN2_ERRSSMSH_EN        BIT(3)
0147 
0148 /* Interrupts */
0149 #define ADF_GEN2_SMIAPF0_MASK_OFFSET    (0x3A000 + 0x28)
0150 #define ADF_GEN2_SMIAPF1_MASK_OFFSET    (0x3A000 + 0x30)
0151 #define ADF_GEN2_SMIA1_MASK             0x1
0152 
0153 u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self);
0154 u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self);
0155 void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev);
0156 void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
0157                int num_a_regs, int num_b_regs);
0158 void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
0159 void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info);
0160 void adf_gen2_get_arb_info(struct arb_info *arb_info);
0161 void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev);
0162 u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev);
0163 void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
0164 
0165 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!