qat/qat_c62x/adf_c62x_hw_data.c

0001 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
0002 /* Copyright(c) 2014 - 2021 Intel Corporation */
0003 #include <adf_accel_devices.h>
0004 #include <adf_common_drv.h>
0005 #include <adf_gen2_hw_data.h>
0006 #include <adf_gen2_pfvf.h>
0007 #include "adf_c62x_hw_data.h"
0008 #include "icp_qat_hw.h"
0009
0010 /* Worker thread to service arbiter mappings */
0011 static const u32 thrd_to_arb_map[ADF_C62X_MAX_ACCELENGINES] = {
0012     0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
0013     0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
0014 };
0015
0016 static struct adf_hw_device_class c62x_class = {
0017     .name = ADF_C62X_DEVICE_NAME,
0018     .type = DEV_C62X,
0019     .instances = 0
0020 };
0021
0022 static u32 get_accel_mask(struct adf_hw_device_data *self)
0023 {
0024     u32 straps = self->straps;
0025     u32 fuses = self->fuses;
0026     u32 accel;
0027
0028     accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET;
0029     accel &= ADF_C62X_ACCELERATORS_MASK;
0030
0031     return accel;
0032 }
0033
0034 static u32 get_ae_mask(struct adf_hw_device_data *self)
0035 {
0036     u32 straps = self->straps;
0037     u32 fuses = self->fuses;
0038     unsigned long disabled;
0039     u32 ae_disable;
0040     int accel;
0041
0042     /* If an accel is disabled, then disable the corresponding two AEs */
0043     disabled = ~get_accel_mask(self) & ADF_C62X_ACCELERATORS_MASK;
0044     ae_disable = BIT(1) | BIT(0);
0045     for_each_set_bit(accel, &disabled, ADF_C62X_MAX_ACCELERATORS)
0046         straps |= ae_disable << (accel << 1);
0047
0048     return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK;
0049 }
0050
0051 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
0052 {
0053     return ADF_C62X_PMISC_BAR;
0054 }
0055
0056 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
0057 {
0058     return ADF_C62X_ETR_BAR;
0059 }
0060
0061 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
0062 {
0063     return ADF_C62X_SRAM_BAR;
0064 }
0065
0066 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
0067 {
0068     int aes = self->get_num_aes(self);
0069
0070     if (aes == 8)
0071         return DEV_SKU_2;
0072     else if (aes == 10)
0073         return DEV_SKU_4;
0074
0075     return DEV_SKU_UNKNOWN;
0076 }
0077
0078 static const u32 *adf_get_arbiter_mapping(void)
0079 {
0080     return thrd_to_arb_map;
0081 }
0082
0083 static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
0084 {
0085     adf_gen2_cfg_iov_thds(accel_dev, enable,
0086                   ADF_C62X_AE2FUNC_MAP_GRP_A_NUM_REGS,
0087                   ADF_C62X_AE2FUNC_MAP_GRP_B_NUM_REGS);
0088 }
0089
0090 void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
0091 {
0092     hw_data->dev_class = &c62x_class;
0093     hw_data->instance_id = c62x_class.instances++;
0094     hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;
0095     hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
0096     hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS;
0097     hw_data->num_logical_accel = 1;
0098     hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
0099     hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
0100     hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
0101     hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
0102     hw_data->alloc_irq = adf_isr_resource_alloc;
0103     hw_data->free_irq = adf_isr_resource_free;
0104     hw_data->enable_error_correction = adf_gen2_enable_error_correction;
0105     hw_data->get_accel_mask = get_accel_mask;
0106     hw_data->get_ae_mask = get_ae_mask;
0107     hw_data->get_accel_cap = adf_gen2_get_accel_cap;
0108     hw_data->get_num_accels = adf_gen2_get_num_accels;
0109     hw_data->get_num_aes = adf_gen2_get_num_aes;
0110     hw_data->get_sram_bar_id = get_sram_bar_id;
0111     hw_data->get_etr_bar_id = get_etr_bar_id;
0112     hw_data->get_misc_bar_id = get_misc_bar_id;
0113     hw_data->get_admin_info = adf_gen2_get_admin_info;
0114     hw_data->get_arb_info = adf_gen2_get_arb_info;
0115     hw_data->get_sku = get_sku;
0116     hw_data->fw_name = ADF_C62X_FW;
0117     hw_data->fw_mmp_name = ADF_C62X_MMP;
0118     hw_data->init_admin_comms = adf_init_admin_comms;
0119     hw_data->exit_admin_comms = adf_exit_admin_comms;
0120     hw_data->configure_iov_threads = configure_iov_threads;
0121     hw_data->send_admin_init = adf_send_admin_init;
0122     hw_data->init_arb = adf_init_arb;
0123     hw_data->exit_arb = adf_exit_arb;
0124     hw_data->get_arb_mapping = adf_get_arbiter_mapping;
0125     hw_data->enable_ints = adf_gen2_enable_ints;
0126     hw_data->reset_device = adf_reset_flr;
0127     hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
0128     hw_data->disable_iov = adf_disable_sriov;
0129
0130     adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
0131     adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
0132 }
0133
0134 void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)
0135 {
0136     hw_data->dev_class->instances--;
0137 }