drivers/crypto/padlock-aes.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Cryptographic API.
0004  *
0005  * Support for VIA PadLock hardware crypto engine.
0006  *
0007  * Copyright (c) 2004  Michal Ludvig <michal@logix.cz>
0008  *
0009  */
0010
0011 #include <crypto/algapi.h>
0012 #include <crypto/aes.h>
0013 #include <crypto/internal/skcipher.h>
0014 #include <crypto/padlock.h>
0015 #include <linux/module.h>
0016 #include <linux/init.h>
0017 #include <linux/types.h>
0018 #include <linux/errno.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/kernel.h>
0021 #include <linux/mm.h>
0022 #include <linux/percpu.h>
0023 #include <linux/smp.h>
0024 #include <linux/slab.h>
0025 #include <asm/cpu_device_id.h>
0026 #include <asm/byteorder.h>
0027 #include <asm/processor.h>
0028 #include <asm/fpu/api.h>
0029
0030 /*
0031  * Number of data blocks actually fetched for each xcrypt insn.
0032  * Processors with prefetch errata will fetch extra blocks.
0033  */
0034 static unsigned int ecb_fetch_blocks = 2;
0035 #define MAX_ECB_FETCH_BLOCKS (8)
0036 #define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE)
0037
0038 static unsigned int cbc_fetch_blocks = 1;
0039 #define MAX_CBC_FETCH_BLOCKS (4)
0040 #define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE)
0041
0042 /* Control word. */
0043 struct cword {
0044     unsigned int __attribute__ ((__packed__))
0045         rounds:4,
0046         algo:3,
0047         keygen:1,
0048         interm:1,
0049         encdec:1,
0050         ksize:2;
0051 } __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
0052
0053 /* Whenever making any changes to the following
0054  * structure *make sure* you keep E, d_data
0055  * and cword aligned on 16 Bytes boundaries and
0056  * the Hardware can access 16 * 16 bytes of E and d_data
0057  * (only the first 15 * 16 bytes matter but the HW reads
0058  * more).
0059  */
0060 struct aes_ctx {
0061     u32 E[AES_MAX_KEYLENGTH_U32]
0062         __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
0063     u32 d_data[AES_MAX_KEYLENGTH_U32]
0064         __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
0065     struct {
0066         struct cword encrypt;
0067         struct cword decrypt;
0068     } cword;
0069     u32 *D;
0070 };
0071
0072 static DEFINE_PER_CPU(struct cword *, paes_last_cword);
0073
0074 /* Tells whether the ACE is capable to generate
0075    the extended key for a given key_len. */
0076 static inline int
0077 aes_hw_extkey_available(uint8_t key_len)
0078 {
0079     /* TODO: We should check the actual CPU model/stepping
0080              as it's possible that the capability will be
0081              added in the next CPU revisions. */
0082     if (key_len == 16)
0083         return 1;
0084     return 0;
0085 }
0086
0087 static inline struct aes_ctx *aes_ctx_common(void *ctx)
0088 {
0089     unsigned long addr = (unsigned long)ctx;
0090     unsigned long align = PADLOCK_ALIGNMENT;
0091
0092     if (align <= crypto_tfm_ctx_alignment())
0093         align = 1;
0094     return (struct aes_ctx *)ALIGN(addr, align);
0095 }
0096
0097 static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm)
0098 {
0099     return aes_ctx_common(crypto_tfm_ctx(tfm));
0100 }
0101
0102 static inline struct aes_ctx *skcipher_aes_ctx(struct crypto_skcipher *tfm)
0103 {
0104     return aes_ctx_common(crypto_skcipher_ctx(tfm));
0105 }
0106
0107 static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
0108                unsigned int key_len)
0109 {
0110     struct aes_ctx *ctx = aes_ctx(tfm);
0111     const __le32 *key = (const __le32 *)in_key;
0112     struct crypto_aes_ctx gen_aes;
0113     int cpu;
0114
0115     if (key_len % 8)
0116         return -EINVAL;
0117
0118     /*
0119      * If the hardware is capable of generating the extended key
0120      * itself we must supply the plain key for both encryption
0121      * and decryption.
0122      */
0123     ctx->D = ctx->E;
0124
0125     ctx->E[0] = le32_to_cpu(key[0]);
0126     ctx->E[1] = le32_to_cpu(key[1]);
0127     ctx->E[2] = le32_to_cpu(key[2]);
0128     ctx->E[3] = le32_to_cpu(key[3]);
0129
0130     /* Prepare control words. */
0131     memset(&ctx->cword, 0, sizeof(ctx->cword));
0132
0133     ctx->cword.decrypt.encdec = 1;
0134     ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
0135     ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
0136     ctx->cword.encrypt.ksize = (key_len - 16) / 8;
0137     ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;
0138
0139     /* Don't generate extended keys if the hardware can do it. */
0140     if (aes_hw_extkey_available(key_len))
0141         goto ok;
0142
0143     ctx->D = ctx->d_data;
0144     ctx->cword.encrypt.keygen = 1;
0145     ctx->cword.decrypt.keygen = 1;
0146
0147     if (aes_expandkey(&gen_aes, in_key, key_len))
0148         return -EINVAL;
0149
0150     memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH);
0151     memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH);
0152
0153 ok:
0154     for_each_online_cpu(cpu)
0155         if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) ||
0156             &ctx->cword.decrypt == per_cpu(paes_last_cword, cpu))
0157             per_cpu(paes_last_cword, cpu) = NULL;
0158
0159     return 0;
0160 }
0161
0162 static int aes_set_key_skcipher(struct crypto_skcipher *tfm, const u8 *in_key,
0163                 unsigned int key_len)
0164 {
0165     return aes_set_key(crypto_skcipher_tfm(tfm), in_key, key_len);
0166 }
0167
0168 /* ====== Encryption/decryption routines ====== */
0169
0170 /* These are the real call to PadLock. */
0171 static inline void padlock_reset_key(struct cword *cword)
0172 {
0173     int cpu = raw_smp_processor_id();
0174
0175     if (cword != per_cpu(paes_last_cword, cpu))
0176 #ifndef CONFIG_X86_64
0177         asm volatile ("pushfl; popfl");
0178 #else
0179         asm volatile ("pushfq; popfq");
0180 #endif
0181 }
0182
0183 static inline void padlock_store_cword(struct cword *cword)
0184 {
0185     per_cpu(paes_last_cword, raw_smp_processor_id()) = cword;
0186 }
0187
0188 /*
0189  * While the padlock instructions don't use FP/SSE registers, they
0190  * generate a spurious DNA fault when CR0.TS is '1'.  Fortunately,
0191  * the kernel doesn't use CR0.TS.
0192  */
0193
0194 static inline void rep_xcrypt_ecb(const u8 *input, u8 *output, void *key,
0195                   struct cword *control_word, int count)
0196 {
0197     asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"   /* rep xcryptecb */
0198               : "+S"(input), "+D"(output)
0199               : "d"(control_word), "b"(key), "c"(count));
0200 }
0201
0202 static inline u8 *rep_xcrypt_cbc(const u8 *input, u8 *output, void *key,
0203                  u8 *iv, struct cword *control_word, int count)
0204 {
0205     asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"   /* rep xcryptcbc */
0206               : "+S" (input), "+D" (output), "+a" (iv)
0207               : "d" (control_word), "b" (key), "c" (count));
0208     return iv;
0209 }
0210
0211 static void ecb_crypt_copy(const u8 *in, u8 *out, u32 *key,
0212                struct cword *cword, int count)
0213 {
0214     /*
0215      * Padlock prefetches extra data so we must provide mapped input buffers.
0216      * Assume there are at least 16 bytes of stack already in use.
0217      */
0218     u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
0219     u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0220
0221     memcpy(tmp, in, count * AES_BLOCK_SIZE);
0222     rep_xcrypt_ecb(tmp, out, key, cword, count);
0223 }
0224
0225 static u8 *cbc_crypt_copy(const u8 *in, u8 *out, u32 *key,
0226                u8 *iv, struct cword *cword, int count)
0227 {
0228     /*
0229      * Padlock prefetches extra data so we must provide mapped input buffers.
0230      * Assume there are at least 16 bytes of stack already in use.
0231      */
0232     u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
0233     u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
0234
0235     memcpy(tmp, in, count * AES_BLOCK_SIZE);
0236     return rep_xcrypt_cbc(tmp, out, key, iv, cword, count);
0237 }
0238
0239 static inline void ecb_crypt(const u8 *in, u8 *out, u32 *key,
0240                  struct cword *cword, int count)
0241 {
0242     /* Padlock in ECB mode fetches at least ecb_fetch_bytes of data.
0243      * We could avoid some copying here but it's probably not worth it.
0244      */
0245     if (unlikely(offset_in_page(in) + ecb_fetch_bytes > PAGE_SIZE)) {
0246         ecb_crypt_copy(in, out, key, cword, count);
0247         return;
0248     }
0249
0250     rep_xcrypt_ecb(in, out, key, cword, count);
0251 }
0252
0253 static inline u8 *cbc_crypt(const u8 *in, u8 *out, u32 *key,
0254                 u8 *iv, struct cword *cword, int count)
0255 {
0256     /* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */
0257     if (unlikely(offset_in_page(in) + cbc_fetch_bytes > PAGE_SIZE))
0258         return cbc_crypt_copy(in, out, key, iv, cword, count);
0259
0260     return rep_xcrypt_cbc(in, out, key, iv, cword, count);
0261 }
0262
0263 static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key,
0264                       void *control_word, u32 count)
0265 {
0266     u32 initial = count & (ecb_fetch_blocks - 1);
0267
0268     if (count < ecb_fetch_blocks) {
0269         ecb_crypt(input, output, key, control_word, count);
0270         return;
0271     }
0272
0273     count -= initial;
0274
0275     if (initial)
0276         asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"   /* rep xcryptecb */
0277                   : "+S"(input), "+D"(output)
0278                   : "d"(control_word), "b"(key), "c"(initial));
0279
0280     asm volatile (".byte 0xf3,0x0f,0xa7,0xc8"   /* rep xcryptecb */
0281               : "+S"(input), "+D"(output)
0282               : "d"(control_word), "b"(key), "c"(count));
0283 }
0284
0285 static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key,
0286                      u8 *iv, void *control_word, u32 count)
0287 {
0288     u32 initial = count & (cbc_fetch_blocks - 1);
0289
0290     if (count < cbc_fetch_blocks)
0291         return cbc_crypt(input, output, key, iv, control_word, count);
0292
0293     count -= initial;
0294
0295     if (initial)
0296         asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"   /* rep xcryptcbc */
0297                   : "+S" (input), "+D" (output), "+a" (iv)
0298                   : "d" (control_word), "b" (key), "c" (initial));
0299
0300     asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"   /* rep xcryptcbc */
0301               : "+S" (input), "+D" (output), "+a" (iv)
0302               : "d" (control_word), "b" (key), "c" (count));
0303     return iv;
0304 }
0305
0306 static void padlock_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
0307 {
0308     struct aes_ctx *ctx = aes_ctx(tfm);
0309
0310     padlock_reset_key(&ctx->cword.encrypt);
0311     ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1);
0312     padlock_store_cword(&ctx->cword.encrypt);
0313 }
0314
0315 static void padlock_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
0316 {
0317     struct aes_ctx *ctx = aes_ctx(tfm);
0318
0319     padlock_reset_key(&ctx->cword.encrypt);
0320     ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1);
0321     padlock_store_cword(&ctx->cword.encrypt);
0322 }
0323
0324 static struct crypto_alg aes_alg = {
0325     .cra_name       =   "aes",
0326     .cra_driver_name    =   "aes-padlock",
0327     .cra_priority       =   PADLOCK_CRA_PRIORITY,
0328     .cra_flags      =   CRYPTO_ALG_TYPE_CIPHER,
0329     .cra_blocksize      =   AES_BLOCK_SIZE,
0330     .cra_ctxsize        =   sizeof(struct aes_ctx),
0331     .cra_alignmask      =   PADLOCK_ALIGNMENT - 1,
0332     .cra_module     =   THIS_MODULE,
0333     .cra_u          =   {
0334         .cipher = {
0335             .cia_min_keysize    =   AES_MIN_KEY_SIZE,
0336             .cia_max_keysize    =   AES_MAX_KEY_SIZE,
0337             .cia_setkey     =   aes_set_key,
0338             .cia_encrypt        =   padlock_aes_encrypt,
0339             .cia_decrypt        =   padlock_aes_decrypt,
0340         }
0341     }
0342 };
0343
0344 static int ecb_aes_encrypt(struct skcipher_request *req)
0345 {
0346     struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
0347     struct aes_ctx *ctx = skcipher_aes_ctx(tfm);
0348     struct skcipher_walk walk;
0349     unsigned int nbytes;
0350     int err;
0351
0352     padlock_reset_key(&ctx->cword.encrypt);
0353
0354     err = skcipher_walk_virt(&walk, req, false);
0355
0356     while ((nbytes = walk.nbytes) != 0) {
0357         padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
0358                    ctx->E, &ctx->cword.encrypt,
0359                    nbytes / AES_BLOCK_SIZE);
0360         nbytes &= AES_BLOCK_SIZE - 1;
0361         err = skcipher_walk_done(&walk, nbytes);
0362     }
0363
0364     padlock_store_cword(&ctx->cword.encrypt);
0365
0366     return err;
0367 }
0368
0369 static int ecb_aes_decrypt(struct skcipher_request *req)
0370 {
0371     struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
0372     struct aes_ctx *ctx = skcipher_aes_ctx(tfm);
0373     struct skcipher_walk walk;
0374     unsigned int nbytes;
0375     int err;
0376
0377     padlock_reset_key(&ctx->cword.decrypt);
0378
0379     err = skcipher_walk_virt(&walk, req, false);
0380
0381     while ((nbytes = walk.nbytes) != 0) {
0382         padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
0383                    ctx->D, &ctx->cword.decrypt,
0384                    nbytes / AES_BLOCK_SIZE);
0385         nbytes &= AES_BLOCK_SIZE - 1;
0386         err = skcipher_walk_done(&walk, nbytes);
0387     }
0388
0389     padlock_store_cword(&ctx->cword.encrypt);
0390
0391     return err;
0392 }
0393
0394 static struct skcipher_alg ecb_aes_alg = {
0395     .base.cra_name      =   "ecb(aes)",
0396     .base.cra_driver_name   =   "ecb-aes-padlock",
0397     .base.cra_priority  =   PADLOCK_COMPOSITE_PRIORITY,
0398     .base.cra_blocksize =   AES_BLOCK_SIZE,
0399     .base.cra_ctxsize   =   sizeof(struct aes_ctx),
0400     .base.cra_alignmask =   PADLOCK_ALIGNMENT - 1,
0401     .base.cra_module    =   THIS_MODULE,
0402     .min_keysize        =   AES_MIN_KEY_SIZE,
0403     .max_keysize        =   AES_MAX_KEY_SIZE,
0404     .setkey         =   aes_set_key_skcipher,
0405     .encrypt        =   ecb_aes_encrypt,
0406     .decrypt        =   ecb_aes_decrypt,
0407 };
0408
0409 static int cbc_aes_encrypt(struct skcipher_request *req)
0410 {
0411     struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
0412     struct aes_ctx *ctx = skcipher_aes_ctx(tfm);
0413     struct skcipher_walk walk;
0414     unsigned int nbytes;
0415     int err;
0416
0417     padlock_reset_key(&ctx->cword.encrypt);
0418
0419     err = skcipher_walk_virt(&walk, req, false);
0420
0421     while ((nbytes = walk.nbytes) != 0) {
0422         u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
0423                         walk.dst.virt.addr, ctx->E,
0424                         walk.iv, &ctx->cword.encrypt,
0425                         nbytes / AES_BLOCK_SIZE);
0426         memcpy(walk.iv, iv, AES_BLOCK_SIZE);
0427         nbytes &= AES_BLOCK_SIZE - 1;
0428         err = skcipher_walk_done(&walk, nbytes);
0429     }
0430
0431     padlock_store_cword(&ctx->cword.decrypt);
0432
0433     return err;
0434 }
0435
0436 static int cbc_aes_decrypt(struct skcipher_request *req)
0437 {
0438     struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
0439     struct aes_ctx *ctx = skcipher_aes_ctx(tfm);
0440     struct skcipher_walk walk;
0441     unsigned int nbytes;
0442     int err;
0443
0444     padlock_reset_key(&ctx->cword.encrypt);
0445
0446     err = skcipher_walk_virt(&walk, req, false);
0447
0448     while ((nbytes = walk.nbytes) != 0) {
0449         padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
0450                    ctx->D, walk.iv, &ctx->cword.decrypt,
0451                    nbytes / AES_BLOCK_SIZE);
0452         nbytes &= AES_BLOCK_SIZE - 1;
0453         err = skcipher_walk_done(&walk, nbytes);
0454     }
0455
0456     padlock_store_cword(&ctx->cword.encrypt);
0457
0458     return err;
0459 }
0460
0461 static struct skcipher_alg cbc_aes_alg = {
0462     .base.cra_name      =   "cbc(aes)",
0463     .base.cra_driver_name   =   "cbc-aes-padlock",
0464     .base.cra_priority  =   PADLOCK_COMPOSITE_PRIORITY,
0465     .base.cra_blocksize =   AES_BLOCK_SIZE,
0466     .base.cra_ctxsize   =   sizeof(struct aes_ctx),
0467     .base.cra_alignmask =   PADLOCK_ALIGNMENT - 1,
0468     .base.cra_module    =   THIS_MODULE,
0469     .min_keysize        =   AES_MIN_KEY_SIZE,
0470     .max_keysize        =   AES_MAX_KEY_SIZE,
0471     .ivsize         =   AES_BLOCK_SIZE,
0472     .setkey         =   aes_set_key_skcipher,
0473     .encrypt        =   cbc_aes_encrypt,
0474     .decrypt        =   cbc_aes_decrypt,
0475 };
0476
0477 static const struct x86_cpu_id padlock_cpu_id[] = {
0478     X86_MATCH_FEATURE(X86_FEATURE_XCRYPT, NULL),
0479     {}
0480 };
0481 MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);
0482
0483 static int __init padlock_init(void)
0484 {
0485     int ret;
0486     struct cpuinfo_x86 *c = &cpu_data(0);
0487
0488     if (!x86_match_cpu(padlock_cpu_id))
0489         return -ENODEV;
0490
0491     if (!boot_cpu_has(X86_FEATURE_XCRYPT_EN)) {
0492         printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
0493         return -ENODEV;
0494     }
0495
0496     if ((ret = crypto_register_alg(&aes_alg)) != 0)
0497         goto aes_err;
0498
0499     if ((ret = crypto_register_skcipher(&ecb_aes_alg)) != 0)
0500         goto ecb_aes_err;
0501
0502     if ((ret = crypto_register_skcipher(&cbc_aes_alg)) != 0)
0503         goto cbc_aes_err;
0504
0505     printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
0506
0507     if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) {
0508         ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
0509         cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
0510         printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
0511     }
0512
0513 out:
0514     return ret;
0515
0516 cbc_aes_err:
0517     crypto_unregister_skcipher(&ecb_aes_alg);
0518 ecb_aes_err:
0519     crypto_unregister_alg(&aes_alg);
0520 aes_err:
0521     printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
0522     goto out;
0523 }
0524
0525 static void __exit padlock_fini(void)
0526 {
0527     crypto_unregister_skcipher(&cbc_aes_alg);
0528     crypto_unregister_skcipher(&ecb_aes_alg);
0529     crypto_unregister_alg(&aes_alg);
0530 }
0531
0532 module_init(padlock_init);
0533 module_exit(padlock_fini);
0534
0535 MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
0536 MODULE_LICENSE("GPL");
0537 MODULE_AUTHOR("Michal Ludvig");
0538
0539 MODULE_ALIAS_CRYPTO("aes");