drivers/crypto/omap-aes.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Cryptographic API.
0004  *
0005  * Support for OMAP AES HW ACCELERATOR defines
0006  *
0007  * Copyright (c) 2015 Texas Instruments Incorporated
0008  */
0009 #ifndef __OMAP_AES_H__
0010 #define __OMAP_AES_H__
0011
0012 #include <crypto/aes.h>
0013 #include <crypto/engine.h>
0014
0015 #define DST_MAXBURST            4
0016 #define DMA_MIN             (DST_MAXBURST * sizeof(u32))
0017
0018 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
0019
0020 /*
0021  * OMAP TRM gives bitfields as start:end, where start is the higher bit
0022  * number. For example 7:0
0023  */
0024 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
0025 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
0026
0027 #define AES_REG_KEY(dd, x)      ((dd)->pdata->key_ofs - \
0028                         (((x) ^ 0x01) * 0x04))
0029 #define AES_REG_IV(dd, x)       ((dd)->pdata->iv_ofs + ((x) * 0x04))
0030
0031 #define AES_REG_CTRL(dd)        ((dd)->pdata->ctrl_ofs)
0032 #define AES_REG_CTRL_CONTEXT_READY  BIT(31)
0033 #define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7)
0034 #define AES_REG_CTRL_CTR_WIDTH_32   0
0035 #define AES_REG_CTRL_CTR_WIDTH_64   BIT(7)
0036 #define AES_REG_CTRL_CTR_WIDTH_96   BIT(8)
0037 #define AES_REG_CTRL_CTR_WIDTH_128  GENMASK(8, 7)
0038 #define AES_REG_CTRL_GCM        GENMASK(17, 16)
0039 #define AES_REG_CTRL_CTR        BIT(6)
0040 #define AES_REG_CTRL_CBC        BIT(5)
0041 #define AES_REG_CTRL_KEY_SIZE       GENMASK(4, 3)
0042 #define AES_REG_CTRL_DIRECTION      BIT(2)
0043 #define AES_REG_CTRL_INPUT_READY    BIT(1)
0044 #define AES_REG_CTRL_OUTPUT_READY   BIT(0)
0045 #define AES_REG_CTRL_MASK       GENMASK(24, 2)
0046
0047 #define AES_REG_C_LEN_0         0x54
0048 #define AES_REG_C_LEN_1         0x58
0049 #define AES_REG_A_LEN           0x5C
0050
0051 #define AES_REG_DATA_N(dd, x)       ((dd)->pdata->data_ofs + ((x) * 0x04))
0052 #define AES_REG_TAG_N(dd, x)        (0x70 + ((x) * 0x04))
0053
0054 #define AES_REG_REV(dd)         ((dd)->pdata->rev_ofs)
0055
0056 #define AES_REG_MASK(dd)        ((dd)->pdata->mask_ofs)
0057 #define AES_REG_MASK_SIDLE      BIT(6)
0058 #define AES_REG_MASK_START      BIT(5)
0059 #define AES_REG_MASK_DMA_OUT_EN     BIT(3)
0060 #define AES_REG_MASK_DMA_IN_EN      BIT(2)
0061 #define AES_REG_MASK_SOFTRESET      BIT(1)
0062 #define AES_REG_AUTOIDLE        BIT(0)
0063
0064 #define AES_REG_LENGTH_N(x)     (0x54 + ((x) * 0x04))
0065
0066 #define AES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
0067 #define AES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
0068 #define AES_REG_IRQ_DATA_IN            BIT(1)
0069 #define AES_REG_IRQ_DATA_OUT           BIT(2)
0070 #define DEFAULT_TIMEOUT     (5 * HZ)
0071
0072 #define DEFAULT_AUTOSUSPEND_DELAY   1000
0073
0074 #define FLAGS_MODE_MASK     0x001f
0075 #define FLAGS_ENCRYPT       BIT(0)
0076 #define FLAGS_CBC       BIT(1)
0077 #define FLAGS_CTR       BIT(2)
0078 #define FLAGS_GCM       BIT(3)
0079 #define FLAGS_RFC4106_GCM   BIT(4)
0080
0081 #define FLAGS_INIT      BIT(5)
0082 #define FLAGS_FAST      BIT(6)
0083
0084 #define FLAGS_IN_DATA_ST_SHIFT  8
0085 #define FLAGS_OUT_DATA_ST_SHIFT 10
0086 #define FLAGS_ASSOC_DATA_ST_SHIFT   12
0087
0088 #define AES_BLOCK_WORDS     (AES_BLOCK_SIZE >> 2)
0089
0090 struct omap_aes_gcm_result {
0091     struct completion completion;
0092     int err;
0093 };
0094
0095 struct omap_aes_ctx {
0096     struct crypto_engine_ctx enginectx;
0097     int     keylen;
0098     u32     key[AES_KEYSIZE_256 / sizeof(u32)];
0099     u8      nonce[4];
0100     struct crypto_skcipher  *fallback;
0101 };
0102
0103 struct omap_aes_gcm_ctx {
0104     struct omap_aes_ctx octx;
0105     struct crypto_aes_ctx   actx;
0106 };
0107
0108 struct omap_aes_reqctx {
0109     struct omap_aes_dev *dd;
0110     unsigned long mode;
0111     u8 iv[AES_BLOCK_SIZE];
0112     u32 auth_tag[AES_BLOCK_SIZE / sizeof(u32)];
0113     struct skcipher_request fallback_req;   // keep at the end
0114 };
0115
0116 #define OMAP_AES_QUEUE_LENGTH   1
0117 #define OMAP_AES_CACHE_SIZE 0
0118
0119 struct omap_aes_algs_info {
0120     struct skcipher_alg *algs_list;
0121     unsigned int        size;
0122     unsigned int        registered;
0123 };
0124
0125 struct omap_aes_aead_algs {
0126     struct aead_alg *algs_list;
0127     unsigned int    size;
0128     unsigned int    registered;
0129 };
0130
0131 struct omap_aes_pdata {
0132     struct omap_aes_algs_info   *algs_info;
0133     unsigned int    algs_info_size;
0134     struct omap_aes_aead_algs   *aead_algs_info;
0135
0136     void        (*trigger)(struct omap_aes_dev *dd, int length);
0137
0138     u32     key_ofs;
0139     u32     iv_ofs;
0140     u32     ctrl_ofs;
0141     u32     data_ofs;
0142     u32     rev_ofs;
0143     u32     mask_ofs;
0144     u32             irq_enable_ofs;
0145     u32             irq_status_ofs;
0146
0147     u32     dma_enable_in;
0148     u32     dma_enable_out;
0149     u32     dma_start;
0150
0151     u32     major_mask;
0152     u32     major_shift;
0153     u32     minor_mask;
0154     u32     minor_shift;
0155 };
0156
0157 struct omap_aes_dev {
0158     struct list_head    list;
0159     unsigned long       phys_base;
0160     void __iomem        *io_base;
0161     struct omap_aes_ctx *ctx;
0162     struct device       *dev;
0163     unsigned long       flags;
0164     int         err;
0165
0166     struct tasklet_struct   done_task;
0167     struct aead_queue   aead_queue;
0168     spinlock_t      lock;
0169
0170     struct skcipher_request     *req;
0171     struct aead_request     *aead_req;
0172     struct crypto_engine        *engine;
0173
0174     /*
0175      * total is used by PIO mode for book keeping so introduce
0176      * variable total_save as need it to calc page_order
0177      */
0178     size_t              total;
0179     size_t              total_save;
0180     size_t              assoc_len;
0181     size_t              authsize;
0182
0183     struct scatterlist      *in_sg;
0184     struct scatterlist      *out_sg;
0185
0186     /* Buffers for copying for unaligned cases */
0187     struct scatterlist      in_sgl[2];
0188     struct scatterlist      out_sgl;
0189     struct scatterlist      *orig_out;
0190
0191     struct scatter_walk     in_walk;
0192     struct scatter_walk     out_walk;
0193     struct dma_chan     *dma_lch_in;
0194     struct dma_chan     *dma_lch_out;
0195     int         in_sg_len;
0196     int         out_sg_len;
0197     int         pio_only;
0198     const struct omap_aes_pdata *pdata;
0199 };
0200
0201 u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset);
0202 void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value);
0203 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx);
0204 int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
0205             unsigned int keylen);
0206 int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key,
0207                 unsigned int keylen);
0208 int omap_aes_gcm_encrypt(struct aead_request *req);
0209 int omap_aes_gcm_decrypt(struct aead_request *req);
0210 int omap_aes_gcm_setauthsize(struct crypto_aead *tfm, unsigned int authsize);
0211 int omap_aes_4106gcm_encrypt(struct aead_request *req);
0212 int omap_aes_4106gcm_decrypt(struct aead_request *req);
0213 int omap_aes_4106gcm_setauthsize(struct crypto_aead *parent,
0214                  unsigned int authsize);
0215 int omap_aes_gcm_cra_init(struct crypto_aead *tfm);
0216 int omap_aes_write_ctrl(struct omap_aes_dev *dd);
0217 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd);
0218 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd);
0219 void omap_aes_gcm_dma_out_callback(void *data);
0220 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd);
0221
0222 #endif