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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Cryptographic API.
0004  *
0005  * Support for OMAP AES HW acceleration.
0006  *
0007  * Copyright (c) 2010 Nokia Corporation
0008  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
0009  * Copyright (c) 2011 Texas Instruments Incorporated
0010  */
0011 
0012 #define pr_fmt(fmt) "%20s: " fmt, __func__
0013 #define prn(num) pr_debug(#num "=%d\n", num)
0014 #define prx(num) pr_debug(#num "=%x\n", num)
0015 
0016 #include <linux/err.h>
0017 #include <linux/module.h>
0018 #include <linux/init.h>
0019 #include <linux/errno.h>
0020 #include <linux/kernel.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/scatterlist.h>
0023 #include <linux/dma-mapping.h>
0024 #include <linux/dmaengine.h>
0025 #include <linux/pm_runtime.h>
0026 #include <linux/of.h>
0027 #include <linux/of_device.h>
0028 #include <linux/of_address.h>
0029 #include <linux/io.h>
0030 #include <linux/crypto.h>
0031 #include <linux/interrupt.h>
0032 #include <crypto/scatterwalk.h>
0033 #include <crypto/aes.h>
0034 #include <crypto/gcm.h>
0035 #include <crypto/engine.h>
0036 #include <crypto/internal/skcipher.h>
0037 #include <crypto/internal/aead.h>
0038 
0039 #include "omap-crypto.h"
0040 #include "omap-aes.h"
0041 
0042 /* keep registered devices data here */
0043 static LIST_HEAD(dev_list);
0044 static DEFINE_SPINLOCK(list_lock);
0045 
0046 static int aes_fallback_sz = 200;
0047 
0048 #ifdef DEBUG
0049 #define omap_aes_read(dd, offset)               \
0050 ({                              \
0051     int _read_ret;                      \
0052     _read_ret = __raw_readl(dd->io_base + offset);      \
0053     pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",   \
0054          offset, _read_ret);                \
0055     _read_ret;                      \
0056 })
0057 #else
0058 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
0059 {
0060     return __raw_readl(dd->io_base + offset);
0061 }
0062 #endif
0063 
0064 #ifdef DEBUG
0065 #define omap_aes_write(dd, offset, value)               \
0066     do {                                \
0067         pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
0068              offset, value);                \
0069         __raw_writel(value, dd->io_base + offset);      \
0070     } while (0)
0071 #else
0072 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
0073                   u32 value)
0074 {
0075     __raw_writel(value, dd->io_base + offset);
0076 }
0077 #endif
0078 
0079 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
0080                     u32 value, u32 mask)
0081 {
0082     u32 val;
0083 
0084     val = omap_aes_read(dd, offset);
0085     val &= ~mask;
0086     val |= value;
0087     omap_aes_write(dd, offset, val);
0088 }
0089 
0090 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
0091                     u32 *value, int count)
0092 {
0093     for (; count--; value++, offset += 4)
0094         omap_aes_write(dd, offset, *value);
0095 }
0096 
0097 static int omap_aes_hw_init(struct omap_aes_dev *dd)
0098 {
0099     int err;
0100 
0101     if (!(dd->flags & FLAGS_INIT)) {
0102         dd->flags |= FLAGS_INIT;
0103         dd->err = 0;
0104     }
0105 
0106     err = pm_runtime_resume_and_get(dd->dev);
0107     if (err < 0) {
0108         dev_err(dd->dev, "failed to get sync: %d\n", err);
0109         return err;
0110     }
0111 
0112     return 0;
0113 }
0114 
0115 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
0116 {
0117     dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
0118     dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
0119     dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
0120 }
0121 
0122 int omap_aes_write_ctrl(struct omap_aes_dev *dd)
0123 {
0124     struct omap_aes_reqctx *rctx;
0125     unsigned int key32;
0126     int i, err;
0127     u32 val;
0128 
0129     err = omap_aes_hw_init(dd);
0130     if (err)
0131         return err;
0132 
0133     key32 = dd->ctx->keylen / sizeof(u32);
0134 
0135     /* RESET the key as previous HASH keys should not get affected*/
0136     if (dd->flags & FLAGS_GCM)
0137         for (i = 0; i < 0x40; i = i + 4)
0138             omap_aes_write(dd, i, 0x0);
0139 
0140     for (i = 0; i < key32; i++) {
0141         omap_aes_write(dd, AES_REG_KEY(dd, i),
0142                    (__force u32)cpu_to_le32(dd->ctx->key[i]));
0143     }
0144 
0145     if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv)
0146         omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4);
0147 
0148     if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
0149         rctx = aead_request_ctx(dd->aead_req);
0150         omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
0151     }
0152 
0153     val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
0154     if (dd->flags & FLAGS_CBC)
0155         val |= AES_REG_CTRL_CBC;
0156 
0157     if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
0158         val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
0159 
0160     if (dd->flags & FLAGS_GCM)
0161         val |= AES_REG_CTRL_GCM;
0162 
0163     if (dd->flags & FLAGS_ENCRYPT)
0164         val |= AES_REG_CTRL_DIRECTION;
0165 
0166     omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
0167 
0168     return 0;
0169 }
0170 
0171 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
0172 {
0173     u32 mask, val;
0174 
0175     val = dd->pdata->dma_start;
0176 
0177     if (dd->dma_lch_out != NULL)
0178         val |= dd->pdata->dma_enable_out;
0179     if (dd->dma_lch_in != NULL)
0180         val |= dd->pdata->dma_enable_in;
0181 
0182     mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
0183            dd->pdata->dma_start;
0184 
0185     omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
0186 
0187 }
0188 
0189 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
0190 {
0191     omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
0192     omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
0193     if (dd->flags & FLAGS_GCM)
0194         omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
0195 
0196     omap_aes_dma_trigger_omap2(dd, length);
0197 }
0198 
0199 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
0200 {
0201     u32 mask;
0202 
0203     mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
0204            dd->pdata->dma_start;
0205 
0206     omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
0207 }
0208 
0209 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
0210 {
0211     struct omap_aes_dev *dd;
0212 
0213     spin_lock_bh(&list_lock);
0214     dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
0215     list_move_tail(&dd->list, &dev_list);
0216     rctx->dd = dd;
0217     spin_unlock_bh(&list_lock);
0218 
0219     return dd;
0220 }
0221 
0222 static void omap_aes_dma_out_callback(void *data)
0223 {
0224     struct omap_aes_dev *dd = data;
0225 
0226     /* dma_lch_out - completed */
0227     tasklet_schedule(&dd->done_task);
0228 }
0229 
0230 static int omap_aes_dma_init(struct omap_aes_dev *dd)
0231 {
0232     int err;
0233 
0234     dd->dma_lch_out = NULL;
0235     dd->dma_lch_in = NULL;
0236 
0237     dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
0238     if (IS_ERR(dd->dma_lch_in)) {
0239         dev_err(dd->dev, "Unable to request in DMA channel\n");
0240         return PTR_ERR(dd->dma_lch_in);
0241     }
0242 
0243     dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
0244     if (IS_ERR(dd->dma_lch_out)) {
0245         dev_err(dd->dev, "Unable to request out DMA channel\n");
0246         err = PTR_ERR(dd->dma_lch_out);
0247         goto err_dma_out;
0248     }
0249 
0250     return 0;
0251 
0252 err_dma_out:
0253     dma_release_channel(dd->dma_lch_in);
0254 
0255     return err;
0256 }
0257 
0258 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
0259 {
0260     if (dd->pio_only)
0261         return;
0262 
0263     dma_release_channel(dd->dma_lch_out);
0264     dma_release_channel(dd->dma_lch_in);
0265 }
0266 
0267 static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
0268                   struct scatterlist *in_sg,
0269                   struct scatterlist *out_sg,
0270                   int in_sg_len, int out_sg_len)
0271 {
0272     struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc;
0273     struct dma_slave_config cfg;
0274     int ret;
0275 
0276     if (dd->pio_only) {
0277         scatterwalk_start(&dd->in_walk, dd->in_sg);
0278         if (out_sg_len)
0279             scatterwalk_start(&dd->out_walk, dd->out_sg);
0280 
0281         /* Enable DATAIN interrupt and let it take
0282            care of the rest */
0283         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
0284         return 0;
0285     }
0286 
0287     dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
0288 
0289     memset(&cfg, 0, sizeof(cfg));
0290 
0291     cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
0292     cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
0293     cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0294     cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0295     cfg.src_maxburst = DST_MAXBURST;
0296     cfg.dst_maxburst = DST_MAXBURST;
0297 
0298     /* IN */
0299     ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
0300     if (ret) {
0301         dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
0302             ret);
0303         return ret;
0304     }
0305 
0306     tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
0307                     DMA_MEM_TO_DEV,
0308                     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0309     if (!tx_in) {
0310         dev_err(dd->dev, "IN prep_slave_sg() failed\n");
0311         return -EINVAL;
0312     }
0313 
0314     /* No callback necessary */
0315     tx_in->callback_param = dd;
0316     tx_in->callback = NULL;
0317 
0318     /* OUT */
0319     if (out_sg_len) {
0320         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
0321         if (ret) {
0322             dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
0323                 ret);
0324             return ret;
0325         }
0326 
0327         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg,
0328                          out_sg_len,
0329                          DMA_DEV_TO_MEM,
0330                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0331         if (!tx_out) {
0332             dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
0333             return -EINVAL;
0334         }
0335 
0336         cb_desc = tx_out;
0337     } else {
0338         cb_desc = tx_in;
0339     }
0340 
0341     if (dd->flags & FLAGS_GCM)
0342         cb_desc->callback = omap_aes_gcm_dma_out_callback;
0343     else
0344         cb_desc->callback = omap_aes_dma_out_callback;
0345     cb_desc->callback_param = dd;
0346 
0347 
0348     dmaengine_submit(tx_in);
0349     if (tx_out)
0350         dmaengine_submit(tx_out);
0351 
0352     dma_async_issue_pending(dd->dma_lch_in);
0353     if (out_sg_len)
0354         dma_async_issue_pending(dd->dma_lch_out);
0355 
0356     /* start DMA */
0357     dd->pdata->trigger(dd, dd->total);
0358 
0359     return 0;
0360 }
0361 
0362 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
0363 {
0364     int err;
0365 
0366     pr_debug("total: %zu\n", dd->total);
0367 
0368     if (!dd->pio_only) {
0369         err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
0370                  DMA_TO_DEVICE);
0371         if (!err) {
0372             dev_err(dd->dev, "dma_map_sg() error\n");
0373             return -EINVAL;
0374         }
0375 
0376         if (dd->out_sg_len) {
0377             err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
0378                      DMA_FROM_DEVICE);
0379             if (!err) {
0380                 dev_err(dd->dev, "dma_map_sg() error\n");
0381                 return -EINVAL;
0382             }
0383         }
0384     }
0385 
0386     err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
0387                  dd->out_sg_len);
0388     if (err && !dd->pio_only) {
0389         dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
0390         if (dd->out_sg_len)
0391             dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
0392                      DMA_FROM_DEVICE);
0393     }
0394 
0395     return err;
0396 }
0397 
0398 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
0399 {
0400     struct skcipher_request *req = dd->req;
0401 
0402     pr_debug("err: %d\n", err);
0403 
0404     crypto_finalize_skcipher_request(dd->engine, req, err);
0405 
0406     pm_runtime_mark_last_busy(dd->dev);
0407     pm_runtime_put_autosuspend(dd->dev);
0408 }
0409 
0410 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
0411 {
0412     pr_debug("total: %zu\n", dd->total);
0413 
0414     omap_aes_dma_stop(dd);
0415 
0416 
0417     return 0;
0418 }
0419 
0420 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
0421                  struct skcipher_request *req)
0422 {
0423     if (req)
0424         return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
0425 
0426     return 0;
0427 }
0428 
0429 static int omap_aes_prepare_req(struct crypto_engine *engine,
0430                 void *areq)
0431 {
0432     struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
0433     struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
0434             crypto_skcipher_reqtfm(req));
0435     struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
0436     struct omap_aes_dev *dd = rctx->dd;
0437     int ret;
0438     u16 flags;
0439 
0440     if (!dd)
0441         return -ENODEV;
0442 
0443     /* assign new request to device */
0444     dd->req = req;
0445     dd->total = req->cryptlen;
0446     dd->total_save = req->cryptlen;
0447     dd->in_sg = req->src;
0448     dd->out_sg = req->dst;
0449     dd->orig_out = req->dst;
0450 
0451     flags = OMAP_CRYPTO_COPY_DATA;
0452     if (req->src == req->dst)
0453         flags |= OMAP_CRYPTO_FORCE_COPY;
0454 
0455     ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
0456                    dd->in_sgl, flags,
0457                    FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
0458     if (ret)
0459         return ret;
0460 
0461     ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
0462                    &dd->out_sgl, 0,
0463                    FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
0464     if (ret)
0465         return ret;
0466 
0467     dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
0468     if (dd->in_sg_len < 0)
0469         return dd->in_sg_len;
0470 
0471     dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
0472     if (dd->out_sg_len < 0)
0473         return dd->out_sg_len;
0474 
0475     rctx->mode &= FLAGS_MODE_MASK;
0476     dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
0477 
0478     dd->ctx = ctx;
0479     rctx->dd = dd;
0480 
0481     return omap_aes_write_ctrl(dd);
0482 }
0483 
0484 static int omap_aes_crypt_req(struct crypto_engine *engine,
0485                   void *areq)
0486 {
0487     struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
0488     struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
0489     struct omap_aes_dev *dd = rctx->dd;
0490 
0491     if (!dd)
0492         return -ENODEV;
0493 
0494     return omap_aes_crypt_dma_start(dd);
0495 }
0496 
0497 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf)
0498 {
0499     int i;
0500 
0501     for (i = 0; i < 4; i++)
0502         ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i));
0503 }
0504 
0505 static void omap_aes_done_task(unsigned long data)
0506 {
0507     struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
0508 
0509     pr_debug("enter done_task\n");
0510 
0511     if (!dd->pio_only) {
0512         dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
0513                        DMA_FROM_DEVICE);
0514         dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
0515         dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
0516                  DMA_FROM_DEVICE);
0517         omap_aes_crypt_dma_stop(dd);
0518     }
0519 
0520     omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save,
0521                 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
0522 
0523     omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save,
0524                 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
0525 
0526     /* Update IV output */
0527     if (dd->flags & (FLAGS_CBC | FLAGS_CTR))
0528         omap_aes_copy_ivout(dd, dd->req->iv);
0529 
0530     omap_aes_finish_req(dd, 0);
0531 
0532     pr_debug("exit\n");
0533 }
0534 
0535 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode)
0536 {
0537     struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
0538             crypto_skcipher_reqtfm(req));
0539     struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
0540     struct omap_aes_dev *dd;
0541     int ret;
0542 
0543     if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR))
0544         return -EINVAL;
0545 
0546     pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
0547           !!(mode & FLAGS_ENCRYPT),
0548           !!(mode & FLAGS_CBC));
0549 
0550     if (req->cryptlen < aes_fallback_sz) {
0551         skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
0552         skcipher_request_set_callback(&rctx->fallback_req,
0553                           req->base.flags,
0554                           req->base.complete,
0555                           req->base.data);
0556         skcipher_request_set_crypt(&rctx->fallback_req, req->src,
0557                        req->dst, req->cryptlen, req->iv);
0558 
0559         if (mode & FLAGS_ENCRYPT)
0560             ret = crypto_skcipher_encrypt(&rctx->fallback_req);
0561         else
0562             ret = crypto_skcipher_decrypt(&rctx->fallback_req);
0563         return ret;
0564     }
0565     dd = omap_aes_find_dev(rctx);
0566     if (!dd)
0567         return -ENODEV;
0568 
0569     rctx->mode = mode;
0570 
0571     return omap_aes_handle_queue(dd, req);
0572 }
0573 
0574 /* ********************** ALG API ************************************ */
0575 
0576 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
0577                unsigned int keylen)
0578 {
0579     struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
0580     int ret;
0581 
0582     if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
0583            keylen != AES_KEYSIZE_256)
0584         return -EINVAL;
0585 
0586     pr_debug("enter, keylen: %d\n", keylen);
0587 
0588     memcpy(ctx->key, key, keylen);
0589     ctx->keylen = keylen;
0590 
0591     crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
0592     crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
0593                          CRYPTO_TFM_REQ_MASK);
0594 
0595     ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
0596     if (!ret)
0597         return 0;
0598 
0599     return 0;
0600 }
0601 
0602 static int omap_aes_ecb_encrypt(struct skcipher_request *req)
0603 {
0604     return omap_aes_crypt(req, FLAGS_ENCRYPT);
0605 }
0606 
0607 static int omap_aes_ecb_decrypt(struct skcipher_request *req)
0608 {
0609     return omap_aes_crypt(req, 0);
0610 }
0611 
0612 static int omap_aes_cbc_encrypt(struct skcipher_request *req)
0613 {
0614     return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
0615 }
0616 
0617 static int omap_aes_cbc_decrypt(struct skcipher_request *req)
0618 {
0619     return omap_aes_crypt(req, FLAGS_CBC);
0620 }
0621 
0622 static int omap_aes_ctr_encrypt(struct skcipher_request *req)
0623 {
0624     return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
0625 }
0626 
0627 static int omap_aes_ctr_decrypt(struct skcipher_request *req)
0628 {
0629     return omap_aes_crypt(req, FLAGS_CTR);
0630 }
0631 
0632 static int omap_aes_prepare_req(struct crypto_engine *engine,
0633                 void *req);
0634 static int omap_aes_crypt_req(struct crypto_engine *engine,
0635                   void *req);
0636 
0637 static int omap_aes_init_tfm(struct crypto_skcipher *tfm)
0638 {
0639     const char *name = crypto_tfm_alg_name(&tfm->base);
0640     struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
0641     struct crypto_skcipher *blk;
0642 
0643     blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
0644     if (IS_ERR(blk))
0645         return PTR_ERR(blk);
0646 
0647     ctx->fallback = blk;
0648 
0649     crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) +
0650                      crypto_skcipher_reqsize(blk));
0651 
0652     ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
0653     ctx->enginectx.op.unprepare_request = NULL;
0654     ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
0655 
0656     return 0;
0657 }
0658 
0659 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm)
0660 {
0661     struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
0662 
0663     if (ctx->fallback)
0664         crypto_free_skcipher(ctx->fallback);
0665 
0666     ctx->fallback = NULL;
0667 }
0668 
0669 /* ********************** ALGS ************************************ */
0670 
0671 static struct skcipher_alg algs_ecb_cbc[] = {
0672 {
0673     .base.cra_name      = "ecb(aes)",
0674     .base.cra_driver_name   = "ecb-aes-omap",
0675     .base.cra_priority  = 300,
0676     .base.cra_flags     = CRYPTO_ALG_KERN_DRIVER_ONLY |
0677                   CRYPTO_ALG_ASYNC |
0678                   CRYPTO_ALG_NEED_FALLBACK,
0679     .base.cra_blocksize = AES_BLOCK_SIZE,
0680     .base.cra_ctxsize   = sizeof(struct omap_aes_ctx),
0681     .base.cra_module    = THIS_MODULE,
0682 
0683     .min_keysize        = AES_MIN_KEY_SIZE,
0684     .max_keysize        = AES_MAX_KEY_SIZE,
0685     .setkey         = omap_aes_setkey,
0686     .encrypt        = omap_aes_ecb_encrypt,
0687     .decrypt        = omap_aes_ecb_decrypt,
0688     .init           = omap_aes_init_tfm,
0689     .exit           = omap_aes_exit_tfm,
0690 },
0691 {
0692     .base.cra_name      = "cbc(aes)",
0693     .base.cra_driver_name   = "cbc-aes-omap",
0694     .base.cra_priority  = 300,
0695     .base.cra_flags     = CRYPTO_ALG_KERN_DRIVER_ONLY |
0696                   CRYPTO_ALG_ASYNC |
0697                   CRYPTO_ALG_NEED_FALLBACK,
0698     .base.cra_blocksize = AES_BLOCK_SIZE,
0699     .base.cra_ctxsize   = sizeof(struct omap_aes_ctx),
0700     .base.cra_module    = THIS_MODULE,
0701 
0702     .min_keysize        = AES_MIN_KEY_SIZE,
0703     .max_keysize        = AES_MAX_KEY_SIZE,
0704     .ivsize         = AES_BLOCK_SIZE,
0705     .setkey         = omap_aes_setkey,
0706     .encrypt        = omap_aes_cbc_encrypt,
0707     .decrypt        = omap_aes_cbc_decrypt,
0708     .init           = omap_aes_init_tfm,
0709     .exit           = omap_aes_exit_tfm,
0710 }
0711 };
0712 
0713 static struct skcipher_alg algs_ctr[] = {
0714 {
0715     .base.cra_name      = "ctr(aes)",
0716     .base.cra_driver_name   = "ctr-aes-omap",
0717     .base.cra_priority  = 300,
0718     .base.cra_flags     = CRYPTO_ALG_KERN_DRIVER_ONLY |
0719                   CRYPTO_ALG_ASYNC |
0720                   CRYPTO_ALG_NEED_FALLBACK,
0721     .base.cra_blocksize = 1,
0722     .base.cra_ctxsize   = sizeof(struct omap_aes_ctx),
0723     .base.cra_module    = THIS_MODULE,
0724 
0725     .min_keysize        = AES_MIN_KEY_SIZE,
0726     .max_keysize        = AES_MAX_KEY_SIZE,
0727     .ivsize         = AES_BLOCK_SIZE,
0728     .setkey         = omap_aes_setkey,
0729     .encrypt        = omap_aes_ctr_encrypt,
0730     .decrypt        = omap_aes_ctr_decrypt,
0731     .init           = omap_aes_init_tfm,
0732     .exit           = omap_aes_exit_tfm,
0733 }
0734 };
0735 
0736 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
0737     {
0738         .algs_list  = algs_ecb_cbc,
0739         .size       = ARRAY_SIZE(algs_ecb_cbc),
0740     },
0741 };
0742 
0743 static struct aead_alg algs_aead_gcm[] = {
0744 {
0745     .base = {
0746         .cra_name       = "gcm(aes)",
0747         .cra_driver_name    = "gcm-aes-omap",
0748         .cra_priority       = 300,
0749         .cra_flags      = CRYPTO_ALG_ASYNC |
0750                       CRYPTO_ALG_KERN_DRIVER_ONLY,
0751         .cra_blocksize      = 1,
0752         .cra_ctxsize        = sizeof(struct omap_aes_gcm_ctx),
0753         .cra_alignmask      = 0xf,
0754         .cra_module     = THIS_MODULE,
0755     },
0756     .init       = omap_aes_gcm_cra_init,
0757     .ivsize     = GCM_AES_IV_SIZE,
0758     .maxauthsize    = AES_BLOCK_SIZE,
0759     .setkey     = omap_aes_gcm_setkey,
0760     .setauthsize    = omap_aes_gcm_setauthsize,
0761     .encrypt    = omap_aes_gcm_encrypt,
0762     .decrypt    = omap_aes_gcm_decrypt,
0763 },
0764 {
0765     .base = {
0766         .cra_name       = "rfc4106(gcm(aes))",
0767         .cra_driver_name    = "rfc4106-gcm-aes-omap",
0768         .cra_priority       = 300,
0769         .cra_flags      = CRYPTO_ALG_ASYNC |
0770                       CRYPTO_ALG_KERN_DRIVER_ONLY,
0771         .cra_blocksize      = 1,
0772         .cra_ctxsize        = sizeof(struct omap_aes_gcm_ctx),
0773         .cra_alignmask      = 0xf,
0774         .cra_module     = THIS_MODULE,
0775     },
0776     .init       = omap_aes_gcm_cra_init,
0777     .maxauthsize    = AES_BLOCK_SIZE,
0778     .ivsize     = GCM_RFC4106_IV_SIZE,
0779     .setkey     = omap_aes_4106gcm_setkey,
0780     .setauthsize    = omap_aes_4106gcm_setauthsize,
0781     .encrypt    = omap_aes_4106gcm_encrypt,
0782     .decrypt    = omap_aes_4106gcm_decrypt,
0783 },
0784 };
0785 
0786 static struct omap_aes_aead_algs omap_aes_aead_info = {
0787     .algs_list  =   algs_aead_gcm,
0788     .size       =   ARRAY_SIZE(algs_aead_gcm),
0789 };
0790 
0791 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
0792     .algs_info  = omap_aes_algs_info_ecb_cbc,
0793     .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
0794     .trigger    = omap_aes_dma_trigger_omap2,
0795     .key_ofs    = 0x1c,
0796     .iv_ofs     = 0x20,
0797     .ctrl_ofs   = 0x30,
0798     .data_ofs   = 0x34,
0799     .rev_ofs    = 0x44,
0800     .mask_ofs   = 0x48,
0801     .dma_enable_in  = BIT(2),
0802     .dma_enable_out = BIT(3),
0803     .dma_start  = BIT(5),
0804     .major_mask = 0xf0,
0805     .major_shift    = 4,
0806     .minor_mask = 0x0f,
0807     .minor_shift    = 0,
0808 };
0809 
0810 #ifdef CONFIG_OF
0811 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
0812     {
0813         .algs_list  = algs_ecb_cbc,
0814         .size       = ARRAY_SIZE(algs_ecb_cbc),
0815     },
0816     {
0817         .algs_list  = algs_ctr,
0818         .size       = ARRAY_SIZE(algs_ctr),
0819     },
0820 };
0821 
0822 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
0823     .algs_info  = omap_aes_algs_info_ecb_cbc_ctr,
0824     .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
0825     .trigger    = omap_aes_dma_trigger_omap2,
0826     .key_ofs    = 0x1c,
0827     .iv_ofs     = 0x20,
0828     .ctrl_ofs   = 0x30,
0829     .data_ofs   = 0x34,
0830     .rev_ofs    = 0x44,
0831     .mask_ofs   = 0x48,
0832     .dma_enable_in  = BIT(2),
0833     .dma_enable_out = BIT(3),
0834     .dma_start  = BIT(5),
0835     .major_mask = 0xf0,
0836     .major_shift    = 4,
0837     .minor_mask = 0x0f,
0838     .minor_shift    = 0,
0839 };
0840 
0841 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
0842     .algs_info  = omap_aes_algs_info_ecb_cbc_ctr,
0843     .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
0844     .aead_algs_info = &omap_aes_aead_info,
0845     .trigger    = omap_aes_dma_trigger_omap4,
0846     .key_ofs    = 0x3c,
0847     .iv_ofs     = 0x40,
0848     .ctrl_ofs   = 0x50,
0849     .data_ofs   = 0x60,
0850     .rev_ofs    = 0x80,
0851     .mask_ofs   = 0x84,
0852     .irq_status_ofs = 0x8c,
0853     .irq_enable_ofs = 0x90,
0854     .dma_enable_in  = BIT(5),
0855     .dma_enable_out = BIT(6),
0856     .major_mask = 0x0700,
0857     .major_shift    = 8,
0858     .minor_mask = 0x003f,
0859     .minor_shift    = 0,
0860 };
0861 
0862 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
0863 {
0864     struct omap_aes_dev *dd = dev_id;
0865     u32 status, i;
0866     u32 *src, *dst;
0867 
0868     status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
0869     if (status & AES_REG_IRQ_DATA_IN) {
0870         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
0871 
0872         BUG_ON(!dd->in_sg);
0873 
0874         BUG_ON(_calc_walked(in) > dd->in_sg->length);
0875 
0876         src = sg_virt(dd->in_sg) + _calc_walked(in);
0877 
0878         for (i = 0; i < AES_BLOCK_WORDS; i++) {
0879             omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
0880 
0881             scatterwalk_advance(&dd->in_walk, 4);
0882             if (dd->in_sg->length == _calc_walked(in)) {
0883                 dd->in_sg = sg_next(dd->in_sg);
0884                 if (dd->in_sg) {
0885                     scatterwalk_start(&dd->in_walk,
0886                               dd->in_sg);
0887                     src = sg_virt(dd->in_sg) +
0888                           _calc_walked(in);
0889                 }
0890             } else {
0891                 src++;
0892             }
0893         }
0894 
0895         /* Clear IRQ status */
0896         status &= ~AES_REG_IRQ_DATA_IN;
0897         omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
0898 
0899         /* Enable DATA_OUT interrupt */
0900         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
0901 
0902     } else if (status & AES_REG_IRQ_DATA_OUT) {
0903         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
0904 
0905         BUG_ON(!dd->out_sg);
0906 
0907         BUG_ON(_calc_walked(out) > dd->out_sg->length);
0908 
0909         dst = sg_virt(dd->out_sg) + _calc_walked(out);
0910 
0911         for (i = 0; i < AES_BLOCK_WORDS; i++) {
0912             *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
0913             scatterwalk_advance(&dd->out_walk, 4);
0914             if (dd->out_sg->length == _calc_walked(out)) {
0915                 dd->out_sg = sg_next(dd->out_sg);
0916                 if (dd->out_sg) {
0917                     scatterwalk_start(&dd->out_walk,
0918                               dd->out_sg);
0919                     dst = sg_virt(dd->out_sg) +
0920                           _calc_walked(out);
0921                 }
0922             } else {
0923                 dst++;
0924             }
0925         }
0926 
0927         dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
0928 
0929         /* Clear IRQ status */
0930         status &= ~AES_REG_IRQ_DATA_OUT;
0931         omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
0932 
0933         if (!dd->total)
0934             /* All bytes read! */
0935             tasklet_schedule(&dd->done_task);
0936         else
0937             /* Enable DATA_IN interrupt for next block */
0938             omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
0939     }
0940 
0941     return IRQ_HANDLED;
0942 }
0943 
0944 static const struct of_device_id omap_aes_of_match[] = {
0945     {
0946         .compatible = "ti,omap2-aes",
0947         .data       = &omap_aes_pdata_omap2,
0948     },
0949     {
0950         .compatible = "ti,omap3-aes",
0951         .data       = &omap_aes_pdata_omap3,
0952     },
0953     {
0954         .compatible = "ti,omap4-aes",
0955         .data       = &omap_aes_pdata_omap4,
0956     },
0957     {},
0958 };
0959 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
0960 
0961 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
0962         struct device *dev, struct resource *res)
0963 {
0964     struct device_node *node = dev->of_node;
0965     int err = 0;
0966 
0967     dd->pdata = of_device_get_match_data(dev);
0968     if (!dd->pdata) {
0969         dev_err(dev, "no compatible OF match\n");
0970         err = -EINVAL;
0971         goto err;
0972     }
0973 
0974     err = of_address_to_resource(node, 0, res);
0975     if (err < 0) {
0976         dev_err(dev, "can't translate OF node address\n");
0977         err = -EINVAL;
0978         goto err;
0979     }
0980 
0981 err:
0982     return err;
0983 }
0984 #else
0985 static const struct of_device_id omap_aes_of_match[] = {
0986     {},
0987 };
0988 
0989 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
0990         struct device *dev, struct resource *res)
0991 {
0992     return -EINVAL;
0993 }
0994 #endif
0995 
0996 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
0997         struct platform_device *pdev, struct resource *res)
0998 {
0999     struct device *dev = &pdev->dev;
1000     struct resource *r;
1001     int err = 0;
1002 
1003     /* Get the base address */
1004     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1005     if (!r) {
1006         dev_err(dev, "no MEM resource info\n");
1007         err = -ENODEV;
1008         goto err;
1009     }
1010     memcpy(res, r, sizeof(*res));
1011 
1012     /* Only OMAP2/3 can be non-DT */
1013     dd->pdata = &omap_aes_pdata_omap2;
1014 
1015 err:
1016     return err;
1017 }
1018 
1019 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1020                  char *buf)
1021 {
1022     return sprintf(buf, "%d\n", aes_fallback_sz);
1023 }
1024 
1025 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1026                   const char *buf, size_t size)
1027 {
1028     ssize_t status;
1029     long value;
1030 
1031     status = kstrtol(buf, 0, &value);
1032     if (status)
1033         return status;
1034 
1035     /* HW accelerator only works with buffers > 9 */
1036     if (value < 9) {
1037         dev_err(dev, "minimum fallback size 9\n");
1038         return -EINVAL;
1039     }
1040 
1041     aes_fallback_sz = value;
1042 
1043     return size;
1044 }
1045 
1046 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1047                   char *buf)
1048 {
1049     struct omap_aes_dev *dd = dev_get_drvdata(dev);
1050 
1051     return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1052 }
1053 
1054 static ssize_t queue_len_store(struct device *dev,
1055                    struct device_attribute *attr, const char *buf,
1056                    size_t size)
1057 {
1058     struct omap_aes_dev *dd;
1059     ssize_t status;
1060     long value;
1061     unsigned long flags;
1062 
1063     status = kstrtol(buf, 0, &value);
1064     if (status)
1065         return status;
1066 
1067     if (value < 1)
1068         return -EINVAL;
1069 
1070     /*
1071      * Changing the queue size in fly is safe, if size becomes smaller
1072      * than current size, it will just not accept new entries until
1073      * it has shrank enough.
1074      */
1075     spin_lock_bh(&list_lock);
1076     list_for_each_entry(dd, &dev_list, list) {
1077         spin_lock_irqsave(&dd->lock, flags);
1078         dd->engine->queue.max_qlen = value;
1079         dd->aead_queue.base.max_qlen = value;
1080         spin_unlock_irqrestore(&dd->lock, flags);
1081     }
1082     spin_unlock_bh(&list_lock);
1083 
1084     return size;
1085 }
1086 
1087 static DEVICE_ATTR_RW(queue_len);
1088 static DEVICE_ATTR_RW(fallback);
1089 
1090 static struct attribute *omap_aes_attrs[] = {
1091     &dev_attr_queue_len.attr,
1092     &dev_attr_fallback.attr,
1093     NULL,
1094 };
1095 
1096 static const struct attribute_group omap_aes_attr_group = {
1097     .attrs = omap_aes_attrs,
1098 };
1099 
1100 static int omap_aes_probe(struct platform_device *pdev)
1101 {
1102     struct device *dev = &pdev->dev;
1103     struct omap_aes_dev *dd;
1104     struct skcipher_alg *algp;
1105     struct aead_alg *aalg;
1106     struct resource res;
1107     int err = -ENOMEM, i, j, irq = -1;
1108     u32 reg;
1109 
1110     dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1111     if (dd == NULL) {
1112         dev_err(dev, "unable to alloc data struct.\n");
1113         goto err_data;
1114     }
1115     dd->dev = dev;
1116     platform_set_drvdata(pdev, dd);
1117 
1118     aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1119 
1120     err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1121                    omap_aes_get_res_pdev(dd, pdev, &res);
1122     if (err)
1123         goto err_res;
1124 
1125     dd->io_base = devm_ioremap_resource(dev, &res);
1126     if (IS_ERR(dd->io_base)) {
1127         err = PTR_ERR(dd->io_base);
1128         goto err_res;
1129     }
1130     dd->phys_base = res.start;
1131 
1132     pm_runtime_use_autosuspend(dev);
1133     pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1134 
1135     pm_runtime_enable(dev);
1136     err = pm_runtime_resume_and_get(dev);
1137     if (err < 0) {
1138         dev_err(dev, "%s: failed to get_sync(%d)\n",
1139             __func__, err);
1140         goto err_pm_disable;
1141     }
1142 
1143     omap_aes_dma_stop(dd);
1144 
1145     reg = omap_aes_read(dd, AES_REG_REV(dd));
1146 
1147     pm_runtime_put_sync(dev);
1148 
1149     dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1150          (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1151          (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1152 
1153     tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1154 
1155     err = omap_aes_dma_init(dd);
1156     if (err == -EPROBE_DEFER) {
1157         goto err_irq;
1158     } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1159         dd->pio_only = 1;
1160 
1161         irq = platform_get_irq(pdev, 0);
1162         if (irq < 0) {
1163             err = irq;
1164             goto err_irq;
1165         }
1166 
1167         err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1168                 dev_name(dev), dd);
1169         if (err) {
1170             dev_err(dev, "Unable to grab omap-aes IRQ\n");
1171             goto err_irq;
1172         }
1173     }
1174 
1175     spin_lock_init(&dd->lock);
1176 
1177     INIT_LIST_HEAD(&dd->list);
1178     spin_lock_bh(&list_lock);
1179     list_add_tail(&dd->list, &dev_list);
1180     spin_unlock_bh(&list_lock);
1181 
1182     /* Initialize crypto engine */
1183     dd->engine = crypto_engine_alloc_init(dev, 1);
1184     if (!dd->engine) {
1185         err = -ENOMEM;
1186         goto err_engine;
1187     }
1188 
1189     err = crypto_engine_start(dd->engine);
1190     if (err)
1191         goto err_engine;
1192 
1193     for (i = 0; i < dd->pdata->algs_info_size; i++) {
1194         if (!dd->pdata->algs_info[i].registered) {
1195             for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1196                 algp = &dd->pdata->algs_info[i].algs_list[j];
1197 
1198                 pr_debug("reg alg: %s\n", algp->base.cra_name);
1199 
1200                 err = crypto_register_skcipher(algp);
1201                 if (err)
1202                     goto err_algs;
1203 
1204                 dd->pdata->algs_info[i].registered++;
1205             }
1206         }
1207     }
1208 
1209     if (dd->pdata->aead_algs_info &&
1210         !dd->pdata->aead_algs_info->registered) {
1211         for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1212             aalg = &dd->pdata->aead_algs_info->algs_list[i];
1213 
1214             pr_debug("reg alg: %s\n", aalg->base.cra_name);
1215 
1216             err = crypto_register_aead(aalg);
1217             if (err)
1218                 goto err_aead_algs;
1219 
1220             dd->pdata->aead_algs_info->registered++;
1221         }
1222     }
1223 
1224     err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
1225     if (err) {
1226         dev_err(dev, "could not create sysfs device attrs\n");
1227         goto err_aead_algs;
1228     }
1229 
1230     return 0;
1231 err_aead_algs:
1232     for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1233         aalg = &dd->pdata->aead_algs_info->algs_list[i];
1234         crypto_unregister_aead(aalg);
1235     }
1236 err_algs:
1237     for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1238         for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1239             crypto_unregister_skcipher(
1240                     &dd->pdata->algs_info[i].algs_list[j]);
1241 
1242 err_engine:
1243     if (dd->engine)
1244         crypto_engine_exit(dd->engine);
1245 
1246     omap_aes_dma_cleanup(dd);
1247 err_irq:
1248     tasklet_kill(&dd->done_task);
1249 err_pm_disable:
1250     pm_runtime_disable(dev);
1251 err_res:
1252     dd = NULL;
1253 err_data:
1254     dev_err(dev, "initialization failed.\n");
1255     return err;
1256 }
1257 
1258 static int omap_aes_remove(struct platform_device *pdev)
1259 {
1260     struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1261     struct aead_alg *aalg;
1262     int i, j;
1263 
1264     spin_lock_bh(&list_lock);
1265     list_del(&dd->list);
1266     spin_unlock_bh(&list_lock);
1267 
1268     for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1269         for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
1270             crypto_unregister_skcipher(
1271                     &dd->pdata->algs_info[i].algs_list[j]);
1272             dd->pdata->algs_info[i].registered--;
1273         }
1274 
1275     for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1276         aalg = &dd->pdata->aead_algs_info->algs_list[i];
1277         crypto_unregister_aead(aalg);
1278         dd->pdata->aead_algs_info->registered--;
1279     }
1280 
1281     crypto_engine_exit(dd->engine);
1282 
1283     tasklet_kill(&dd->done_task);
1284     omap_aes_dma_cleanup(dd);
1285     pm_runtime_disable(dd->dev);
1286 
1287     sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group);
1288 
1289     return 0;
1290 }
1291 
1292 #ifdef CONFIG_PM_SLEEP
1293 static int omap_aes_suspend(struct device *dev)
1294 {
1295     pm_runtime_put_sync(dev);
1296     return 0;
1297 }
1298 
1299 static int omap_aes_resume(struct device *dev)
1300 {
1301     pm_runtime_get_sync(dev);
1302     return 0;
1303 }
1304 #endif
1305 
1306 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1307 
1308 static struct platform_driver omap_aes_driver = {
1309     .probe  = omap_aes_probe,
1310     .remove = omap_aes_remove,
1311     .driver = {
1312         .name   = "omap-aes",
1313         .pm = &omap_aes_pm_ops,
1314         .of_match_table = omap_aes_of_match,
1315     },
1316 };
1317 
1318 module_platform_driver(omap_aes_driver);
1319 
1320 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1321 MODULE_LICENSE("GPL v2");
1322 MODULE_AUTHOR("Dmitry Kasatkin");
1323
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