drivers/crypto/n2_core.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _N2_CORE_H
0003 #define _N2_CORE_H
0004
0005 #ifndef __ASSEMBLY__
0006
0007 struct ino_blob {
0008     u64         intr;
0009     u64         ino;
0010 };
0011
0012 struct spu_mdesc_info {
0013     u64         cfg_handle;
0014     struct ino_blob     *ino_table;
0015     int         num_intrs;
0016 };
0017
0018 struct n2_crypto {
0019     struct spu_mdesc_info   cwq_info;
0020     struct list_head    cwq_list;
0021 };
0022
0023 struct n2_mau {
0024     struct spu_mdesc_info   mau_info;
0025     struct list_head    mau_list;
0026 };
0027
0028 #define CWQ_ENTRY_SIZE      64
0029 #define CWQ_NUM_ENTRIES     64
0030
0031 #define MAU_ENTRY_SIZE      64
0032 #define MAU_NUM_ENTRIES     64
0033
0034 struct cwq_initial_entry {
0035     u64         control;
0036     u64         src_addr;
0037     u64         auth_key_addr;
0038     u64         auth_iv_addr;
0039     u64         final_auth_state_addr;
0040     u64         enc_key_addr;
0041     u64         enc_iv_addr;
0042     u64         dest_addr;
0043 };
0044
0045 struct cwq_ext_entry {
0046     u64         len;
0047     u64         src_addr;
0048     u64         resv1;
0049     u64         resv2;
0050     u64         resv3;
0051     u64         resv4;
0052     u64         resv5;
0053     u64         resv6;
0054 };
0055
0056 struct cwq_final_entry {
0057     u64         control;
0058     u64         src_addr;
0059     u64         resv1;
0060     u64         resv2;
0061     u64         resv3;
0062     u64         resv4;
0063     u64         resv5;
0064     u64         resv6;
0065 };
0066
0067 #define CONTROL_LEN         0x000000000000ffffULL
0068 #define CONTROL_LEN_SHIFT       0
0069 #define CONTROL_HMAC_KEY_LEN        0x0000000000ff0000ULL
0070 #define CONTROL_HMAC_KEY_LEN_SHIFT  16
0071 #define CONTROL_ENC_TYPE        0x00000000ff000000ULL
0072 #define CONTROL_ENC_TYPE_SHIFT      24
0073 #define  ENC_TYPE_ALG_RC4_STREAM    0x00ULL
0074 #define  ENC_TYPE_ALG_RC4_NOSTREAM  0x04ULL
0075 #define  ENC_TYPE_ALG_DES       0x08ULL
0076 #define  ENC_TYPE_ALG_3DES      0x0cULL
0077 #define  ENC_TYPE_ALG_AES128        0x10ULL
0078 #define  ENC_TYPE_ALG_AES192        0x14ULL
0079 #define  ENC_TYPE_ALG_AES256        0x18ULL
0080 #define  ENC_TYPE_ALG_RESERVED      0x1cULL
0081 #define  ENC_TYPE_ALG_MASK      0x1cULL
0082 #define  ENC_TYPE_CHAINING_ECB      0x00ULL
0083 #define  ENC_TYPE_CHAINING_CBC      0x01ULL
0084 #define  ENC_TYPE_CHAINING_CFB      0x02ULL
0085 #define  ENC_TYPE_CHAINING_COUNTER  0x03ULL
0086 #define  ENC_TYPE_CHAINING_MASK     0x03ULL
0087 #define CONTROL_AUTH_TYPE       0x0000001f00000000ULL
0088 #define CONTROL_AUTH_TYPE_SHIFT     32
0089 #define  AUTH_TYPE_RESERVED     0x00ULL
0090 #define  AUTH_TYPE_MD5          0x01ULL
0091 #define  AUTH_TYPE_SHA1         0x02ULL
0092 #define  AUTH_TYPE_SHA256       0x03ULL
0093 #define  AUTH_TYPE_CRC32        0x04ULL
0094 #define  AUTH_TYPE_HMAC_MD5     0x05ULL
0095 #define  AUTH_TYPE_HMAC_SHA1        0x06ULL
0096 #define  AUTH_TYPE_HMAC_SHA256      0x07ULL
0097 #define  AUTH_TYPE_TCP_CHECKSUM     0x08ULL
0098 #define  AUTH_TYPE_SSL_HMAC_MD5     0x09ULL
0099 #define  AUTH_TYPE_SSL_HMAC_SHA1    0x0aULL
0100 #define  AUTH_TYPE_SSL_HMAC_SHA256  0x0bULL
0101 #define CONTROL_STRAND          0x000000e000000000ULL
0102 #define CONTROL_STRAND_SHIFT        37
0103 #define CONTROL_HASH_LEN        0x0000ff0000000000ULL
0104 #define CONTROL_HASH_LEN_SHIFT      40
0105 #define CONTROL_INTERRUPT       0x0001000000000000ULL
0106 #define CONTROL_STORE_FINAL_AUTH_STATE  0x0002000000000000ULL
0107 #define CONTROL_RESERVED        0x001c000000000000ULL
0108 #define CONTROL_HV_DONE         0x0004000000000000ULL
0109 #define CONTROL_HV_PROTOCOL_ERROR   0x0008000000000000ULL
0110 #define CONTROL_HV_HARDWARE_ERROR   0x0010000000000000ULL
0111 #define CONTROL_END_OF_BLOCK        0x0020000000000000ULL
0112 #define CONTROL_START_OF_BLOCK      0x0040000000000000ULL
0113 #define CONTROL_ENCRYPT         0x0080000000000000ULL
0114 #define CONTROL_OPCODE          0xff00000000000000ULL
0115 #define CONTROL_OPCODE_SHIFT        56
0116 #define  OPCODE_INPLACE_BIT     0x80ULL
0117 #define  OPCODE_SSL_KEYBLOCK        0x10ULL
0118 #define  OPCODE_COPY            0x20ULL
0119 #define  OPCODE_ENCRYPT         0x40ULL
0120 #define  OPCODE_AUTH_MAC        0x41ULL
0121
0122 #endif /* !(__ASSEMBLY__) */
0123
0124 /* NCS v2.0 hypervisor interfaces */
0125 #define HV_NCS_QTYPE_MAU        0x01
0126 #define HV_NCS_QTYPE_CWQ        0x02
0127
0128 /* ncs_qconf()
0129  * TRAP:    HV_FAST_TRAP
0130  * FUNCTION:    HV_FAST_NCS_QCONF
0131  * ARG0:    Queue type (HV_NCS_QTYPE_{MAU,CWQ})
0132  * ARG1:    Real address of queue, or handle for unconfigure
0133  * ARG2:    Number of entries in queue, zero for unconfigure
0134  * RET0:    status
0135  * RET1:    queue handle
0136  *
0137  * Configure a queue in the stream processing unit.
0138  *
0139  * The real address given as the base must be 64-byte
0140  * aligned.
0141  *
0142  * The queue size can range from a minimum of 2 to a maximum
0143  * of 64.  The queue size must be a power of two.
0144  *
0145  * To unconfigure a queue, specify a length of zero and place
0146  * the queue handle into ARG1.
0147  *
0148  * On configure success the hypervisor will set the FIRST, HEAD,
0149  * and TAIL registers to the address of the first entry in the
0150  * queue.  The LAST register will be set to point to the last
0151  * entry in the queue.
0152  */
0153 #define HV_FAST_NCS_QCONF       0x111
0154
0155 /* ncs_qinfo()
0156  * TRAP:    HV_FAST_TRAP
0157  * FUNCTION:    HV_FAST_NCS_QINFO
0158  * ARG0:    Queue handle
0159  * RET0:    status
0160  * RET1:    Queue type (HV_NCS_QTYPE_{MAU,CWQ})
0161  * RET2:    Queue base address
0162  * RET3:    Number of entries
0163  */
0164 #define HV_FAST_NCS_QINFO       0x112
0165
0166 /* ncs_gethead()
0167  * TRAP:    HV_FAST_TRAP
0168  * FUNCTION:    HV_FAST_NCS_GETHEAD
0169  * ARG0:    Queue handle
0170  * RET0:    status
0171  * RET1:    queue head offset
0172  */
0173 #define HV_FAST_NCS_GETHEAD     0x113
0174
0175 /* ncs_gettail()
0176  * TRAP:    HV_FAST_TRAP
0177  * FUNCTION:    HV_FAST_NCS_GETTAIL
0178  * ARG0:    Queue handle
0179  * RET0:    status
0180  * RET1:    queue tail offset
0181  */
0182 #define HV_FAST_NCS_GETTAIL     0x114
0183
0184 /* ncs_settail()
0185  * TRAP:    HV_FAST_TRAP
0186  * FUNCTION:    HV_FAST_NCS_SETTAIL
0187  * ARG0:    Queue handle
0188  * ARG1:    New tail offset
0189  * RET0:    status
0190  */
0191 #define HV_FAST_NCS_SETTAIL     0x115
0192
0193 /* ncs_qhandle_to_devino()
0194  * TRAP:    HV_FAST_TRAP
0195  * FUNCTION:    HV_FAST_NCS_QHANDLE_TO_DEVINO
0196  * ARG0:    Queue handle
0197  * RET0:    status
0198  * RET1:    devino
0199  */
0200 #define HV_FAST_NCS_QHANDLE_TO_DEVINO   0x116
0201
0202 /* ncs_sethead_marker()
0203  * TRAP:    HV_FAST_TRAP
0204  * FUNCTION:    HV_FAST_NCS_SETHEAD_MARKER
0205  * ARG0:    Queue handle
0206  * ARG1:    New head offset
0207  * RET0:    status
0208  */
0209 #define HV_FAST_NCS_SETHEAD_MARKER  0x117
0210
0211 #ifndef __ASSEMBLY__
0212 extern unsigned long sun4v_ncs_qconf(unsigned long queue_type,
0213                      unsigned long queue_ra,
0214                      unsigned long num_entries,
0215                      unsigned long *qhandle);
0216 extern unsigned long sun4v_ncs_qinfo(unsigned long qhandle,
0217                      unsigned long *queue_type,
0218                      unsigned long *queue_ra,
0219                      unsigned long *num_entries);
0220 extern unsigned long sun4v_ncs_gethead(unsigned long qhandle,
0221                        unsigned long *head);
0222 extern unsigned long sun4v_ncs_gettail(unsigned long qhandle,
0223                        unsigned long *tail);
0224 extern unsigned long sun4v_ncs_settail(unsigned long qhandle,
0225                        unsigned long tail);
0226 extern unsigned long sun4v_ncs_qhandle_to_devino(unsigned long qhandle,
0227                          unsigned long *devino);
0228 extern unsigned long sun4v_ncs_sethead_marker(unsigned long qhandle,
0229                           unsigned long head);
0230 #endif /* !(__ASSEMBLY__) */
0231
0232 #endif /* _N2_CORE_H */