Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale i.MX23/i.MX28 Data Co-Processor driver
0004  *
0005  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
0006  */
0007 
0008 #include <linux/dma-mapping.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/kthread.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/stmp_device.h>
0017 #include <linux/clk.h>
0018 
0019 #include <crypto/aes.h>
0020 #include <crypto/sha1.h>
0021 #include <crypto/sha2.h>
0022 #include <crypto/internal/hash.h>
0023 #include <crypto/internal/skcipher.h>
0024 #include <crypto/scatterwalk.h>
0025 
0026 #define DCP_MAX_CHANS   4
0027 #define DCP_BUF_SZ  PAGE_SIZE
0028 #define DCP_SHA_PAY_SZ  64
0029 
0030 #define DCP_ALIGNMENT   64
0031 
0032 /*
0033  * Null hashes to align with hw behavior on imx6sl and ull
0034  * these are flipped for consistency with hw output
0035  */
0036 static const uint8_t sha1_null_hash[] =
0037     "\x09\x07\xd8\xaf\x90\x18\x60\x95\xef\xbf"
0038     "\x55\x32\x0d\x4b\x6b\x5e\xee\xa3\x39\xda";
0039 
0040 static const uint8_t sha256_null_hash[] =
0041     "\x55\xb8\x52\x78\x1b\x99\x95\xa4"
0042     "\x4c\x93\x9b\x64\xe4\x41\xae\x27"
0043     "\x24\xb9\x6f\x99\xc8\xf4\xfb\x9a"
0044     "\x14\x1c\xfc\x98\x42\xc4\xb0\xe3";
0045 
0046 /* DCP DMA descriptor. */
0047 struct dcp_dma_desc {
0048     uint32_t    next_cmd_addr;
0049     uint32_t    control0;
0050     uint32_t    control1;
0051     uint32_t    source;
0052     uint32_t    destination;
0053     uint32_t    size;
0054     uint32_t    payload;
0055     uint32_t    status;
0056 };
0057 
0058 /* Coherent aligned block for bounce buffering. */
0059 struct dcp_coherent_block {
0060     uint8_t         aes_in_buf[DCP_BUF_SZ];
0061     uint8_t         aes_out_buf[DCP_BUF_SZ];
0062     uint8_t         sha_in_buf[DCP_BUF_SZ];
0063     uint8_t         sha_out_buf[DCP_SHA_PAY_SZ];
0064 
0065     uint8_t         aes_key[2 * AES_KEYSIZE_128];
0066 
0067     struct dcp_dma_desc desc[DCP_MAX_CHANS];
0068 };
0069 
0070 struct dcp {
0071     struct device           *dev;
0072     void __iomem            *base;
0073 
0074     uint32_t            caps;
0075 
0076     struct dcp_coherent_block   *coh;
0077 
0078     struct completion       completion[DCP_MAX_CHANS];
0079     spinlock_t          lock[DCP_MAX_CHANS];
0080     struct task_struct      *thread[DCP_MAX_CHANS];
0081     struct crypto_queue     queue[DCP_MAX_CHANS];
0082     struct clk          *dcp_clk;
0083 };
0084 
0085 enum dcp_chan {
0086     DCP_CHAN_HASH_SHA   = 0,
0087     DCP_CHAN_CRYPTO     = 2,
0088 };
0089 
0090 struct dcp_async_ctx {
0091     /* Common context */
0092     enum dcp_chan   chan;
0093     uint32_t    fill;
0094 
0095     /* SHA Hash-specific context */
0096     struct mutex            mutex;
0097     uint32_t            alg;
0098     unsigned int            hot:1;
0099 
0100     /* Crypto-specific context */
0101     struct crypto_skcipher      *fallback;
0102     unsigned int            key_len;
0103     uint8_t             key[AES_KEYSIZE_128];
0104 };
0105 
0106 struct dcp_aes_req_ctx {
0107     unsigned int    enc:1;
0108     unsigned int    ecb:1;
0109     struct skcipher_request fallback_req;   // keep at the end
0110 };
0111 
0112 struct dcp_sha_req_ctx {
0113     unsigned int    init:1;
0114     unsigned int    fini:1;
0115 };
0116 
0117 struct dcp_export_state {
0118     struct dcp_sha_req_ctx req_ctx;
0119     struct dcp_async_ctx async_ctx;
0120 };
0121 
0122 /*
0123  * There can even be only one instance of the MXS DCP due to the
0124  * design of Linux Crypto API.
0125  */
0126 static struct dcp *global_sdcp;
0127 
0128 /* DCP register layout. */
0129 #define MXS_DCP_CTRL                0x00
0130 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
0131 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
0132 
0133 #define MXS_DCP_STAT                0x10
0134 #define MXS_DCP_STAT_CLR            0x18
0135 #define MXS_DCP_STAT_IRQ_MASK           0xf
0136 
0137 #define MXS_DCP_CHANNELCTRL         0x20
0138 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
0139 
0140 #define MXS_DCP_CAPABILITY1         0x40
0141 #define MXS_DCP_CAPABILITY1_SHA256      (4 << 16)
0142 #define MXS_DCP_CAPABILITY1_SHA1        (1 << 16)
0143 #define MXS_DCP_CAPABILITY1_AES128      (1 << 0)
0144 
0145 #define MXS_DCP_CONTEXT             0x50
0146 
0147 #define MXS_DCP_CH_N_CMDPTR(n)          (0x100 + ((n) * 0x40))
0148 
0149 #define MXS_DCP_CH_N_SEMA(n)            (0x110 + ((n) * 0x40))
0150 
0151 #define MXS_DCP_CH_N_STAT(n)            (0x120 + ((n) * 0x40))
0152 #define MXS_DCP_CH_N_STAT_CLR(n)        (0x128 + ((n) * 0x40))
0153 
0154 /* DMA descriptor bits. */
0155 #define MXS_DCP_CONTROL0_HASH_TERM      (1 << 13)
0156 #define MXS_DCP_CONTROL0_HASH_INIT      (1 << 12)
0157 #define MXS_DCP_CONTROL0_PAYLOAD_KEY        (1 << 11)
0158 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT     (1 << 8)
0159 #define MXS_DCP_CONTROL0_CIPHER_INIT        (1 << 9)
0160 #define MXS_DCP_CONTROL0_ENABLE_HASH        (1 << 6)
0161 #define MXS_DCP_CONTROL0_ENABLE_CIPHER      (1 << 5)
0162 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE     (1 << 1)
0163 #define MXS_DCP_CONTROL0_INTERRUPT      (1 << 0)
0164 
0165 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16)
0166 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1   (0 << 16)
0167 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC    (1 << 4)
0168 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB    (0 << 4)
0169 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128   (0 << 0)
0170 
0171 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
0172 {
0173     int dma_err;
0174     struct dcp *sdcp = global_sdcp;
0175     const int chan = actx->chan;
0176     uint32_t stat;
0177     unsigned long ret;
0178     struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
0179     dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
0180                           DMA_TO_DEVICE);
0181 
0182     dma_err = dma_mapping_error(sdcp->dev, desc_phys);
0183     if (dma_err)
0184         return dma_err;
0185 
0186     reinit_completion(&sdcp->completion[chan]);
0187 
0188     /* Clear status register. */
0189     writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
0190 
0191     /* Load the DMA descriptor. */
0192     writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
0193 
0194     /* Increment the semaphore to start the DMA transfer. */
0195     writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
0196 
0197     ret = wait_for_completion_timeout(&sdcp->completion[chan],
0198                       msecs_to_jiffies(1000));
0199     if (!ret) {
0200         dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
0201             chan, readl(sdcp->base + MXS_DCP_STAT));
0202         return -ETIMEDOUT;
0203     }
0204 
0205     stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
0206     if (stat & 0xff) {
0207         dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
0208             chan, stat);
0209         return -EINVAL;
0210     }
0211 
0212     dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
0213 
0214     return 0;
0215 }
0216 
0217 /*
0218  * Encryption (AES128)
0219  */
0220 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
0221                struct skcipher_request *req, int init)
0222 {
0223     dma_addr_t key_phys, src_phys, dst_phys;
0224     struct dcp *sdcp = global_sdcp;
0225     struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
0226     struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
0227     int ret;
0228 
0229     key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
0230                   2 * AES_KEYSIZE_128, DMA_TO_DEVICE);
0231     ret = dma_mapping_error(sdcp->dev, key_phys);
0232     if (ret)
0233         return ret;
0234 
0235     src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
0236                   DCP_BUF_SZ, DMA_TO_DEVICE);
0237     ret = dma_mapping_error(sdcp->dev, src_phys);
0238     if (ret)
0239         goto err_src;
0240 
0241     dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
0242                   DCP_BUF_SZ, DMA_FROM_DEVICE);
0243     ret = dma_mapping_error(sdcp->dev, dst_phys);
0244     if (ret)
0245         goto err_dst;
0246 
0247     if (actx->fill % AES_BLOCK_SIZE) {
0248         dev_err(sdcp->dev, "Invalid block size!\n");
0249         ret = -EINVAL;
0250         goto aes_done_run;
0251     }
0252 
0253     /* Fill in the DMA descriptor. */
0254     desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
0255             MXS_DCP_CONTROL0_INTERRUPT |
0256             MXS_DCP_CONTROL0_ENABLE_CIPHER;
0257 
0258     /* Payload contains the key. */
0259     desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
0260 
0261     if (rctx->enc)
0262         desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
0263     if (init)
0264         desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
0265 
0266     desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
0267 
0268     if (rctx->ecb)
0269         desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
0270     else
0271         desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
0272 
0273     desc->next_cmd_addr = 0;
0274     desc->source = src_phys;
0275     desc->destination = dst_phys;
0276     desc->size = actx->fill;
0277     desc->payload = key_phys;
0278     desc->status = 0;
0279 
0280     ret = mxs_dcp_start_dma(actx);
0281 
0282 aes_done_run:
0283     dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
0284 err_dst:
0285     dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
0286 err_src:
0287     dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
0288              DMA_TO_DEVICE);
0289 
0290     return ret;
0291 }
0292 
0293 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
0294 {
0295     struct dcp *sdcp = global_sdcp;
0296 
0297     struct skcipher_request *req = skcipher_request_cast(arq);
0298     struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
0299     struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
0300 
0301     struct scatterlist *dst = req->dst;
0302     struct scatterlist *src = req->src;
0303     int dst_nents = sg_nents(dst);
0304 
0305     const int out_off = DCP_BUF_SZ;
0306     uint8_t *in_buf = sdcp->coh->aes_in_buf;
0307     uint8_t *out_buf = sdcp->coh->aes_out_buf;
0308 
0309     uint32_t dst_off = 0;
0310     uint8_t *src_buf = NULL;
0311     uint32_t last_out_len = 0;
0312 
0313     uint8_t *key = sdcp->coh->aes_key;
0314 
0315     int ret = 0;
0316     unsigned int i, len, clen, tlen = 0;
0317     int init = 0;
0318     bool limit_hit = false;
0319 
0320     actx->fill = 0;
0321 
0322     /* Copy the key from the temporary location. */
0323     memcpy(key, actx->key, actx->key_len);
0324 
0325     if (!rctx->ecb) {
0326         /* Copy the CBC IV just past the key. */
0327         memcpy(key + AES_KEYSIZE_128, req->iv, AES_KEYSIZE_128);
0328         /* CBC needs the INIT set. */
0329         init = 1;
0330     } else {
0331         memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
0332     }
0333 
0334     for_each_sg(req->src, src, sg_nents(req->src), i) {
0335         src_buf = sg_virt(src);
0336         len = sg_dma_len(src);
0337         tlen += len;
0338         limit_hit = tlen > req->cryptlen;
0339 
0340         if (limit_hit)
0341             len = req->cryptlen - (tlen - len);
0342 
0343         do {
0344             if (actx->fill + len > out_off)
0345                 clen = out_off - actx->fill;
0346             else
0347                 clen = len;
0348 
0349             memcpy(in_buf + actx->fill, src_buf, clen);
0350             len -= clen;
0351             src_buf += clen;
0352             actx->fill += clen;
0353 
0354             /*
0355              * If we filled the buffer or this is the last SG,
0356              * submit the buffer.
0357              */
0358             if (actx->fill == out_off || sg_is_last(src) ||
0359                 limit_hit) {
0360                 ret = mxs_dcp_run_aes(actx, req, init);
0361                 if (ret)
0362                     return ret;
0363                 init = 0;
0364 
0365                 sg_pcopy_from_buffer(dst, dst_nents, out_buf,
0366                              actx->fill, dst_off);
0367                 dst_off += actx->fill;
0368                 last_out_len = actx->fill;
0369                 actx->fill = 0;
0370             }
0371         } while (len);
0372 
0373         if (limit_hit)
0374             break;
0375     }
0376 
0377     /* Copy the IV for CBC for chaining */
0378     if (!rctx->ecb) {
0379         if (rctx->enc)
0380             memcpy(req->iv, out_buf+(last_out_len-AES_BLOCK_SIZE),
0381                 AES_BLOCK_SIZE);
0382         else
0383             memcpy(req->iv, in_buf+(last_out_len-AES_BLOCK_SIZE),
0384                 AES_BLOCK_SIZE);
0385     }
0386 
0387     return ret;
0388 }
0389 
0390 static int dcp_chan_thread_aes(void *data)
0391 {
0392     struct dcp *sdcp = global_sdcp;
0393     const int chan = DCP_CHAN_CRYPTO;
0394 
0395     struct crypto_async_request *backlog;
0396     struct crypto_async_request *arq;
0397 
0398     int ret;
0399 
0400     while (!kthread_should_stop()) {
0401         set_current_state(TASK_INTERRUPTIBLE);
0402 
0403         spin_lock(&sdcp->lock[chan]);
0404         backlog = crypto_get_backlog(&sdcp->queue[chan]);
0405         arq = crypto_dequeue_request(&sdcp->queue[chan]);
0406         spin_unlock(&sdcp->lock[chan]);
0407 
0408         if (!backlog && !arq) {
0409             schedule();
0410             continue;
0411         }
0412 
0413         set_current_state(TASK_RUNNING);
0414 
0415         if (backlog)
0416             backlog->complete(backlog, -EINPROGRESS);
0417 
0418         if (arq) {
0419             ret = mxs_dcp_aes_block_crypt(arq);
0420             arq->complete(arq, ret);
0421         }
0422     }
0423 
0424     return 0;
0425 }
0426 
0427 static int mxs_dcp_block_fallback(struct skcipher_request *req, int enc)
0428 {
0429     struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
0430     struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
0431     struct dcp_async_ctx *ctx = crypto_skcipher_ctx(tfm);
0432     int ret;
0433 
0434     skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
0435     skcipher_request_set_callback(&rctx->fallback_req, req->base.flags,
0436                       req->base.complete, req->base.data);
0437     skcipher_request_set_crypt(&rctx->fallback_req, req->src, req->dst,
0438                    req->cryptlen, req->iv);
0439 
0440     if (enc)
0441         ret = crypto_skcipher_encrypt(&rctx->fallback_req);
0442     else
0443         ret = crypto_skcipher_decrypt(&rctx->fallback_req);
0444 
0445     return ret;
0446 }
0447 
0448 static int mxs_dcp_aes_enqueue(struct skcipher_request *req, int enc, int ecb)
0449 {
0450     struct dcp *sdcp = global_sdcp;
0451     struct crypto_async_request *arq = &req->base;
0452     struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
0453     struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
0454     int ret;
0455 
0456     if (unlikely(actx->key_len != AES_KEYSIZE_128))
0457         return mxs_dcp_block_fallback(req, enc);
0458 
0459     rctx->enc = enc;
0460     rctx->ecb = ecb;
0461     actx->chan = DCP_CHAN_CRYPTO;
0462 
0463     spin_lock(&sdcp->lock[actx->chan]);
0464     ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
0465     spin_unlock(&sdcp->lock[actx->chan]);
0466 
0467     wake_up_process(sdcp->thread[actx->chan]);
0468 
0469     return ret;
0470 }
0471 
0472 static int mxs_dcp_aes_ecb_decrypt(struct skcipher_request *req)
0473 {
0474     return mxs_dcp_aes_enqueue(req, 0, 1);
0475 }
0476 
0477 static int mxs_dcp_aes_ecb_encrypt(struct skcipher_request *req)
0478 {
0479     return mxs_dcp_aes_enqueue(req, 1, 1);
0480 }
0481 
0482 static int mxs_dcp_aes_cbc_decrypt(struct skcipher_request *req)
0483 {
0484     return mxs_dcp_aes_enqueue(req, 0, 0);
0485 }
0486 
0487 static int mxs_dcp_aes_cbc_encrypt(struct skcipher_request *req)
0488 {
0489     return mxs_dcp_aes_enqueue(req, 1, 0);
0490 }
0491 
0492 static int mxs_dcp_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
0493                   unsigned int len)
0494 {
0495     struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm);
0496 
0497     /*
0498      * AES 128 is supposed by the hardware, store key into temporary
0499      * buffer and exit. We must use the temporary buffer here, since
0500      * there can still be an operation in progress.
0501      */
0502     actx->key_len = len;
0503     if (len == AES_KEYSIZE_128) {
0504         memcpy(actx->key, key, len);
0505         return 0;
0506     }
0507 
0508     /*
0509      * If the requested AES key size is not supported by the hardware,
0510      * but is supported by in-kernel software implementation, we use
0511      * software fallback.
0512      */
0513     crypto_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK);
0514     crypto_skcipher_set_flags(actx->fallback,
0515                   tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
0516     return crypto_skcipher_setkey(actx->fallback, key, len);
0517 }
0518 
0519 static int mxs_dcp_aes_fallback_init_tfm(struct crypto_skcipher *tfm)
0520 {
0521     const char *name = crypto_tfm_alg_name(crypto_skcipher_tfm(tfm));
0522     struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm);
0523     struct crypto_skcipher *blk;
0524 
0525     blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
0526     if (IS_ERR(blk))
0527         return PTR_ERR(blk);
0528 
0529     actx->fallback = blk;
0530     crypto_skcipher_set_reqsize(tfm, sizeof(struct dcp_aes_req_ctx) +
0531                      crypto_skcipher_reqsize(blk));
0532     return 0;
0533 }
0534 
0535 static void mxs_dcp_aes_fallback_exit_tfm(struct crypto_skcipher *tfm)
0536 {
0537     struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm);
0538 
0539     crypto_free_skcipher(actx->fallback);
0540 }
0541 
0542 /*
0543  * Hashing (SHA1/SHA256)
0544  */
0545 static int mxs_dcp_run_sha(struct ahash_request *req)
0546 {
0547     struct dcp *sdcp = global_sdcp;
0548     int ret;
0549 
0550     struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
0551     struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
0552     struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
0553     struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
0554 
0555     dma_addr_t digest_phys = 0;
0556     dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
0557                          DCP_BUF_SZ, DMA_TO_DEVICE);
0558 
0559     ret = dma_mapping_error(sdcp->dev, buf_phys);
0560     if (ret)
0561         return ret;
0562 
0563     /* Fill in the DMA descriptor. */
0564     desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
0565             MXS_DCP_CONTROL0_INTERRUPT |
0566             MXS_DCP_CONTROL0_ENABLE_HASH;
0567     if (rctx->init)
0568         desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
0569 
0570     desc->control1 = actx->alg;
0571     desc->next_cmd_addr = 0;
0572     desc->source = buf_phys;
0573     desc->destination = 0;
0574     desc->size = actx->fill;
0575     desc->payload = 0;
0576     desc->status = 0;
0577 
0578     /*
0579      * Align driver with hw behavior when generating null hashes
0580      */
0581     if (rctx->init && rctx->fini && desc->size == 0) {
0582         struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
0583         const uint8_t *sha_buf =
0584             (actx->alg == MXS_DCP_CONTROL1_HASH_SELECT_SHA1) ?
0585             sha1_null_hash : sha256_null_hash;
0586         memcpy(sdcp->coh->sha_out_buf, sha_buf, halg->digestsize);
0587         ret = 0;
0588         goto done_run;
0589     }
0590 
0591     /* Set HASH_TERM bit for last transfer block. */
0592     if (rctx->fini) {
0593         digest_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_out_buf,
0594                          DCP_SHA_PAY_SZ, DMA_FROM_DEVICE);
0595         ret = dma_mapping_error(sdcp->dev, digest_phys);
0596         if (ret)
0597             goto done_run;
0598 
0599         desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
0600         desc->payload = digest_phys;
0601     }
0602 
0603     ret = mxs_dcp_start_dma(actx);
0604 
0605     if (rctx->fini)
0606         dma_unmap_single(sdcp->dev, digest_phys, DCP_SHA_PAY_SZ,
0607                  DMA_FROM_DEVICE);
0608 
0609 done_run:
0610     dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
0611 
0612     return ret;
0613 }
0614 
0615 static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
0616 {
0617     struct dcp *sdcp = global_sdcp;
0618 
0619     struct ahash_request *req = ahash_request_cast(arq);
0620     struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
0621     struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
0622     struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
0623     struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
0624 
0625     uint8_t *in_buf = sdcp->coh->sha_in_buf;
0626     uint8_t *out_buf = sdcp->coh->sha_out_buf;
0627 
0628     struct scatterlist *src;
0629 
0630     unsigned int i, len, clen, oft = 0;
0631     int ret;
0632 
0633     int fin = rctx->fini;
0634     if (fin)
0635         rctx->fini = 0;
0636 
0637     src = req->src;
0638     len = req->nbytes;
0639 
0640     while (len) {
0641         if (actx->fill + len > DCP_BUF_SZ)
0642             clen = DCP_BUF_SZ - actx->fill;
0643         else
0644             clen = len;
0645 
0646         scatterwalk_map_and_copy(in_buf + actx->fill, src, oft, clen,
0647                      0);
0648 
0649         len -= clen;
0650         oft += clen;
0651         actx->fill += clen;
0652 
0653         /*
0654          * If we filled the buffer and still have some
0655          * more data, submit the buffer.
0656          */
0657         if (len && actx->fill == DCP_BUF_SZ) {
0658             ret = mxs_dcp_run_sha(req);
0659             if (ret)
0660                 return ret;
0661             actx->fill = 0;
0662             rctx->init = 0;
0663         }
0664     }
0665 
0666     if (fin) {
0667         rctx->fini = 1;
0668 
0669         /* Submit whatever is left. */
0670         if (!req->result)
0671             return -EINVAL;
0672 
0673         ret = mxs_dcp_run_sha(req);
0674         if (ret)
0675             return ret;
0676 
0677         actx->fill = 0;
0678 
0679         /* For some reason the result is flipped */
0680         for (i = 0; i < halg->digestsize; i++)
0681             req->result[i] = out_buf[halg->digestsize - i - 1];
0682     }
0683 
0684     return 0;
0685 }
0686 
0687 static int dcp_chan_thread_sha(void *data)
0688 {
0689     struct dcp *sdcp = global_sdcp;
0690     const int chan = DCP_CHAN_HASH_SHA;
0691 
0692     struct crypto_async_request *backlog;
0693     struct crypto_async_request *arq;
0694     int ret;
0695 
0696     while (!kthread_should_stop()) {
0697         set_current_state(TASK_INTERRUPTIBLE);
0698 
0699         spin_lock(&sdcp->lock[chan]);
0700         backlog = crypto_get_backlog(&sdcp->queue[chan]);
0701         arq = crypto_dequeue_request(&sdcp->queue[chan]);
0702         spin_unlock(&sdcp->lock[chan]);
0703 
0704         if (!backlog && !arq) {
0705             schedule();
0706             continue;
0707         }
0708 
0709         set_current_state(TASK_RUNNING);
0710 
0711         if (backlog)
0712             backlog->complete(backlog, -EINPROGRESS);
0713 
0714         if (arq) {
0715             ret = dcp_sha_req_to_buf(arq);
0716             arq->complete(arq, ret);
0717         }
0718     }
0719 
0720     return 0;
0721 }
0722 
0723 static int dcp_sha_init(struct ahash_request *req)
0724 {
0725     struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
0726     struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
0727 
0728     struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
0729 
0730     /*
0731      * Start hashing session. The code below only inits the
0732      * hashing session context, nothing more.
0733      */
0734     memset(actx, 0, sizeof(*actx));
0735 
0736     if (strcmp(halg->base.cra_name, "sha1") == 0)
0737         actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
0738     else
0739         actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
0740 
0741     actx->fill = 0;
0742     actx->hot = 0;
0743     actx->chan = DCP_CHAN_HASH_SHA;
0744 
0745     mutex_init(&actx->mutex);
0746 
0747     return 0;
0748 }
0749 
0750 static int dcp_sha_update_fx(struct ahash_request *req, int fini)
0751 {
0752     struct dcp *sdcp = global_sdcp;
0753 
0754     struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
0755     struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
0756     struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
0757 
0758     int ret;
0759 
0760     /*
0761      * Ignore requests that have no data in them and are not
0762      * the trailing requests in the stream of requests.
0763      */
0764     if (!req->nbytes && !fini)
0765         return 0;
0766 
0767     mutex_lock(&actx->mutex);
0768 
0769     rctx->fini = fini;
0770 
0771     if (!actx->hot) {
0772         actx->hot = 1;
0773         rctx->init = 1;
0774     }
0775 
0776     spin_lock(&sdcp->lock[actx->chan]);
0777     ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
0778     spin_unlock(&sdcp->lock[actx->chan]);
0779 
0780     wake_up_process(sdcp->thread[actx->chan]);
0781     mutex_unlock(&actx->mutex);
0782 
0783     return ret;
0784 }
0785 
0786 static int dcp_sha_update(struct ahash_request *req)
0787 {
0788     return dcp_sha_update_fx(req, 0);
0789 }
0790 
0791 static int dcp_sha_final(struct ahash_request *req)
0792 {
0793     ahash_request_set_crypt(req, NULL, req->result, 0);
0794     req->nbytes = 0;
0795     return dcp_sha_update_fx(req, 1);
0796 }
0797 
0798 static int dcp_sha_finup(struct ahash_request *req)
0799 {
0800     return dcp_sha_update_fx(req, 1);
0801 }
0802 
0803 static int dcp_sha_digest(struct ahash_request *req)
0804 {
0805     int ret;
0806 
0807     ret = dcp_sha_init(req);
0808     if (ret)
0809         return ret;
0810 
0811     return dcp_sha_finup(req);
0812 }
0813 
0814 static int dcp_sha_import(struct ahash_request *req, const void *in)
0815 {
0816     struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
0817     struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
0818     struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
0819     const struct dcp_export_state *export = in;
0820 
0821     memset(rctx, 0, sizeof(struct dcp_sha_req_ctx));
0822     memset(actx, 0, sizeof(struct dcp_async_ctx));
0823     memcpy(rctx, &export->req_ctx, sizeof(struct dcp_sha_req_ctx));
0824     memcpy(actx, &export->async_ctx, sizeof(struct dcp_async_ctx));
0825 
0826     return 0;
0827 }
0828 
0829 static int dcp_sha_export(struct ahash_request *req, void *out)
0830 {
0831     struct dcp_sha_req_ctx *rctx_state = ahash_request_ctx(req);
0832     struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
0833     struct dcp_async_ctx *actx_state = crypto_ahash_ctx(tfm);
0834     struct dcp_export_state *export = out;
0835 
0836     memcpy(&export->req_ctx, rctx_state, sizeof(struct dcp_sha_req_ctx));
0837     memcpy(&export->async_ctx, actx_state, sizeof(struct dcp_async_ctx));
0838 
0839     return 0;
0840 }
0841 
0842 static int dcp_sha_cra_init(struct crypto_tfm *tfm)
0843 {
0844     crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
0845                  sizeof(struct dcp_sha_req_ctx));
0846     return 0;
0847 }
0848 
0849 static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
0850 {
0851 }
0852 
0853 /* AES 128 ECB and AES 128 CBC */
0854 static struct skcipher_alg dcp_aes_algs[] = {
0855     {
0856         .base.cra_name      = "ecb(aes)",
0857         .base.cra_driver_name   = "ecb-aes-dcp",
0858         .base.cra_priority  = 400,
0859         .base.cra_alignmask = 15,
0860         .base.cra_flags     = CRYPTO_ALG_ASYNC |
0861                       CRYPTO_ALG_NEED_FALLBACK,
0862         .base.cra_blocksize = AES_BLOCK_SIZE,
0863         .base.cra_ctxsize   = sizeof(struct dcp_async_ctx),
0864         .base.cra_module    = THIS_MODULE,
0865 
0866         .min_keysize        = AES_MIN_KEY_SIZE,
0867         .max_keysize        = AES_MAX_KEY_SIZE,
0868         .setkey         = mxs_dcp_aes_setkey,
0869         .encrypt        = mxs_dcp_aes_ecb_encrypt,
0870         .decrypt        = mxs_dcp_aes_ecb_decrypt,
0871         .init           = mxs_dcp_aes_fallback_init_tfm,
0872         .exit           = mxs_dcp_aes_fallback_exit_tfm,
0873     }, {
0874         .base.cra_name      = "cbc(aes)",
0875         .base.cra_driver_name   = "cbc-aes-dcp",
0876         .base.cra_priority  = 400,
0877         .base.cra_alignmask = 15,
0878         .base.cra_flags     = CRYPTO_ALG_ASYNC |
0879                       CRYPTO_ALG_NEED_FALLBACK,
0880         .base.cra_blocksize = AES_BLOCK_SIZE,
0881         .base.cra_ctxsize   = sizeof(struct dcp_async_ctx),
0882         .base.cra_module    = THIS_MODULE,
0883 
0884         .min_keysize        = AES_MIN_KEY_SIZE,
0885         .max_keysize        = AES_MAX_KEY_SIZE,
0886         .setkey         = mxs_dcp_aes_setkey,
0887         .encrypt        = mxs_dcp_aes_cbc_encrypt,
0888         .decrypt        = mxs_dcp_aes_cbc_decrypt,
0889         .ivsize         = AES_BLOCK_SIZE,
0890         .init           = mxs_dcp_aes_fallback_init_tfm,
0891         .exit           = mxs_dcp_aes_fallback_exit_tfm,
0892     },
0893 };
0894 
0895 /* SHA1 */
0896 static struct ahash_alg dcp_sha1_alg = {
0897     .init   = dcp_sha_init,
0898     .update = dcp_sha_update,
0899     .final  = dcp_sha_final,
0900     .finup  = dcp_sha_finup,
0901     .digest = dcp_sha_digest,
0902     .import = dcp_sha_import,
0903     .export = dcp_sha_export,
0904     .halg   = {
0905         .digestsize = SHA1_DIGEST_SIZE,
0906         .statesize  = sizeof(struct dcp_export_state),
0907         .base       = {
0908             .cra_name       = "sha1",
0909             .cra_driver_name    = "sha1-dcp",
0910             .cra_priority       = 400,
0911             .cra_alignmask      = 63,
0912             .cra_flags      = CRYPTO_ALG_ASYNC,
0913             .cra_blocksize      = SHA1_BLOCK_SIZE,
0914             .cra_ctxsize        = sizeof(struct dcp_async_ctx),
0915             .cra_module     = THIS_MODULE,
0916             .cra_init       = dcp_sha_cra_init,
0917             .cra_exit       = dcp_sha_cra_exit,
0918         },
0919     },
0920 };
0921 
0922 /* SHA256 */
0923 static struct ahash_alg dcp_sha256_alg = {
0924     .init   = dcp_sha_init,
0925     .update = dcp_sha_update,
0926     .final  = dcp_sha_final,
0927     .finup  = dcp_sha_finup,
0928     .digest = dcp_sha_digest,
0929     .import = dcp_sha_import,
0930     .export = dcp_sha_export,
0931     .halg   = {
0932         .digestsize = SHA256_DIGEST_SIZE,
0933         .statesize  = sizeof(struct dcp_export_state),
0934         .base       = {
0935             .cra_name       = "sha256",
0936             .cra_driver_name    = "sha256-dcp",
0937             .cra_priority       = 400,
0938             .cra_alignmask      = 63,
0939             .cra_flags      = CRYPTO_ALG_ASYNC,
0940             .cra_blocksize      = SHA256_BLOCK_SIZE,
0941             .cra_ctxsize        = sizeof(struct dcp_async_ctx),
0942             .cra_module     = THIS_MODULE,
0943             .cra_init       = dcp_sha_cra_init,
0944             .cra_exit       = dcp_sha_cra_exit,
0945         },
0946     },
0947 };
0948 
0949 static irqreturn_t mxs_dcp_irq(int irq, void *context)
0950 {
0951     struct dcp *sdcp = context;
0952     uint32_t stat;
0953     int i;
0954 
0955     stat = readl(sdcp->base + MXS_DCP_STAT);
0956     stat &= MXS_DCP_STAT_IRQ_MASK;
0957     if (!stat)
0958         return IRQ_NONE;
0959 
0960     /* Clear the interrupts. */
0961     writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
0962 
0963     /* Complete the DMA requests that finished. */
0964     for (i = 0; i < DCP_MAX_CHANS; i++)
0965         if (stat & (1 << i))
0966             complete(&sdcp->completion[i]);
0967 
0968     return IRQ_HANDLED;
0969 }
0970 
0971 static int mxs_dcp_probe(struct platform_device *pdev)
0972 {
0973     struct device *dev = &pdev->dev;
0974     struct dcp *sdcp = NULL;
0975     int i, ret;
0976     int dcp_vmi_irq, dcp_irq;
0977 
0978     if (global_sdcp) {
0979         dev_err(dev, "Only one DCP instance allowed!\n");
0980         return -ENODEV;
0981     }
0982 
0983     dcp_vmi_irq = platform_get_irq(pdev, 0);
0984     if (dcp_vmi_irq < 0)
0985         return dcp_vmi_irq;
0986 
0987     dcp_irq = platform_get_irq(pdev, 1);
0988     if (dcp_irq < 0)
0989         return dcp_irq;
0990 
0991     sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
0992     if (!sdcp)
0993         return -ENOMEM;
0994 
0995     sdcp->dev = dev;
0996     sdcp->base = devm_platform_ioremap_resource(pdev, 0);
0997     if (IS_ERR(sdcp->base))
0998         return PTR_ERR(sdcp->base);
0999 
1000 
1001     ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
1002                    "dcp-vmi-irq", sdcp);
1003     if (ret) {
1004         dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
1005         return ret;
1006     }
1007 
1008     ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
1009                    "dcp-irq", sdcp);
1010     if (ret) {
1011         dev_err(dev, "Failed to claim DCP IRQ!\n");
1012         return ret;
1013     }
1014 
1015     /* Allocate coherent helper block. */
1016     sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
1017                    GFP_KERNEL);
1018     if (!sdcp->coh)
1019         return -ENOMEM;
1020 
1021     /* Re-align the structure so it fits the DCP constraints. */
1022     sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
1023 
1024     /* DCP clock is optional, only used on some SOCs */
1025     sdcp->dcp_clk = devm_clk_get(dev, "dcp");
1026     if (IS_ERR(sdcp->dcp_clk)) {
1027         if (sdcp->dcp_clk != ERR_PTR(-ENOENT))
1028             return PTR_ERR(sdcp->dcp_clk);
1029         sdcp->dcp_clk = NULL;
1030     }
1031     ret = clk_prepare_enable(sdcp->dcp_clk);
1032     if (ret)
1033         return ret;
1034 
1035     /* Restart the DCP block. */
1036     ret = stmp_reset_block(sdcp->base);
1037     if (ret) {
1038         dev_err(dev, "Failed reset\n");
1039         goto err_disable_unprepare_clk;
1040     }
1041 
1042     /* Initialize control register. */
1043     writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
1044            MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
1045            sdcp->base + MXS_DCP_CTRL);
1046 
1047     /* Enable all DCP DMA channels. */
1048     writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
1049            sdcp->base + MXS_DCP_CHANNELCTRL);
1050 
1051     /*
1052      * We do not enable context switching. Give the context buffer a
1053      * pointer to an illegal address so if context switching is
1054      * inadvertantly enabled, the DCP will return an error instead of
1055      * trashing good memory. The DCP DMA cannot access ROM, so any ROM
1056      * address will do.
1057      */
1058     writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
1059     for (i = 0; i < DCP_MAX_CHANS; i++)
1060         writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
1061     writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
1062 
1063     global_sdcp = sdcp;
1064 
1065     platform_set_drvdata(pdev, sdcp);
1066 
1067     for (i = 0; i < DCP_MAX_CHANS; i++) {
1068         spin_lock_init(&sdcp->lock[i]);
1069         init_completion(&sdcp->completion[i]);
1070         crypto_init_queue(&sdcp->queue[i], 50);
1071     }
1072 
1073     /* Create the SHA and AES handler threads. */
1074     sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
1075                               NULL, "mxs_dcp_chan/sha");
1076     if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1077         dev_err(dev, "Error starting SHA thread!\n");
1078         ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
1079         goto err_disable_unprepare_clk;
1080     }
1081 
1082     sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
1083                             NULL, "mxs_dcp_chan/aes");
1084     if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
1085         dev_err(dev, "Error starting SHA thread!\n");
1086         ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1087         goto err_destroy_sha_thread;
1088     }
1089 
1090     /* Register the various crypto algorithms. */
1091     sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1092 
1093     if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1094         ret = crypto_register_skciphers(dcp_aes_algs,
1095                         ARRAY_SIZE(dcp_aes_algs));
1096         if (ret) {
1097             /* Failed to register algorithm. */
1098             dev_err(dev, "Failed to register AES crypto!\n");
1099             goto err_destroy_aes_thread;
1100         }
1101     }
1102 
1103     if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1104         ret = crypto_register_ahash(&dcp_sha1_alg);
1105         if (ret) {
1106             dev_err(dev, "Failed to register %s hash!\n",
1107                 dcp_sha1_alg.halg.base.cra_name);
1108             goto err_unregister_aes;
1109         }
1110     }
1111 
1112     if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1113         ret = crypto_register_ahash(&dcp_sha256_alg);
1114         if (ret) {
1115             dev_err(dev, "Failed to register %s hash!\n",
1116                 dcp_sha256_alg.halg.base.cra_name);
1117             goto err_unregister_sha1;
1118         }
1119     }
1120 
1121     return 0;
1122 
1123 err_unregister_sha1:
1124     if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1125         crypto_unregister_ahash(&dcp_sha1_alg);
1126 
1127 err_unregister_aes:
1128     if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1129         crypto_unregister_skciphers(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1130 
1131 err_destroy_aes_thread:
1132     kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1133 
1134 err_destroy_sha_thread:
1135     kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1136 
1137 err_disable_unprepare_clk:
1138     clk_disable_unprepare(sdcp->dcp_clk);
1139 
1140     return ret;
1141 }
1142 
1143 static int mxs_dcp_remove(struct platform_device *pdev)
1144 {
1145     struct dcp *sdcp = platform_get_drvdata(pdev);
1146 
1147     if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1148         crypto_unregister_ahash(&dcp_sha256_alg);
1149 
1150     if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1151         crypto_unregister_ahash(&dcp_sha1_alg);
1152 
1153     if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1154         crypto_unregister_skciphers(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1155 
1156     kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1157     kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1158 
1159     clk_disable_unprepare(sdcp->dcp_clk);
1160 
1161     platform_set_drvdata(pdev, NULL);
1162 
1163     global_sdcp = NULL;
1164 
1165     return 0;
1166 }
1167 
1168 static const struct of_device_id mxs_dcp_dt_ids[] = {
1169     { .compatible = "fsl,imx23-dcp", .data = NULL, },
1170     { .compatible = "fsl,imx28-dcp", .data = NULL, },
1171     { /* sentinel */ }
1172 };
1173 
1174 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1175 
1176 static struct platform_driver mxs_dcp_driver = {
1177     .probe  = mxs_dcp_probe,
1178     .remove = mxs_dcp_remove,
1179     .driver = {
1180         .name       = "mxs-dcp",
1181         .of_match_table = mxs_dcp_dt_ids,
1182     },
1183 };
1184 
1185 module_platform_driver(mxs_dcp_driver);
1186 
1187 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1188 MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1189 MODULE_LICENSE("GPL");
1190 MODULE_ALIAS("platform:mxs-dcp");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!