marvell/octeontx2/otx2_cptvf.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  * Copyright (C) 2020 Marvell.
0003  */
0004
0005 #ifndef __OTX2_CPTVF_H
0006 #define __OTX2_CPTVF_H
0007
0008 #include "mbox.h"
0009 #include "otx2_cptlf.h"
0010
0011 struct otx2_cptvf_dev {
0012     void __iomem *reg_base;     /* Register start address */
0013     void __iomem *pfvf_mbox_base;   /* PF-VF mbox start address */
0014     struct pci_dev *pdev;       /* PCI device handle */
0015     struct otx2_cptlfs_info lfs;    /* CPT LFs attached to this VF */
0016     u8 vf_id;           /* Virtual function index */
0017
0018     /* PF <=> VF mbox */
0019     struct otx2_mbox    pfvf_mbox;
0020     struct work_struct  pfvf_mbox_work;
0021     struct workqueue_struct *pfvf_mbox_wq;
0022     void *bbuf_base;
0023     unsigned long cap_flag;
0024 };
0025
0026 irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg);
0027 void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work);
0028 int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type);
0029 int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf);
0030 int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev);
0031
0032 #endif /* __OTX2_CPTVF_H */