marvell/octeontx2/otx2_cptpf_ucode.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  * Copyright (C) 2020 Marvell.
0003  */
0004
0005 #ifndef __OTX2_CPTPF_UCODE_H
0006 #define __OTX2_CPTPF_UCODE_H
0007
0008 #include <linux/pci.h>
0009 #include <linux/types.h>
0010 #include <linux/module.h>
0011 #include "otx2_cpt_hw_types.h"
0012 #include "otx2_cpt_common.h"
0013
0014 /*
0015  * On OcteonTX2 platform IPSec ucode can use both IE and SE engines therefore
0016  * IE and SE engines can be attached to the same engine group.
0017  */
0018 #define OTX2_CPT_MAX_ETYPES_PER_GRP 2
0019
0020 /* CPT ucode signature size */
0021 #define OTX2_CPT_UCODE_SIGN_LEN     256
0022
0023 /* Microcode version string length */
0024 #define OTX2_CPT_UCODE_VER_STR_SZ   44
0025
0026 /* Maximum number of supported engines/cores on OcteonTX2/CN10K platform */
0027 #define OTX2_CPT_MAX_ENGINES        144
0028
0029 #define OTX2_CPT_ENGS_BITMASK_LEN   BITS_TO_LONGS(OTX2_CPT_MAX_ENGINES)
0030
0031 #define OTX2_CPT_UCODE_SZ           (64 * 1024)
0032
0033 /* Microcode types */
0034 enum otx2_cpt_ucode_type {
0035     OTX2_CPT_AE_UC_TYPE = 1,  /* AE-MAIN */
0036     OTX2_CPT_SE_UC_TYPE1 = 20,/* SE-MAIN - combination of 21 and 22 */
0037     OTX2_CPT_SE_UC_TYPE2 = 21,/* Fast Path IPSec + AirCrypto */
0038     OTX2_CPT_SE_UC_TYPE3 = 22,/*
0039                    * Hash + HMAC + FlexiCrypto + RNG +
0040                    * Full Feature IPSec + AirCrypto + Kasumi
0041                    */
0042     OTX2_CPT_IE_UC_TYPE1 = 30, /* IE-MAIN - combination of 31 and 32 */
0043     OTX2_CPT_IE_UC_TYPE2 = 31, /* Fast Path IPSec */
0044     OTX2_CPT_IE_UC_TYPE3 = 32, /*
0045                     * Hash + HMAC + FlexiCrypto + RNG +
0046                     * Full Future IPSec
0047                     */
0048 };
0049
0050 struct otx2_cpt_bitmap {
0051     unsigned long bits[OTX2_CPT_ENGS_BITMASK_LEN];
0052     int size;
0053 };
0054
0055 struct otx2_cpt_engines {
0056     int type;
0057     int count;
0058 };
0059
0060 /* Microcode version number */
0061 struct otx2_cpt_ucode_ver_num {
0062     u8 nn;
0063     u8 xx;
0064     u8 yy;
0065     u8 zz;
0066 };
0067
0068 struct otx2_cpt_ucode_hdr {
0069     struct otx2_cpt_ucode_ver_num ver_num;
0070     u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];
0071     __be32 code_length;
0072     u32 padding[3];
0073 };
0074
0075 struct otx2_cpt_ucode {
0076     u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/*
0077                            * ucode version in readable
0078                            * format
0079                            */
0080     struct otx2_cpt_ucode_ver_num ver_num;/* ucode version number */
0081     char filename[OTX2_CPT_NAME_LENGTH];/* ucode filename */
0082     dma_addr_t dma;     /* phys address of ucode image */
0083     void *va;       /* virt address of ucode image */
0084     u32 size;       /* ucode image size */
0085     int type;       /* ucode image type SE, IE, AE or SE+IE */
0086 };
0087
0088 struct otx2_cpt_uc_info_t {
0089     struct list_head list;
0090     struct otx2_cpt_ucode ucode;/* microcode information */
0091     const struct firmware *fw;
0092 };
0093
0094 /* Maximum and current number of engines available for all engine groups */
0095 struct otx2_cpt_engs_available {
0096     int max_se_cnt;
0097     int max_ie_cnt;
0098     int max_ae_cnt;
0099     int se_cnt;
0100     int ie_cnt;
0101     int ae_cnt;
0102 };
0103
0104 /* Engines reserved to an engine group */
0105 struct otx2_cpt_engs_rsvd {
0106     int type;   /* engine type */
0107     int count;  /* number of engines attached */
0108     int offset;     /* constant offset of engine type in the bitmap */
0109     unsigned long *bmap;        /* attached engines bitmap */
0110     struct otx2_cpt_ucode *ucode;   /* ucode used by these engines */
0111 };
0112
0113 struct otx2_cpt_mirror_info {
0114     int is_ena; /*
0115              * is mirroring enabled, it is set only for engine
0116              * group which mirrors another engine group
0117              */
0118     int idx;    /*
0119              * index of engine group which is mirrored by this
0120              * group, set only for engine group which mirrors
0121              * another group
0122              */
0123     int ref_count;  /*
0124              * number of times this engine group is mirrored by
0125              * other groups, this is set only for engine group
0126              * which is mirrored by other group(s)
0127              */
0128 };
0129
0130 struct otx2_cpt_eng_grp_info {
0131     struct otx2_cpt_eng_grps *g; /* pointer to engine_groups structure */
0132     /* engines attached */
0133     struct otx2_cpt_engs_rsvd engs[OTX2_CPT_MAX_ETYPES_PER_GRP];
0134     /* ucodes information */
0135     struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP];
0136     /* engine group mirroring information */
0137     struct otx2_cpt_mirror_info mirror;
0138     int idx;     /* engine group index */
0139     bool is_enabled; /*
0140               * is engine group enabled, engine group is enabled
0141               * when it has engines attached and ucode loaded
0142               */
0143 };
0144
0145 struct otx2_cpt_eng_grps {
0146     struct mutex lock;
0147     struct otx2_cpt_eng_grp_info grp[OTX2_CPT_MAX_ENGINE_GROUPS];
0148     struct otx2_cpt_engs_available avail;
0149     void *obj;          /* device specific data */
0150     int engs_num;           /* total number of engines supported */
0151     u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines reference count */
0152     bool is_grps_created; /* Is the engine groups are already created */
0153 };
0154 struct otx2_cptpf_dev;
0155 int otx2_cpt_init_eng_grps(struct pci_dev *pdev,
0156                struct otx2_cpt_eng_grps *eng_grps);
0157 void otx2_cpt_cleanup_eng_grps(struct pci_dev *pdev,
0158                    struct otx2_cpt_eng_grps *eng_grps);
0159 int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
0160                  struct otx2_cpt_eng_grps *eng_grps);
0161 int otx2_cpt_disable_all_cores(struct otx2_cptpf_dev *cptpf);
0162 int otx2_cpt_get_eng_grp(struct otx2_cpt_eng_grps *eng_grps, int eng_type);
0163 int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf);
0164 int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf,
0165                    struct devlink_param_gset_ctx *ctx);
0166 int otx2_cpt_dl_custom_egrp_delete(struct otx2_cptpf_dev *cptpf,
0167                    struct devlink_param_gset_ctx *ctx);
0168 void otx2_cpt_print_uc_dbg_info(struct otx2_cptpf_dev *cptpf);
0169 struct otx2_cpt_engs_rsvd *find_engines_by_type(
0170                     struct otx2_cpt_eng_grp_info *eng_grp,
0171                     int eng_type);
0172 #endif /* __OTX2_CPTPF_UCODE_H */