marvell/octeontx2/otx2_cptpf.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  * Copyright (C) 2020 Marvell.
0003  */
0004
0005 #ifndef __OTX2_CPTPF_H
0006 #define __OTX2_CPTPF_H
0007
0008 #include "otx2_cpt_common.h"
0009 #include "otx2_cptpf_ucode.h"
0010 #include "otx2_cptlf.h"
0011
0012 struct otx2_cptpf_dev;
0013 struct otx2_cptvf_info {
0014     struct otx2_cptpf_dev *cptpf;   /* PF pointer this VF belongs to */
0015     struct work_struct vfpf_mbox_work;
0016     struct pci_dev *vf_dev;
0017     int vf_id;
0018     int intr_idx;
0019 };
0020
0021 struct cptpf_flr_work {
0022     struct work_struct work;
0023     struct otx2_cptpf_dev *pf;
0024 };
0025
0026 struct otx2_cptpf_dev {
0027     void __iomem *reg_base;     /* CPT PF registers start address */
0028     void __iomem *afpf_mbox_base;   /* PF-AF mbox start address */
0029     void __iomem *vfpf_mbox_base;   /* VF-PF mbox start address */
0030     struct pci_dev *pdev;       /* PCI device handle */
0031     struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];
0032     struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */
0033     struct otx2_cptlfs_info lfs;      /* CPT LFs attached to this PF */
0034     /* HW capabilities for each engine type */
0035     union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
0036     bool is_eng_caps_discovered;
0037
0038     /* AF <=> PF mbox */
0039     struct otx2_mbox    afpf_mbox;
0040     struct work_struct  afpf_mbox_work;
0041     struct workqueue_struct *afpf_mbox_wq;
0042
0043     /* VF <=> PF mbox */
0044     struct otx2_mbox    vfpf_mbox;
0045     struct workqueue_struct *vfpf_mbox_wq;
0046
0047     struct workqueue_struct *flr_wq;
0048     struct cptpf_flr_work   *flr_work;
0049     struct mutex            lock;   /* serialize mailbox access */
0050
0051     unsigned long cap_flag;
0052     u8 pf_id;               /* RVU PF number */
0053     u8 max_vfs;     /* Maximum number of VFs supported by CPT */
0054     u8 enabled_vfs;     /* Number of enabled VFs */
0055     u8 kvf_limits;      /* Kernel crypto limits */
0056     bool has_cpt1;
0057
0058     /* Devlink */
0059     struct devlink *dl;
0060 };
0061
0062 irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);
0063 void otx2_cptpf_afpf_mbox_handler(struct work_struct *work);
0064 irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg);
0065 void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work);
0066
0067 #endif /* __OTX2_CPTPF_H */