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0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  * Copyright (C) 2020 Marvell.
0003  */
0004 #ifndef __OTX2_CPTLF_H
0005 #define __OTX2_CPTLF_H
0006 
0007 #include <linux/soc/marvell/octeontx2/asm.h>
0008 #include <mbox.h>
0009 #include <rvu.h>
0010 #include "otx2_cpt_common.h"
0011 #include "otx2_cpt_reqmgr.h"
0012 
0013 /*
0014  * CPT instruction and pending queues user requested length in CPT_INST_S msgs
0015  */
0016 #define OTX2_CPT_USER_REQUESTED_QLEN_MSGS 8200
0017 
0018 /*
0019  * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S
0020  * messages.
0021  */
0022 #define OTX2_CPT_SIZE_DIV40 (OTX2_CPT_USER_REQUESTED_QLEN_MSGS/40)
0023 
0024 /*
0025  * CPT instruction and pending queues length in CPT_INST_S messages
0026  */
0027 #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40)
0028 
0029 /*
0030  * LDWB is getting incorrectly used when IQB_LDWB = 1 and CPT instruction
0031  * queue has less than 320 free entries. So, increase HW instruction queue
0032  * size by 320 and give 320 entries less for SW/NIX RX as a workaround.
0033  */
0034 #define OTX2_CPT_INST_QLEN_EXTRA_BYTES  (320 * OTX2_CPT_INST_SIZE)
0035 #define OTX2_CPT_EXTRA_SIZE_DIV40       (320/40)
0036 
0037 /* CPT instruction queue length in bytes */
0038 #define OTX2_CPT_INST_QLEN_BYTES                                               \
0039         ((OTX2_CPT_SIZE_DIV40 * 40 * OTX2_CPT_INST_SIZE) +             \
0040         OTX2_CPT_INST_QLEN_EXTRA_BYTES)
0041 
0042 /* CPT instruction group queue length in bytes */
0043 #define OTX2_CPT_INST_GRP_QLEN_BYTES                                           \
0044         ((OTX2_CPT_SIZE_DIV40 + OTX2_CPT_EXTRA_SIZE_DIV40) * 16)
0045 
0046 /* CPT FC length in bytes */
0047 #define OTX2_CPT_Q_FC_LEN 128
0048 
0049 /* CPT instruction queue alignment */
0050 #define OTX2_CPT_INST_Q_ALIGNMENT  128
0051 
0052 /* Mask which selects all engine groups */
0053 #define OTX2_CPT_ALL_ENG_GRPS_MASK 0xFF
0054 
0055 /* Maximum LFs supported in OcteonTX2 for CPT */
0056 #define OTX2_CPT_MAX_LFS_NUM    64
0057 
0058 /* Queue priority */
0059 #define OTX2_CPT_QUEUE_HI_PRIO  0x1
0060 #define OTX2_CPT_QUEUE_LOW_PRIO 0x0
0061 
0062 enum otx2_cptlf_state {
0063     OTX2_CPTLF_IN_RESET,
0064     OTX2_CPTLF_STARTED,
0065 };
0066 
0067 struct otx2_cpt_inst_queue {
0068     u8 *vaddr;
0069     u8 *real_vaddr;
0070     dma_addr_t dma_addr;
0071     dma_addr_t real_dma_addr;
0072     u32 size;
0073 };
0074 
0075 struct otx2_cptlfs_info;
0076 struct otx2_cptlf_wqe {
0077     struct tasklet_struct work;
0078     struct otx2_cptlfs_info *lfs;
0079     u8 lf_num;
0080 };
0081 
0082 struct otx2_cptlf_info {
0083     struct otx2_cptlfs_info *lfs;           /* Ptr to cptlfs_info struct */
0084     void __iomem *lmtline;                  /* Address of LMTLINE */
0085     void __iomem *ioreg;                    /* LMTLINE send register */
0086     int msix_offset;                        /* MSI-X interrupts offset */
0087     cpumask_var_t affinity_mask;            /* IRQs affinity mask */
0088     u8 irq_name[OTX2_CPT_LF_MSIX_VECTORS][32];/* Interrupts name */
0089     u8 is_irq_reg[OTX2_CPT_LF_MSIX_VECTORS];  /* Is interrupt registered */
0090     u8 slot;                                /* Slot number of this LF */
0091 
0092     struct otx2_cpt_inst_queue iqueue;/* Instruction queue */
0093     struct otx2_cpt_pending_queue pqueue; /* Pending queue */
0094     struct otx2_cptlf_wqe *wqe;       /* Tasklet work info */
0095 };
0096 
0097 struct cpt_hw_ops {
0098     void (*send_cmd)(union otx2_cpt_inst_s *cptinst, u32 insts_num,
0099              struct otx2_cptlf_info *lf);
0100     u8 (*cpt_get_compcode)(union otx2_cpt_res_s *result);
0101     u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s *result);
0102 };
0103 
0104 struct otx2_cptlfs_info {
0105     /* Registers start address of VF/PF LFs are attached to */
0106     void __iomem *reg_base;
0107 #define LMTLINE_SIZE  128
0108     void __iomem *lmt_base;
0109     struct pci_dev *pdev;   /* Device LFs are attached to */
0110     struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM];
0111     struct otx2_mbox *mbox;
0112     struct cpt_hw_ops *ops;
0113     u8 are_lfs_attached;    /* Whether CPT LFs are attached */
0114     u8 lfs_num;     /* Number of CPT LFs */
0115     u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */
0116     u8 kvf_limits;          /* Kernel crypto limits */
0117     atomic_t state;         /* LF's state. started/reset */
0118     int blkaddr;            /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */
0119 };
0120 
0121 static inline void otx2_cpt_free_instruction_queues(
0122                     struct otx2_cptlfs_info *lfs)
0123 {
0124     struct otx2_cpt_inst_queue *iq;
0125     int i;
0126 
0127     for (i = 0; i < lfs->lfs_num; i++) {
0128         iq = &lfs->lf[i].iqueue;
0129         if (iq->real_vaddr)
0130             dma_free_coherent(&lfs->pdev->dev,
0131                       iq->size,
0132                       iq->real_vaddr,
0133                       iq->real_dma_addr);
0134         iq->real_vaddr = NULL;
0135         iq->vaddr = NULL;
0136     }
0137 }
0138 
0139 static inline int otx2_cpt_alloc_instruction_queues(
0140                     struct otx2_cptlfs_info *lfs)
0141 {
0142     struct otx2_cpt_inst_queue *iq;
0143     int ret = 0, i;
0144 
0145     if (!lfs->lfs_num)
0146         return -EINVAL;
0147 
0148     for (i = 0; i < lfs->lfs_num; i++) {
0149         iq = &lfs->lf[i].iqueue;
0150         iq->size = OTX2_CPT_INST_QLEN_BYTES +
0151                OTX2_CPT_Q_FC_LEN +
0152                OTX2_CPT_INST_GRP_QLEN_BYTES +
0153                OTX2_CPT_INST_Q_ALIGNMENT;
0154         iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size,
0155                     &iq->real_dma_addr, GFP_KERNEL);
0156         if (!iq->real_vaddr) {
0157             ret = -ENOMEM;
0158             goto error;
0159         }
0160         iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES;
0161         iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES;
0162 
0163         /* Align pointers */
0164         iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT);
0165         iq->dma_addr = PTR_ALIGN(iq->dma_addr,
0166                      OTX2_CPT_INST_Q_ALIGNMENT);
0167     }
0168     return 0;
0169 
0170 error:
0171     otx2_cpt_free_instruction_queues(lfs);
0172     return ret;
0173 }
0174 
0175 static inline void otx2_cptlf_set_iqueues_base_addr(
0176                     struct otx2_cptlfs_info *lfs)
0177 {
0178     union otx2_cptx_lf_q_base lf_q_base;
0179     int slot;
0180 
0181     for (slot = 0; slot < lfs->lfs_num; slot++) {
0182         lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;
0183         otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
0184                  OTX2_CPT_LF_Q_BASE, lf_q_base.u);
0185     }
0186 }
0187 
0188 static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf)
0189 {
0190     union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 };
0191 
0192     lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 +
0193                  OTX2_CPT_EXTRA_SIZE_DIV40;
0194     otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
0195              OTX2_CPT_LF_Q_SIZE, lf_q_size.u);
0196 }
0197 
0198 static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs)
0199 {
0200     int slot;
0201 
0202     for (slot = 0; slot < lfs->lfs_num; slot++)
0203         otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]);
0204 }
0205 
0206 static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf)
0207 {
0208     union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };
0209     union otx2_cptx_lf_inprog lf_inprog;
0210     int timeout = 20;
0211 
0212     /* Disable instructions enqueuing */
0213     otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
0214              OTX2_CPT_LF_CTL, lf_ctl.u);
0215 
0216     /* Wait for instruction queue to become empty */
0217     do {
0218         lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,
0219                           lf->slot, OTX2_CPT_LF_INPROG);
0220         if (!lf_inprog.s.inflight)
0221             break;
0222 
0223         usleep_range(10000, 20000);
0224         if (timeout-- < 0) {
0225             dev_err(&lf->lfs->pdev->dev,
0226                 "Error LF %d is still busy.\n", lf->slot);
0227             break;
0228         }
0229 
0230     } while (1);
0231 
0232     /*
0233      * Disable executions in the LF's queue,
0234      * the queue should be empty at this point
0235      */
0236     lf_inprog.s.eena = 0x0;
0237     otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
0238              OTX2_CPT_LF_INPROG, lf_inprog.u);
0239 }
0240 
0241 static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs)
0242 {
0243     int slot;
0244 
0245     for (slot = 0; slot < lfs->lfs_num; slot++)
0246         otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]);
0247 }
0248 
0249 static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,
0250                          bool enable)
0251 {
0252     union otx2_cptx_lf_ctl lf_ctl;
0253 
0254     lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
0255                    OTX2_CPT_LF_CTL);
0256 
0257     /* Set iqueue's enqueuing */
0258     lf_ctl.s.ena = enable ? 0x1 : 0x0;
0259     otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
0260              OTX2_CPT_LF_CTL, lf_ctl.u);
0261 }
0262 
0263 static inline void otx2_cptlf_enable_iqueue_enq(struct otx2_cptlf_info *lf)
0264 {
0265     otx2_cptlf_set_iqueue_enq(lf, true);
0266 }
0267 
0268 static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf,
0269                           bool enable)
0270 {
0271     union otx2_cptx_lf_inprog lf_inprog;
0272 
0273     lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
0274                       OTX2_CPT_LF_INPROG);
0275 
0276     /* Set iqueue's execution */
0277     lf_inprog.s.eena = enable ? 0x1 : 0x0;
0278     otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
0279              OTX2_CPT_LF_INPROG, lf_inprog.u);
0280 }
0281 
0282 static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf)
0283 {
0284     otx2_cptlf_set_iqueue_exec(lf, true);
0285 }
0286 
0287 static inline void otx2_cptlf_disable_iqueue_exec(struct otx2_cptlf_info *lf)
0288 {
0289     otx2_cptlf_set_iqueue_exec(lf, false);
0290 }
0291 
0292 static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs)
0293 {
0294     int slot;
0295 
0296     for (slot = 0; slot < lfs->lfs_num; slot++) {
0297         otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]);
0298         otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]);
0299     }
0300 }
0301 
0302 static inline void otx2_cpt_fill_inst(union otx2_cpt_inst_s *cptinst,
0303                       struct otx2_cpt_iq_command *iq_cmd,
0304                       u64 comp_baddr)
0305 {
0306     cptinst->u[0] = 0x0;
0307     cptinst->s.doneint = true;
0308     cptinst->s.res_addr = comp_baddr;
0309     cptinst->u[2] = 0x0;
0310     cptinst->u[3] = 0x0;
0311     cptinst->s.ei0 = iq_cmd->cmd.u;
0312     cptinst->s.ei1 = iq_cmd->dptr;
0313     cptinst->s.ei2 = iq_cmd->rptr;
0314     cptinst->s.ei3 = iq_cmd->cptr.u;
0315 }
0316 
0317 /*
0318  * On OcteonTX2 platform the parameter insts_num is used as a count of
0319  * instructions to be enqueued. The valid values for insts_num are:
0320  * 1 - 1 CPT instruction will be enqueued during LMTST operation
0321  * 2 - 2 CPT instructions will be enqueued during LMTST operation
0322  */
0323 static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst,
0324                      u32 insts_num, struct otx2_cptlf_info *lf)
0325 {
0326     void __iomem *lmtline = lf->lmtline;
0327     long ret;
0328 
0329     /*
0330      * Make sure memory areas pointed in CPT_INST_S
0331      * are flushed before the instruction is sent to CPT
0332      */
0333     dma_wmb();
0334 
0335     do {
0336         /* Copy CPT command to LMTLINE */
0337         memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
0338 
0339         /*
0340          * LDEOR initiates atomic transfer to I/O device
0341          * The following will cause the LMTST to fail (the LDEOR
0342          * returns zero):
0343          * - No stores have been performed to the LMTLINE since it was
0344          * last invalidated.
0345          * - The bytes which have been stored to LMTLINE since it was
0346          * last invalidated form a pattern that is non-contiguous, does
0347          * not start at byte 0, or does not end on a 8-byte boundary.
0348          * (i.e.comprises a formation of other than 1–16 8-byte
0349          * words.)
0350          *
0351          * These rules are designed such that an operating system
0352          * context switch or hypervisor guest switch need have no
0353          * knowledge of the LMTST operations; the switch code does not
0354          * need to store to LMTCANCEL. Also note as LMTLINE data cannot
0355          * be read, there is no information leakage between processes.
0356          */
0357         ret = otx2_lmt_flush(lf->ioreg);
0358 
0359     } while (!ret);
0360 }
0361 
0362 static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs)
0363 {
0364     return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;
0365 }
0366 
0367 int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
0368             int lfs_num);
0369 void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);
0370 int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs);
0371 void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs);
0372 void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs);
0373 int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs);
0374 
0375 #endif /* __OTX2_CPTLF_H */
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