marvell/octeontx2/otx2_cpt_reqmgr.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  * Copyright (C) 2020 Marvell.
0003  */
0004
0005 #ifndef __OTX2_CPT_REQMGR_H
0006 #define __OTX2_CPT_REQMGR_H
0007
0008 #include "otx2_cpt_common.h"
0009
0010 /* Completion code size and initial value */
0011 #define OTX2_CPT_COMPLETION_CODE_SIZE 8
0012 #define OTX2_CPT_COMPLETION_CODE_INIT OTX2_CPT_COMP_E_NOTDONE
0013 /*
0014  * Maximum total number of SG buffers is 100, we divide it equally
0015  * between input and output
0016  */
0017 #define OTX2_CPT_MAX_SG_IN_CNT  50
0018 #define OTX2_CPT_MAX_SG_OUT_CNT 50
0019
0020 /* DMA mode direct or SG */
0021 #define OTX2_CPT_DMA_MODE_DIRECT 0
0022 #define OTX2_CPT_DMA_MODE_SG     1
0023
0024 /* Context source CPTR or DPTR */
0025 #define OTX2_CPT_FROM_CPTR 0
0026 #define OTX2_CPT_FROM_DPTR 1
0027
0028 #define OTX2_CPT_MAX_REQ_SIZE 65535
0029
0030 union otx2_cpt_opcode {
0031     u16 flags;
0032     struct {
0033         u8 major;
0034         u8 minor;
0035     } s;
0036 };
0037
0038 struct otx2_cptvf_request {
0039     u32 param1;
0040     u32 param2;
0041     u16 dlen;
0042     union otx2_cpt_opcode opcode;
0043 };
0044
0045 /*
0046  * CPT_INST_S software command definitions
0047  * Words EI (0-3)
0048  */
0049 union otx2_cpt_iq_cmd_word0 {
0050     u64 u;
0051     struct {
0052         __be16 opcode;
0053         __be16 param1;
0054         __be16 param2;
0055         __be16 dlen;
0056     } s;
0057 };
0058
0059 union otx2_cpt_iq_cmd_word3 {
0060     u64 u;
0061     struct {
0062         u64 cptr:61;
0063         u64 grp:3;
0064     } s;
0065 };
0066
0067 struct otx2_cpt_iq_command {
0068     union otx2_cpt_iq_cmd_word0 cmd;
0069     u64 dptr;
0070     u64 rptr;
0071     union otx2_cpt_iq_cmd_word3 cptr;
0072 };
0073
0074 struct otx2_cpt_pending_entry {
0075     void *completion_addr;  /* Completion address */
0076     void *info;
0077     /* Kernel async request callback */
0078     void (*callback)(int status, void *arg1, void *arg2);
0079     struct crypto_async_request *areq; /* Async request callback arg */
0080     u8 resume_sender;   /* Notify sender to resume sending requests */
0081     u8 busy;        /* Entry status (free/busy) */
0082 };
0083
0084 struct otx2_cpt_pending_queue {
0085     struct otx2_cpt_pending_entry *head; /* Head of the queue */
0086     u32 front;      /* Process work from here */
0087     u32 rear;       /* Append new work here */
0088     u32 pending_count;  /* Pending requests count */
0089     u32 qlen;       /* Queue length */
0090     spinlock_t lock;    /* Queue lock */
0091 };
0092
0093 struct otx2_cpt_buf_ptr {
0094     u8 *vptr;
0095     dma_addr_t dma_addr;
0096     u16 size;
0097 };
0098
0099 union otx2_cpt_ctrl_info {
0100     u32 flags;
0101     struct {
0102 #if defined(__BIG_ENDIAN_BITFIELD)
0103         u32 reserved_6_31:26;
0104         u32 grp:3;  /* Group bits */
0105         u32 dma_mode:2; /* DMA mode */
0106         u32 se_req:1;   /* To SE core */
0107 #else
0108         u32 se_req:1;   /* To SE core */
0109         u32 dma_mode:2; /* DMA mode */
0110         u32 grp:3;  /* Group bits */
0111         u32 reserved_6_31:26;
0112 #endif
0113     } s;
0114 };
0115
0116 struct otx2_cpt_req_info {
0117     /* Kernel async request callback */
0118     void (*callback)(int status, void *arg1, void *arg2);
0119     struct crypto_async_request *areq; /* Async request callback arg */
0120     struct otx2_cptvf_request req;/* Request information (core specific) */
0121     union otx2_cpt_ctrl_info ctrl;/* User control information */
0122     struct otx2_cpt_buf_ptr in[OTX2_CPT_MAX_SG_IN_CNT];
0123     struct otx2_cpt_buf_ptr out[OTX2_CPT_MAX_SG_OUT_CNT];
0124     u8 *iv_out;     /* IV to send back */
0125     u16 rlen;   /* Output length */
0126     u8 in_cnt;  /* Number of input buffers */
0127     u8 out_cnt; /* Number of output buffers */
0128     u8 req_type;    /* Type of request */
0129     u8 is_enc;  /* Is a request an encryption request */
0130     u8 is_trunc_hmac;/* Is truncated hmac used */
0131 };
0132
0133 struct otx2_cpt_inst_info {
0134     struct otx2_cpt_pending_entry *pentry;
0135     struct otx2_cpt_req_info *req;
0136     struct pci_dev *pdev;
0137     void *completion_addr;
0138     u8 *out_buffer;
0139     u8 *in_buffer;
0140     dma_addr_t dptr_baddr;
0141     dma_addr_t rptr_baddr;
0142     dma_addr_t comp_baddr;
0143     unsigned long time_in;
0144     u32 dlen;
0145     u32 dma_len;
0146     u8 extra_time;
0147 };
0148
0149 struct otx2_cpt_sglist_component {
0150     __be16 len0;
0151     __be16 len1;
0152     __be16 len2;
0153     __be16 len3;
0154     __be64 ptr0;
0155     __be64 ptr1;
0156     __be64 ptr2;
0157     __be64 ptr3;
0158 };
0159
0160 static inline void otx2_cpt_info_destroy(struct pci_dev *pdev,
0161                      struct otx2_cpt_inst_info *info)
0162 {
0163     struct otx2_cpt_req_info *req;
0164     int i;
0165
0166     if (info->dptr_baddr)
0167         dma_unmap_single(&pdev->dev, info->dptr_baddr,
0168                  info->dma_len, DMA_BIDIRECTIONAL);
0169
0170     if (info->req) {
0171         req = info->req;
0172         for (i = 0; i < req->out_cnt; i++) {
0173             if (req->out[i].dma_addr)
0174                 dma_unmap_single(&pdev->dev,
0175                          req->out[i].dma_addr,
0176                          req->out[i].size,
0177                          DMA_BIDIRECTIONAL);
0178         }
0179
0180         for (i = 0; i < req->in_cnt; i++) {
0181             if (req->in[i].dma_addr)
0182                 dma_unmap_single(&pdev->dev,
0183                          req->in[i].dma_addr,
0184                          req->in[i].size,
0185                          DMA_BIDIRECTIONAL);
0186         }
0187     }
0188     kfree(info);
0189 }
0190
0191 struct otx2_cptlf_wqe;
0192 int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
0193             int cpu_num);
0194 void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe);
0195 int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev);
0196
0197 #endif /* __OTX2_CPT_REQMGR_H */