0001
0002
0003
0004 #include "otx2_cpt_common.h"
0005 #include "otx2_cptlf.h"
0006
0007 int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)
0008 {
0009 int ret;
0010
0011 otx2_mbox_msg_send(mbox, 0);
0012 ret = otx2_mbox_wait_for_rsp(mbox, 0);
0013 if (ret == -EIO) {
0014 dev_err(&pdev->dev, "RVU MBOX timeout.\n");
0015 return ret;
0016 } else if (ret) {
0017 dev_err(&pdev->dev, "RVU MBOX error: %d.\n", ret);
0018 return -EFAULT;
0019 }
0020 return ret;
0021 }
0022
0023 int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)
0024 {
0025 struct mbox_msghdr *req;
0026
0027 req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
0028 sizeof(struct ready_msg_rsp));
0029 if (req == NULL) {
0030 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
0031 return -EFAULT;
0032 }
0033 req->id = MBOX_MSG_READY;
0034 req->sig = OTX2_MBOX_REQ_SIG;
0035 req->pcifunc = 0;
0036
0037 return otx2_cpt_send_mbox_msg(mbox, pdev);
0038 }
0039
0040 int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev)
0041 {
0042 return otx2_cpt_send_mbox_msg(mbox, pdev);
0043 }
0044
0045 int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0046 u64 reg, u64 *val, int blkaddr)
0047 {
0048 struct cpt_rd_wr_reg_msg *reg_msg;
0049
0050 reg_msg = (struct cpt_rd_wr_reg_msg *)
0051 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),
0052 sizeof(*reg_msg));
0053 if (reg_msg == NULL) {
0054 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
0055 return -EFAULT;
0056 }
0057
0058 reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
0059 reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;
0060 reg_msg->hdr.pcifunc = 0;
0061
0062 reg_msg->is_write = 0;
0063 reg_msg->reg_offset = reg;
0064 reg_msg->ret_val = val;
0065 reg_msg->blkaddr = blkaddr;
0066
0067 return 0;
0068 }
0069
0070 int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0071 u64 reg, u64 val, int blkaddr)
0072 {
0073 struct cpt_rd_wr_reg_msg *reg_msg;
0074
0075 reg_msg = (struct cpt_rd_wr_reg_msg *)
0076 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),
0077 sizeof(*reg_msg));
0078 if (reg_msg == NULL) {
0079 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
0080 return -EFAULT;
0081 }
0082
0083 reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
0084 reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;
0085 reg_msg->hdr.pcifunc = 0;
0086
0087 reg_msg->is_write = 1;
0088 reg_msg->reg_offset = reg;
0089 reg_msg->val = val;
0090 reg_msg->blkaddr = blkaddr;
0091
0092 return 0;
0093 }
0094
0095 int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0096 u64 reg, u64 *val, int blkaddr)
0097 {
0098 int ret;
0099
0100 ret = otx2_cpt_add_read_af_reg(mbox, pdev, reg, val, blkaddr);
0101 if (ret)
0102 return ret;
0103
0104 return otx2_cpt_send_mbox_msg(mbox, pdev);
0105 }
0106
0107 int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0108 u64 reg, u64 val, int blkaddr)
0109 {
0110 int ret;
0111
0112 ret = otx2_cpt_add_write_af_reg(mbox, pdev, reg, val, blkaddr);
0113 if (ret)
0114 return ret;
0115
0116 return otx2_cpt_send_mbox_msg(mbox, pdev);
0117 }
0118
0119 int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs)
0120 {
0121 struct otx2_mbox *mbox = lfs->mbox;
0122 struct rsrc_attach *req;
0123 int ret;
0124
0125 req = (struct rsrc_attach *)
0126 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
0127 sizeof(struct msg_rsp));
0128 if (req == NULL) {
0129 dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");
0130 return -EFAULT;
0131 }
0132
0133 req->hdr.id = MBOX_MSG_ATTACH_RESOURCES;
0134 req->hdr.sig = OTX2_MBOX_REQ_SIG;
0135 req->hdr.pcifunc = 0;
0136 req->cptlfs = lfs->lfs_num;
0137 ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
0138 if (ret)
0139 return ret;
0140
0141 if (!lfs->are_lfs_attached)
0142 ret = -EINVAL;
0143
0144 return ret;
0145 }
0146
0147 int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs)
0148 {
0149 struct otx2_mbox *mbox = lfs->mbox;
0150 struct rsrc_detach *req;
0151 int ret;
0152
0153 req = (struct rsrc_detach *)
0154 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
0155 sizeof(struct msg_rsp));
0156 if (req == NULL) {
0157 dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");
0158 return -EFAULT;
0159 }
0160
0161 req->hdr.id = MBOX_MSG_DETACH_RESOURCES;
0162 req->hdr.sig = OTX2_MBOX_REQ_SIG;
0163 req->hdr.pcifunc = 0;
0164 ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
0165 if (ret)
0166 return ret;
0167
0168 if (lfs->are_lfs_attached)
0169 ret = -EINVAL;
0170
0171 return ret;
0172 }
0173
0174 int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs)
0175 {
0176 struct otx2_mbox *mbox = lfs->mbox;
0177 struct pci_dev *pdev = lfs->pdev;
0178 struct mbox_msghdr *req;
0179 int ret, i;
0180
0181 req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
0182 sizeof(struct msix_offset_rsp));
0183 if (req == NULL) {
0184 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
0185 return -EFAULT;
0186 }
0187
0188 req->id = MBOX_MSG_MSIX_OFFSET;
0189 req->sig = OTX2_MBOX_REQ_SIG;
0190 req->pcifunc = 0;
0191 ret = otx2_cpt_send_mbox_msg(mbox, pdev);
0192 if (ret)
0193 return ret;
0194
0195 for (i = 0; i < lfs->lfs_num; i++) {
0196 if (lfs->lf[i].msix_offset == MSIX_VECTOR_INVALID) {
0197 dev_err(&pdev->dev,
0198 "Invalid msix offset %d for LF %d\n",
0199 lfs->lf[i].msix_offset, i);
0200 return -EINVAL;
0201 }
0202 }
0203 return ret;
0204 }
0205
0206 int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox)
0207 {
0208 int err;
0209
0210 if (!otx2_mbox_nonempty(mbox, 0))
0211 return 0;
0212 otx2_mbox_msg_send(mbox, 0);
0213 err = otx2_mbox_wait_for_rsp(mbox, 0);
0214 if (err)
0215 return err;
0216
0217 return otx2_mbox_check_rsp_msgs(mbox, 0);
0218 }
