marvell/octeontx2/otx2_cpt_common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  * Copyright (C) 2020 Marvell.
0003  */
0004
0005 #ifndef __OTX2_CPT_COMMON_H
0006 #define __OTX2_CPT_COMMON_H
0007
0008 #include <linux/pci.h>
0009 #include <linux/types.h>
0010 #include <linux/module.h>
0011 #include <linux/delay.h>
0012 #include <linux/crypto.h>
0013 #include <net/devlink.h>
0014 #include "otx2_cpt_hw_types.h"
0015 #include "rvu.h"
0016 #include "mbox.h"
0017
0018 #define OTX2_CPT_MAX_VFS_NUM 128
0019 #define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \
0020         (((blk) << 20) | ((slot) << 12) | (offs))
0021 #define OTX2_CPT_RVU_PFFUNC(pf, func)   \
0022         ((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) | \
0023         (((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT))
0024
0025 #define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF
0026 #define OTX2_CPT_NAME_LENGTH 64
0027 #define OTX2_CPT_DMA_MINALIGN 128
0028
0029 /* HW capability flags */
0030 #define CN10K_MBOX  0
0031 #define CN10K_LMTST 1
0032
0033 #define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES
0034
0035 enum otx2_cpt_eng_type {
0036     OTX2_CPT_AE_TYPES = 1,
0037     OTX2_CPT_SE_TYPES = 2,
0038     OTX2_CPT_IE_TYPES = 3,
0039     OTX2_CPT_MAX_ENG_TYPES,
0040 };
0041
0042 /* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
0043 #define MBOX_MSG_GET_ENG_GRP_NUM        0xBFF
0044 #define MBOX_MSG_GET_CAPS               0xBFD
0045 #define MBOX_MSG_GET_KVF_LIMITS         0xBFC
0046
0047 /*
0048  * Message request and response to get engine group number
0049  * which has attached a given type of engines (SE, AE, IE)
0050  * This messages are only used between CPT PF <=> CPT VF
0051  */
0052 struct otx2_cpt_egrp_num_msg {
0053     struct mbox_msghdr hdr;
0054     u8 eng_type;
0055 };
0056
0057 struct otx2_cpt_egrp_num_rsp {
0058     struct mbox_msghdr hdr;
0059     u8 eng_type;
0060     u8 eng_grp_num;
0061 };
0062
0063 /*
0064  * Message request and response to get kernel crypto limits
0065  * This messages are only used between CPT PF <-> CPT VF
0066  */
0067 struct otx2_cpt_kvf_limits_msg {
0068     struct mbox_msghdr hdr;
0069 };
0070
0071 struct otx2_cpt_kvf_limits_rsp {
0072     struct mbox_msghdr hdr;
0073     u8 kvf_limits;
0074 };
0075
0076 /* CPT HW capabilities */
0077 union otx2_cpt_eng_caps {
0078     u64 u;
0079     struct {
0080         u64 reserved_0_4:5;
0081         u64 mul:1;
0082         u64 sha1_sha2:1;
0083         u64 chacha20:1;
0084         u64 zuc_snow3g:1;
0085         u64 sha3:1;
0086         u64 aes:1;
0087         u64 kasumi:1;
0088         u64 des:1;
0089         u64 crc:1;
0090         u64 reserved_14_63:50;
0091     };
0092 };
0093
0094 /*
0095  * Message request and response to get HW capabilities for each
0096  * engine type (SE, IE, AE).
0097  * This messages are only used between CPT PF <=> CPT VF
0098  */
0099 struct otx2_cpt_caps_msg {
0100     struct mbox_msghdr hdr;
0101 };
0102
0103 struct otx2_cpt_caps_rsp {
0104     struct mbox_msghdr hdr;
0105     u16 cpt_pf_drv_version;
0106     u8 cpt_revision;
0107     union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
0108 };
0109
0110 static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot,
0111                     u64 offs, u64 val)
0112 {
0113     writeq_relaxed(val, reg_base +
0114                OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs));
0115 }
0116
0117 static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot,
0118                   u64 offs)
0119 {
0120     return readq_relaxed(reg_base +
0121                  OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs));
0122 }
0123
0124 static inline bool is_dev_otx2(struct pci_dev *pdev)
0125 {
0126     if (pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID ||
0127         pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID)
0128         return true;
0129
0130     return false;
0131 }
0132
0133 static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
0134                     unsigned long *cap_flag)
0135 {
0136     if (!is_dev_otx2(pdev)) {
0137         __set_bit(CN10K_MBOX, cap_flag);
0138         __set_bit(CN10K_LMTST, cap_flag);
0139     }
0140 }
0141
0142
0143 int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
0144 int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
0145
0146 int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox,
0147                   struct pci_dev *pdev);
0148 int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0149                  u64 reg, u64 *val, int blkaddr);
0150 int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0151                   u64 reg, u64 val, int blkaddr);
0152 int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0153              u64 reg, u64 *val, int blkaddr);
0154 int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
0155               u64 reg, u64 val, int blkaddr);
0156 struct otx2_cptlfs_info;
0157 int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);
0158 int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
0159 int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
0160 int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);
0161
0162 #endif /* __OTX2_CPT_COMMON_H */