marvell/octeontx2/cn10k_cpt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (C) 2021 Marvell. */
0003
0004 #include <linux/soc/marvell/octeontx2/asm.h>
0005 #include "otx2_cptpf.h"
0006 #include "otx2_cptvf.h"
0007 #include "otx2_cptlf.h"
0008 #include "cn10k_cpt.h"
0009
0010 static struct cpt_hw_ops otx2_hw_ops = {
0011     .send_cmd = otx2_cpt_send_cmd,
0012     .cpt_get_compcode = otx2_cpt_get_compcode,
0013     .cpt_get_uc_compcode = otx2_cpt_get_uc_compcode,
0014 };
0015
0016 static struct cpt_hw_ops cn10k_hw_ops = {
0017     .send_cmd = cn10k_cpt_send_cmd,
0018     .cpt_get_compcode = cn10k_cpt_get_compcode,
0019     .cpt_get_uc_compcode = cn10k_cpt_get_uc_compcode,
0020 };
0021
0022 void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
0023             struct otx2_cptlf_info *lf)
0024 {
0025     void __iomem *lmtline = lf->lmtline;
0026     u64 val = (lf->slot & 0x7FF);
0027     u64 tar_addr = 0;
0028
0029     /* tar_addr<6:4> = Size of first LMTST - 1 in units of 128b. */
0030     tar_addr |= (__force u64)lf->ioreg |
0031             (((OTX2_CPT_INST_SIZE/16) - 1) & 0x7) << 4;
0032     /*
0033      * Make sure memory areas pointed in CPT_INST_S
0034      * are flushed before the instruction is sent to CPT
0035      */
0036     dma_wmb();
0037
0038     /* Copy CPT command to LMTLINE */
0039     memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
0040     cn10k_lmt_flush(val, tar_addr);
0041 }
0042
0043 int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)
0044 {
0045     struct pci_dev *pdev = cptpf->pdev;
0046     resource_size_t size;
0047     u64 lmt_base;
0048
0049     if (!test_bit(CN10K_LMTST, &cptpf->cap_flag)) {
0050         cptpf->lfs.ops = &otx2_hw_ops;
0051         return 0;
0052     }
0053
0054     cptpf->lfs.ops = &cn10k_hw_ops;
0055     lmt_base = readq(cptpf->reg_base + RVU_PF_LMTLINE_ADDR);
0056     if (!lmt_base) {
0057         dev_err(&pdev->dev, "PF LMTLINE address not configured\n");
0058         return -ENOMEM;
0059     }
0060     size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
0061     size -= ((1 + cptpf->max_vfs) * MBOX_SIZE);
0062     cptpf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, lmt_base, size);
0063     if (!cptpf->lfs.lmt_base) {
0064         dev_err(&pdev->dev,
0065             "Mapping of PF LMTLINE address failed\n");
0066         return -ENOMEM;
0067     }
0068
0069     return 0;
0070 }
0071
0072 int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)
0073 {
0074     struct pci_dev *pdev = cptvf->pdev;
0075     resource_size_t offset, size;
0076
0077     if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) {
0078         cptvf->lfs.ops = &otx2_hw_ops;
0079         return 0;
0080     }
0081
0082     cptvf->lfs.ops = &cn10k_hw_ops;
0083     offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
0084     size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
0085     /* Map VF LMILINE region */
0086     cptvf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, offset, size);
0087     if (!cptvf->lfs.lmt_base) {
0088         dev_err(&pdev->dev, "Unable to map BAR4\n");
0089         return -ENOMEM;
0090     }
0091
0092     return 0;
0093 }