marvell/octeontx/otx_cptvf.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  * Marvell OcteonTX CPT driver
0003  *
0004  * Copyright (C) 2019 Marvell International Ltd.
0005  *
0006  * This program is free software; you can redistribute it and/or modify
0007  * it under the terms of the GNU General Public License version 2 as
0008  * published by the Free Software Foundation.
0009  */
0010
0011 #ifndef __OTX_CPTVF_H
0012 #define __OTX_CPTVF_H
0013
0014 #include <linux/list.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/device.h>
0017 #include "otx_cpt_common.h"
0018 #include "otx_cptvf_reqmgr.h"
0019
0020 /* Flags to indicate the features supported */
0021 #define OTX_CPT_FLAG_DEVICE_READY  BIT(1)
0022 #define otx_cpt_device_ready(cpt)  ((cpt)->flags & OTX_CPT_FLAG_DEVICE_READY)
0023 /* Default command queue length */
0024 #define OTX_CPT_CMD_QLEN    (4*2046)
0025 #define OTX_CPT_CMD_QCHUNK_SIZE 1023
0026 #define OTX_CPT_NUM_QS_PER_VF   1
0027
0028 struct otx_cpt_cmd_chunk {
0029     u8 *head;
0030     dma_addr_t dma_addr;
0031     u32 size; /* Chunk size, max OTX_CPT_INST_CHUNK_MAX_SIZE */
0032     struct list_head nextchunk;
0033 };
0034
0035 struct otx_cpt_cmd_queue {
0036     u32 idx;    /* Command queue host write idx */
0037     u32 num_chunks; /* Number of command chunks */
0038     struct otx_cpt_cmd_chunk *qhead;/*
0039                      * Command queue head, instructions
0040                      * are inserted here
0041                      */
0042     struct otx_cpt_cmd_chunk *base;
0043     struct list_head chead;
0044 };
0045
0046 struct otx_cpt_cmd_qinfo {
0047     u32 qchunksize; /* Command queue chunk size */
0048     struct otx_cpt_cmd_queue queue[OTX_CPT_NUM_QS_PER_VF];
0049 };
0050
0051 struct otx_cpt_pending_qinfo {
0052     u32 num_queues; /* Number of queues supported */
0053     struct otx_cpt_pending_queue queue[OTX_CPT_NUM_QS_PER_VF];
0054 };
0055
0056 #define for_each_pending_queue(qinfo, q, i) \
0057         for (i = 0, q = &qinfo->queue[i]; i < qinfo->num_queues; i++, \
0058              q = &qinfo->queue[i])
0059
0060 struct otx_cptvf_wqe {
0061     struct tasklet_struct twork;
0062     struct otx_cptvf *cptvf;
0063 };
0064
0065 struct otx_cptvf_wqe_info {
0066     struct otx_cptvf_wqe vq_wqe[OTX_CPT_NUM_QS_PER_VF];
0067 };
0068
0069 struct otx_cptvf {
0070     u16 flags;  /* Flags to hold device status bits */
0071     u8 vfid;    /* Device Index 0...OTX_CPT_MAX_VF_NUM */
0072     u8 num_vfs; /* Number of enabled VFs */
0073     u8 vftype;  /* VF type of SE_TYPE(2) or AE_TYPE(1) */
0074     u8 vfgrp;   /* VF group (0 - 8) */
0075     u8 node;    /* Operating node: Bits (46:44) in BAR0 address */
0076     u8 priority;    /*
0077              * VF priority ring: 1-High proirity round
0078              * robin ring;0-Low priority round robin ring;
0079              */
0080     struct pci_dev *pdev;   /* Pci device handle */
0081     void __iomem *reg_base; /* Register start address */
0082     void *wqe_info;     /* BH worker info */
0083     /* MSI-X */
0084     cpumask_var_t affinity_mask[OTX_CPT_VF_MSIX_VECTORS];
0085     /* Command and Pending queues */
0086     u32 qsize;
0087     u32 num_queues;
0088     struct otx_cpt_cmd_qinfo cqinfo; /* Command queue information */
0089     struct otx_cpt_pending_qinfo pqinfo; /* Pending queue information */
0090     /* VF-PF mailbox communication */
0091     bool pf_acked;
0092     bool pf_nacked;
0093 };
0094
0095 int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf);
0096 int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf);
0097 int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group);
0098 int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf);
0099 int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf);
0100 int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf);
0101 void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf);
0102 void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val);
0103
0104 #endif /* __OTX_CPTVF_H */