marvell/octeontx/otx_cptpf_ucode.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  * Marvell OcteonTX CPT driver
0003  *
0004  * Copyright (C) 2019 Marvell International Ltd.
0005  *
0006  * This program is free software; you can redistribute it and/or modify
0007  * it under the terms of the GNU General Public License version 2 as
0008  * published by the Free Software Foundation.
0009  */
0010
0011 #ifndef __OTX_CPTPF_UCODE_H
0012 #define __OTX_CPTPF_UCODE_H
0013
0014 #include <linux/pci.h>
0015 #include <linux/types.h>
0016 #include <linux/module.h>
0017 #include "otx_cpt_hw_types.h"
0018
0019 /* CPT ucode name maximum length */
0020 #define OTX_CPT_UCODE_NAME_LENGTH   64
0021 /*
0022  * On OcteonTX 83xx platform, only one type of engines is allowed to be
0023  * attached to an engine group.
0024  */
0025 #define OTX_CPT_MAX_ETYPES_PER_GRP  1
0026
0027 /* Default tar archive file names */
0028 #define OTX_CPT_UCODE_TAR_FILE_NAME "cpt8x-mc.tar"
0029
0030 /* CPT ucode alignment */
0031 #define OTX_CPT_UCODE_ALIGNMENT     128
0032
0033 /* CPT ucode signature size */
0034 #define OTX_CPT_UCODE_SIGN_LEN      256
0035
0036 /* Microcode version string length */
0037 #define OTX_CPT_UCODE_VER_STR_SZ    44
0038
0039 /* Maximum number of supported engines/cores on OcteonTX 83XX platform */
0040 #define OTX_CPT_MAX_ENGINES     64
0041
0042 #define OTX_CPT_ENGS_BITMASK_LEN    (OTX_CPT_MAX_ENGINES/(BITS_PER_BYTE * \
0043                      sizeof(unsigned long)))
0044
0045 /* Microcode types */
0046 enum otx_cpt_ucode_type {
0047     OTX_CPT_AE_UC_TYPE =    1,  /* AE-MAIN */
0048     OTX_CPT_SE_UC_TYPE1 =   20, /* SE-MAIN - combination of 21 and 22 */
0049     OTX_CPT_SE_UC_TYPE2 =   21, /* Fast Path IPSec + AirCrypto */
0050     OTX_CPT_SE_UC_TYPE3 =   22, /*
0051                      * Hash + HMAC + FlexiCrypto + RNG + Full
0052                      * Feature IPSec + AirCrypto + Kasumi
0053                      */
0054 };
0055
0056 struct otx_cpt_bitmap {
0057     unsigned long bits[OTX_CPT_ENGS_BITMASK_LEN];
0058     int size;
0059 };
0060
0061 struct otx_cpt_engines {
0062     int type;
0063     int count;
0064 };
0065
0066 /* Microcode version number */
0067 struct otx_cpt_ucode_ver_num {
0068     u8 nn;
0069     u8 xx;
0070     u8 yy;
0071     u8 zz;
0072 };
0073
0074 struct otx_cpt_ucode_hdr {
0075     struct otx_cpt_ucode_ver_num ver_num;
0076     u8 ver_str[OTX_CPT_UCODE_VER_STR_SZ];
0077     __be32 code_length;
0078     u32 padding[3];
0079 };
0080
0081 struct otx_cpt_ucode {
0082     u8 ver_str[OTX_CPT_UCODE_VER_STR_SZ];/*
0083                           * ucode version in readable format
0084                           */
0085     struct otx_cpt_ucode_ver_num ver_num;/* ucode version number */
0086     char filename[OTX_CPT_UCODE_NAME_LENGTH];    /* ucode filename */
0087     dma_addr_t dma;     /* phys address of ucode image */
0088     dma_addr_t align_dma;   /* aligned phys address of ucode image */
0089     void *va;       /* virt address of ucode image */
0090     void *align_va;     /* aligned virt address of ucode image */
0091     u32 size;       /* ucode image size */
0092     int type;       /* ucode image type SE or AE */
0093 };
0094
0095 struct tar_ucode_info_t {
0096     struct list_head list;
0097     struct otx_cpt_ucode ucode;/* microcode information */
0098     const u8 *ucode_ptr;    /* pointer to microcode in tar archive */
0099 };
0100
0101 /* Maximum and current number of engines available for all engine groups */
0102 struct otx_cpt_engs_available {
0103     int max_se_cnt;
0104     int max_ae_cnt;
0105     int se_cnt;
0106     int ae_cnt;
0107 };
0108
0109 /* Engines reserved to an engine group */
0110 struct otx_cpt_engs_rsvd {
0111     int type;   /* engine type */
0112     int count;  /* number of engines attached */
0113     int offset;     /* constant offset of engine type in the bitmap */
0114     unsigned long *bmap;        /* attached engines bitmap */
0115     struct otx_cpt_ucode *ucode;    /* ucode used by these engines */
0116 };
0117
0118 struct otx_cpt_mirror_info {
0119     int is_ena; /*
0120              * is mirroring enabled, it is set only for engine
0121              * group which mirrors another engine group
0122              */
0123     int idx;    /*
0124              * index of engine group which is mirrored by this
0125              * group, set only for engine group which mirrors
0126              * another group
0127              */
0128     int ref_count;  /*
0129              * number of times this engine group is mirrored by
0130              * other groups, this is set only for engine group
0131              * which is mirrored by other group(s)
0132              */
0133 };
0134
0135 struct otx_cpt_eng_grp_info {
0136     struct otx_cpt_eng_grps *g; /* pointer to engine_groups structure */
0137     struct device_attribute info_attr; /* group info entry attr */
0138     /* engines attached */
0139     struct otx_cpt_engs_rsvd engs[OTX_CPT_MAX_ETYPES_PER_GRP];
0140     /* Microcode information */
0141     struct otx_cpt_ucode ucode[OTX_CPT_MAX_ETYPES_PER_GRP];
0142     /* sysfs info entry name */
0143     char sysfs_info_name[OTX_CPT_UCODE_NAME_LENGTH];
0144     /* engine group mirroring information */
0145     struct otx_cpt_mirror_info mirror;
0146     int idx;     /* engine group index */
0147     bool is_enabled; /*
0148               * is engine group enabled, engine group is enabled
0149               * when it has engines attached and ucode loaded
0150               */
0151 };
0152
0153 struct otx_cpt_eng_grps {
0154     struct otx_cpt_eng_grp_info grp[OTX_CPT_MAX_ENGINE_GROUPS];
0155     struct device_attribute ucode_load_attr;/* ucode load attr */
0156     struct otx_cpt_engs_available avail;
0157     struct mutex lock;
0158     void *obj;
0159     int engs_num;           /* total number of engines supported */
0160     int eng_types_supported;    /* engine types supported SE, AE */
0161     u8 eng_ref_cnt[OTX_CPT_MAX_ENGINES];/* engines reference count */
0162     bool is_ucode_load_created; /* is ucode_load sysfs entry created */
0163     bool is_first_try; /* is this first try to create kcrypto engine grp */
0164     bool is_rdonly; /* do engine groups configuration can be modified */
0165 };
0166
0167 int otx_cpt_init_eng_grps(struct pci_dev *pdev,
0168               struct otx_cpt_eng_grps *eng_grps, int pf_type);
0169 void otx_cpt_cleanup_eng_grps(struct pci_dev *pdev,
0170                   struct otx_cpt_eng_grps *eng_grps);
0171 int otx_cpt_try_create_default_eng_grps(struct pci_dev *pdev,
0172                     struct otx_cpt_eng_grps *eng_grps,
0173                     int pf_type);
0174 void otx_cpt_set_eng_grps_is_rdonly(struct otx_cpt_eng_grps *eng_grps,
0175                     bool is_rdonly);
0176 int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type);
0177 int otx_cpt_eng_grp_has_eng_type(struct otx_cpt_eng_grp_info *eng_grp,
0178                  int eng_type);
0179
0180 #endif /* __OTX_CPTPF_UCODE_H */