drivers/crypto/geode-aes.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Copyright (C) 2003-2006, Advanced Micro Devices, Inc.
0003  */
0004
0005 #ifndef _GEODE_AES_H_
0006 #define _GEODE_AES_H_
0007
0008 /* driver logic flags */
0009 #define AES_MODE_ECB 0
0010 #define AES_MODE_CBC 1
0011
0012 #define AES_DIR_DECRYPT 0
0013 #define AES_DIR_ENCRYPT 1
0014
0015 #define AES_FLAGS_HIDDENKEY (1 << 0)
0016
0017 /* Register definitions */
0018
0019 #define AES_CTRLA_REG  0x0000
0020
0021 #define AES_CTRL_START     0x01
0022 #define AES_CTRL_DECRYPT   0x00
0023 #define AES_CTRL_ENCRYPT   0x02
0024 #define AES_CTRL_WRKEY     0x04
0025 #define AES_CTRL_DCA       0x08
0026 #define AES_CTRL_SCA       0x10
0027 #define AES_CTRL_CBC       0x20
0028
0029 #define AES_INTR_REG  0x0008
0030
0031 #define AES_INTRA_PENDING (1 << 16)
0032 #define AES_INTRB_PENDING (1 << 17)
0033
0034 #define AES_INTR_PENDING  (AES_INTRA_PENDING | AES_INTRB_PENDING)
0035 #define AES_INTR_MASK     0x07
0036
0037 #define AES_SOURCEA_REG   0x0010
0038 #define AES_DSTA_REG      0x0014
0039 #define AES_LENA_REG      0x0018
0040 #define AES_WRITEKEY0_REG 0x0030
0041 #define AES_WRITEIV0_REG  0x0040
0042
0043 /*  A very large counter that is used to gracefully bail out of an
0044  *  operation in case of trouble
0045  */
0046
0047 #define AES_OP_TIMEOUT    0x50000
0048
0049 struct geode_aes_tfm_ctx {
0050     u8 key[AES_KEYSIZE_128];
0051     union {
0052         struct crypto_skcipher *skcipher;
0053         struct crypto_cipher *cip;
0054     } fallback;
0055     u32 keylen;
0056 };
0057
0058 #endif