crypto/gemini/sl3516-ce.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
0004  *
0005  * Copyright (C) 2021 Corentin LABBE <clabbe@baylibre.com>
0006  *
0007  * General notes on this driver:
0008  * Called either Crypto Acceleration Engine Module, Security Acceleration Engine
0009  * or IPSEC module in the datasheet, it will be called Crypto Engine for short
0010  * in this driver.
0011  * The CE was designed to handle IPSEC and wifi(TKIP WEP) protocol.
0012  * It can handle AES, DES, 3DES, MD5, WEP, TKIP, SHA1, HMAC(MD5), HMAC(SHA1),
0013  * Michael cipher/digest suites.
0014  * It acts the same as a network hw, with both RX and TX chained descriptors.
0015  */
0016 #include <crypto/aes.h>
0017 #include <crypto/engine.h>
0018 #include <crypto/scatterwalk.h>
0019 #include <crypto/skcipher.h>
0020 #include <linux/crypto.h>
0021 #include <linux/debugfs.h>
0022 #include <linux/hw_random.h>
0023
0024 #define TQ0_TYPE_DATA 0
0025 #define TQ0_TYPE_CTRL BIT(0)
0026 #define TQ1_CIPHER BIT(1)
0027 #define TQ2_AUTH BIT(2)
0028 #define TQ3_IV BIT(3)
0029 #define TQ4_KEY0 BIT(4)
0030 #define TQ5_KEY4 BIT(5)
0031 #define TQ6_KEY6 BIT(6)
0032 #define TQ7_AKEY0 BIT(7)
0033 #define TQ8_AKEY2 BIT(8)
0034 #define TQ9_AKEY2 BIT(9)
0035
0036 #define ECB_AES       0x2
0037
0038 #define DESC_LAST 0x01
0039 #define DESC_FIRST 0x02
0040
0041 #define IPSEC_ID        0x0000
0042 #define IPSEC_STATUS_REG    0x00a8
0043 #define IPSEC_RAND_NUM_REG  0x00ac
0044 #define IPSEC_DMA_DEVICE_ID 0xff00
0045 #define IPSEC_DMA_STATUS    0xff04
0046 #define IPSEC_TXDMA_CTRL    0xff08
0047 #define IPSEC_TXDMA_FIRST_DESC  0xff0c
0048 #define IPSEC_TXDMA_CURR_DESC   0xff10
0049 #define IPSEC_RXDMA_CTRL    0xff14
0050 #define IPSEC_RXDMA_FIRST_DESC  0xff18
0051 #define IPSEC_RXDMA_CURR_DESC   0xff1c
0052 #define IPSEC_TXDMA_BUF_ADDR    0xff28
0053 #define IPSEC_RXDMA_BUF_ADDR    0xff38
0054 #define IPSEC_RXDMA_BUF_SIZE    0xff30
0055
0056 #define CE_ENCRYPTION       0x01
0057 #define CE_DECRYPTION       0x03
0058
0059 #define MAXDESC 6
0060
0061 #define DMA_STATUS_RS_EOFI  BIT(22)
0062 #define DMA_STATUS_RS_PERR  BIT(24)
0063 #define DMA_STATUS_RS_DERR  BIT(25)
0064 #define DMA_STATUS_TS_EOFI  BIT(27)
0065 #define DMA_STATUS_TS_PERR  BIT(29)
0066 #define DMA_STATUS_TS_DERR  BIT(30)
0067
0068 #define TXDMA_CTRL_START BIT(31)
0069 #define TXDMA_CTRL_CONTINUE BIT(30)
0070 #define TXDMA_CTRL_CHAIN_MODE BIT(29)
0071 /* the burst value is not documented in the datasheet */
0072 #define TXDMA_CTRL_BURST_UNK BIT(22)
0073 #define TXDMA_CTRL_INT_FAIL BIT(17)
0074 #define TXDMA_CTRL_INT_PERR BIT(16)
0075
0076 #define RXDMA_CTRL_START BIT(31)
0077 #define RXDMA_CTRL_CONTINUE BIT(30)
0078 #define RXDMA_CTRL_CHAIN_MODE BIT(29)
0079 /* the burst value is not documented in the datasheet */
0080 #define RXDMA_CTRL_BURST_UNK BIT(22)
0081 #define RXDMA_CTRL_INT_FINISH BIT(18)
0082 #define RXDMA_CTRL_INT_FAIL BIT(17)
0083 #define RXDMA_CTRL_INT_PERR BIT(16)
0084 #define RXDMA_CTRL_INT_EOD BIT(15)
0085 #define RXDMA_CTRL_INT_EOF BIT(14)
0086
0087 #define CE_CPU 0
0088 #define CE_DMA 1
0089
0090 /*
0091  * struct sl3516_ce_descriptor - descriptor for CE operations
0092  * @frame_ctrl:     Information for the current descriptor
0093  * @flag_status:    For send packet, describe flag of operations.
0094  * @buf_adr:        pointer to a send/recv buffer for data packet
0095  * @next_desc:      control linking to other descriptors
0096  */
0097 struct descriptor {
0098     union {
0099         u32 raw;
0100         /*
0101          * struct desc_frame_ctrl - Information for the current descriptor
0102          * @buffer_size:    the size of buffer at buf_adr
0103          * @desc_count:     Upon completion of a DMA operation, DMA
0104          *          write the number of descriptors used
0105          *          for the current frame
0106          * @checksum:       unknown
0107          * @authcomp:       unknown
0108          * @perr:       Protocol error during processing this descriptor
0109          * @derr:       Data error during processing this descriptor
0110          * @own:        0 if owned by CPU, 1 for DMA
0111          */
0112         struct desc_frame_ctrl {
0113             u32 buffer_size :16;
0114             u32 desc_count  :6;
0115             u32 checksum    :6;
0116             u32 authcomp    :1;
0117             u32 perr    :1;
0118             u32 derr    :1;
0119             u32 own     :1;
0120         } bits;
0121     } frame_ctrl;
0122
0123     union {
0124         u32 raw;
0125         /*
0126          * struct desc_flag_status - flag for this descriptor
0127          * @tqflag: list of flag describing the type of operation
0128          *      to be performed.
0129          */
0130         struct desc_tx_flag_status {
0131             u32 tqflag  :10;
0132             u32 unused  :22;
0133         } tx_flag;
0134     } flag_status;
0135
0136     u32 buf_adr;
0137
0138     union {
0139         u32 next_descriptor;
0140         /*
0141          * struct desc_next - describe chaining of descriptors
0142          * @sof_eof:    does the descriptor is first (0x11),
0143          *      the last (0x01), middle of a chan (0x00)
0144          *      or the only one (0x11)
0145          * @dec:    AHB bus address increase (0), decrease (1)
0146          * @eofie:  End of frame interrupt enable
0147          * @ndar:   Next descriptor address
0148          */
0149         struct desc_next {
0150             u32 sof_eof :2;
0151             u32 dec     :1;
0152             u32 eofie   :1;
0153             u32 ndar    :28;
0154         } bits;
0155     } next_desc;
0156 };
0157
0158 /*
0159  * struct control - The value of this register is used to set the
0160  *          operation mode of the IPSec Module.
0161  * @process_id:     Used to identify the process. The number will be copied
0162  *          to the descriptor status of the received packet.
0163  * @auth_check_len: Number of 32-bit words to be checked or appended by the
0164  *          authentication module
0165  * @auth_algorithm:
0166  * @auth_mode:      0:append 1:Check Authentication Result
0167  * @fcs_stream_copy:    0:enable 1:disable authentication stream copy
0168  * @mix_key_sel:    0:use rCipherKey0-3  1:use Key Mixer
0169  * @aesnk:      AES Key Size
0170  * @cipher_algorithm:   choice of CBC/ECE and AES/DES/3DES
0171  * @op_mode:        Operation Mode for the IPSec Module
0172  */
0173 struct pkt_control_header {
0174     u32 process_id      :8;
0175     u32 auth_check_len  :3;
0176     u32 un1         :1;
0177     u32 auth_algorithm  :3;
0178     u32 auth_mode       :1;
0179     u32 fcs_stream_copy :1;
0180     u32 un2         :2;
0181     u32 mix_key_sel     :1;
0182     u32 aesnk       :4;
0183     u32 cipher_algorithm    :3;
0184     u32 un3         :1;
0185     u32 op_mode     :4;
0186 };
0187
0188 struct pkt_control_cipher {
0189     u32 algorithm_len   :16;
0190     u32 header_len      :16;
0191 };
0192
0193 /*
0194  * struct pkt_control_ecb - control packet for ECB
0195  */
0196 struct pkt_control_ecb {
0197     struct pkt_control_header control;
0198     struct pkt_control_cipher cipher;
0199     unsigned char key[AES_MAX_KEY_SIZE];
0200 };
0201
0202 /*
0203  * struct sl3516_ce_dev - main container for all this driver information
0204  * @base:   base address
0205  * @clks:   clocks used
0206  * @reset:  pointer to reset controller
0207  * @dev:    the platform device
0208  * @engine: ptr to the crypto/crypto_engine
0209  * @complete:   completion for the current task on this flow
0210  * @status: set to 1 by interrupt if task is done
0211  * @dtx:    base DMA address for TX descriptors
0212  * @tx      base address of TX descriptors
0213  * @drx:    base DMA address for RX descriptors
0214  * @rx      base address of RX descriptors
0215  * @ctx     current used TX descriptor
0216  * @crx     current used RX descriptor
0217  * @trng    hw_random structure for RNG
0218  * @hwrng_stat_req  number of HWRNG requests
0219  * @hwrng_stat_bytes    total number of bytes generated by RNG
0220  * @stat_irq    number of IRQ handled by CE
0221  * @stat_irq_tx number of TX IRQ handled by CE
0222  * @stat_irq_rx number of RX IRQ handled by CE
0223  * @stat_req    number of requests handled by CE
0224  * @fallbak_sg_count_tx     number of fallback due to destination SG count
0225  * @fallbak_sg_count_rx     number of fallback due to source SG count
0226  * @fallbak_not_same_len    number of fallback due to difference in SG length
0227  * @dbgfs_dir:  Debugfs dentry for statistic directory
0228  * @dbgfs_stats: Debugfs dentry for statistic counters
0229  */
0230 struct sl3516_ce_dev {
0231     void __iomem *base;
0232     struct clk *clks;
0233     struct reset_control *reset;
0234     struct device *dev;
0235     struct crypto_engine *engine;
0236     struct completion complete;
0237     int status;
0238     dma_addr_t dtx;
0239     struct descriptor *tx;
0240     dma_addr_t drx;
0241     struct descriptor *rx;
0242     int ctx;
0243     int crx;
0244     struct hwrng trng;
0245     unsigned long hwrng_stat_req;
0246     unsigned long hwrng_stat_bytes;
0247     unsigned long stat_irq;
0248     unsigned long stat_irq_tx;
0249     unsigned long stat_irq_rx;
0250     unsigned long stat_req;
0251     unsigned long fallback_sg_count_tx;
0252     unsigned long fallback_sg_count_rx;
0253     unsigned long fallback_not_same_len;
0254     unsigned long fallback_mod16;
0255     unsigned long fallback_align16;
0256 #ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG
0257     struct dentry *dbgfs_dir;
0258     struct dentry *dbgfs_stats;
0259 #endif
0260     void *pctrl;
0261     dma_addr_t dctrl;
0262 };
0263
0264 struct sginfo {
0265     u32 addr;
0266     u32 len;
0267 };
0268
0269 /*
0270  * struct sl3516_ce_cipher_req_ctx - context for a skcipher request
0271  * @t_src:      list of mapped SGs with their size
0272  * @t_dst:      list of mapped SGs with their size
0273  * @op_dir:     direction (encrypt vs decrypt) for this request
0274  * @pctrllen:       the length of the ctrl packet
0275  * @tqflag:     the TQflag to set in data packet
0276  * @h           pointer to the pkt_control_cipher header
0277  * @nr_sgs:     number of source SG
0278  * @nr_sgd:     number of destination SG
0279  * @fallback_req:   request struct for invoking the fallback skcipher TFM
0280  */
0281 struct sl3516_ce_cipher_req_ctx {
0282     struct sginfo t_src[MAXDESC];
0283     struct sginfo t_dst[MAXDESC];
0284     u32 op_dir;
0285     unsigned int pctrllen;
0286     u32 tqflag;
0287     struct pkt_control_cipher *h;
0288     int nr_sgs;
0289     int nr_sgd;
0290     struct skcipher_request fallback_req;   // keep at the end
0291 };
0292
0293 /*
0294  * struct sl3516_ce_cipher_tfm_ctx - context for a skcipher TFM
0295  * @enginectx:      crypto_engine used by this TFM
0296  * @key:        pointer to key data
0297  * @keylen:     len of the key
0298  * @ce:         pointer to the private data of driver handling this TFM
0299  * @fallback_tfm:   pointer to the fallback TFM
0300  *
0301  * enginectx must be the first element
0302  */
0303 struct sl3516_ce_cipher_tfm_ctx {
0304     struct crypto_engine_ctx enginectx;
0305     u32 *key;
0306     u32 keylen;
0307     struct sl3516_ce_dev *ce;
0308     struct crypto_skcipher *fallback_tfm;
0309 };
0310
0311 /*
0312  * struct sl3516_ce_alg_template - crypto_alg template
0313  * @type:       the CRYPTO_ALG_TYPE for this template
0314  * @mode:       value to be used in control packet for this algorithm
0315  * @ce:         pointer to the sl3516_ce_dev structure associated with
0316  *          this template
0317  * @alg:        one of sub struct must be used
0318  * @stat_req:       number of request done on this template
0319  * @stat_fb:        number of request which has fallbacked
0320  * @stat_bytes:     total data size done by this template
0321  */
0322 struct sl3516_ce_alg_template {
0323     u32 type;
0324     u32 mode;
0325     struct sl3516_ce_dev *ce;
0326     union {
0327         struct skcipher_alg skcipher;
0328     } alg;
0329     unsigned long stat_req;
0330     unsigned long stat_fb;
0331     unsigned long stat_bytes;
0332 };
0333
0334 int sl3516_ce_enqueue(struct crypto_async_request *areq, u32 type);
0335
0336 int sl3516_ce_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
0337              unsigned int keylen);
0338 int sl3516_ce_cipher_init(struct crypto_tfm *tfm);
0339 void sl3516_ce_cipher_exit(struct crypto_tfm *tfm);
0340 int sl3516_ce_skdecrypt(struct skcipher_request *areq);
0341 int sl3516_ce_skencrypt(struct skcipher_request *areq);
0342
0343 int sl3516_ce_run_task(struct sl3516_ce_dev *ce,
0344                struct sl3516_ce_cipher_req_ctx *rctx, const char *name);
0345
0346 int sl3516_ce_rng_register(struct sl3516_ce_dev *ce);
0347 void sl3516_ce_rng_unregister(struct sl3516_ce_dev *ce);