crypto/chelsio/chcr_core.h

0001 /*
0002  * This file is part of the Chelsio T6 Crypto driver for Linux.
0003  *
0004  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
0005  *
0006  * This software is available to you under a choice of one of two
0007  * licenses.  You may choose to be licensed under the terms of the GNU
0008  * General Public License (GPL) Version 2, available from the file
0009  * COPYING in the main directory of this source tree, or the
0010  * OpenIB.org BSD license below:
0011  *
0012  *     Redistribution and use in source and binary forms, with or
0013  *     without modification, are permitted provided that the following
0014  *     conditions are met:
0015  *
0016  *      - Redistributions of source code must retain the above
0017  *        copyright notice, this list of conditions and the following
0018  *        disclaimer.
0019  *
0020  *      - Redistributions in binary form must reproduce the above
0021  *        copyright notice, this list of conditions and the following
0022  *        disclaimer in the documentation and/or other materials
0023  *        provided with the distribution.
0024  *
0025  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0026  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0027  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0028  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0029  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0030  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0031  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0032  * SOFTWARE.
0033  *
0034  */
0035
0036 #ifndef __CHCR_CORE_H__
0037 #define __CHCR_CORE_H__
0038
0039 #include <crypto/algapi.h>
0040 #include <net/tls.h>
0041 #include "t4_hw.h"
0042 #include "cxgb4.h"
0043 #include "t4_msg.h"
0044 #include "cxgb4_uld.h"
0045
0046 #define DRV_MODULE_NAME "chcr"
0047 #define DRV_DESC "Chelsio T6 Crypto Co-processor Driver"
0048
0049 #define MAX_PENDING_REQ_TO_HW 20
0050 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
0051 #define WQ_DETACH_TM    (msecs_to_jiffies(50))
0052 #define PAD_ERROR_BIT       1
0053 #define CHK_PAD_ERR_BIT(x)  (((x) >> PAD_ERROR_BIT) & 1)
0054
0055 #define MAC_ERROR_BIT       0
0056 #define CHK_MAC_ERR_BIT(x)  (((x) >> MAC_ERROR_BIT) & 1)
0057 #define MAX_SALT                4
0058 #define CIP_WR_MIN_LEN (sizeof(struct chcr_wr) + \
0059             sizeof(struct cpl_rx_phys_dsgl) + \
0060             sizeof(struct ulptx_sgl) + 16) //IV
0061
0062 #define HASH_WR_MIN_LEN (sizeof(struct chcr_wr) + \
0063             DUMMY_BYTES + \
0064             sizeof(struct ulptx_sgl))
0065 struct uld_ctx;
0066
0067 struct _key_ctx {
0068     __be32 ctx_hdr;
0069     u8 salt[MAX_SALT];
0070     __be64 iv_to_auth;
0071     unsigned char key[];
0072 };
0073
0074 #define WQ_RETRY    5
0075 struct chcr_driver_data {
0076     struct list_head act_dev;
0077     struct list_head inact_dev;
0078     atomic_t dev_count;
0079     struct mutex drv_mutex;
0080     struct uld_ctx *last_dev;
0081 };
0082
0083 enum chcr_state {
0084     CHCR_INIT = 0,
0085     CHCR_ATTACH,
0086     CHCR_DETACH,
0087 };
0088 struct chcr_wr {
0089     struct fw_crypto_lookaside_wr wreq;
0090     struct ulp_txpkt ulptx;
0091     struct ulptx_idata sc_imm;
0092     struct cpl_tx_sec_pdu sec_cpl;
0093     struct _key_ctx key_ctx;
0094 };
0095
0096 struct chcr_dev {
0097     spinlock_t lock_chcr_dev;
0098     enum chcr_state state;
0099     atomic_t inflight;
0100     int wqretry;
0101     struct delayed_work detach_work;
0102     struct completion detach_comp;
0103 };
0104
0105 struct uld_ctx {
0106     struct list_head entry;
0107     struct cxgb4_lld_info lldi;
0108     struct chcr_dev dev;
0109 };
0110
0111 /*
0112  *      sgl_len - calculates the size of an SGL of the given capacity
0113  *      @n: the number of SGL entries
0114  *      Calculates the number of flits needed for a scatter/gather list that
0115  *      can hold the given number of entries.
0116  */
0117 static inline unsigned int sgl_len(unsigned int n)
0118 {
0119     n--;
0120     return (3 * n) / 2 + (n & 1) + 2;
0121 }
0122
0123 static inline void *padap(struct chcr_dev *dev)
0124 {
0125     struct uld_ctx *u_ctx = container_of(dev, struct uld_ctx, dev);
0126
0127     return pci_get_drvdata(u_ctx->lldi.pdev);
0128 }
0129
0130 struct uld_ctx *assign_chcr_device(void);
0131 int chcr_send_wr(struct sk_buff *skb);
0132 int start_crypto(void);
0133 int stop_crypto(void);
0134 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
0135             const struct pkt_gl *pgl);
0136 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
0137 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
0138              int err);
0139 #endif /* __CHCR_CORE_H__ */