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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
0003 
0004 #ifndef __CC_CRYS_KERNEL_H__
0005 #define __CC_CRYS_KERNEL_H__
0006 
0007 // --------------------------------------
0008 // BLOCK: DSCRPTR
0009 // --------------------------------------
0010 #define CC_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET    0xE00UL
0011 #define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT  0x0UL
0012 #define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE   0x6UL
0013 #define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT    0x6UL
0014 #define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL
0015 #define CC_DSCRPTR_SW_RESET_REG_OFFSET  0xE40UL
0016 #define CC_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL
0017 #define CC_DSCRPTR_SW_RESET_VALUE_BIT_SIZE  0x1UL
0018 #define CC_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET   0xE60UL
0019 #define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL
0020 #define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE  0xAUL
0021 #define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT  0xAUL
0022 #define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE   0xCUL
0023 #define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT  0x16UL
0024 #define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE   0x3UL
0025 #define CC_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET    0xE64UL
0026 #define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT   0x0UL
0027 #define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE    0x1UL
0028 #define CC_DSCRPTR_MEASURE_CNTR_REG_OFFSET  0xE68UL
0029 #define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL
0030 #define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE  0x20UL
0031 #define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET   0xE80UL
0032 #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT  0x0UL
0033 #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE   0x20UL
0034 #define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET   0xE84UL
0035 #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT   0x0UL
0036 #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE    0x2UL
0037 #define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT   0x2UL
0038 #define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE    0x18UL
0039 #define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL
0040 #define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE  0x1UL
0041 #define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT    0x1BUL
0042 #define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL
0043 #define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT   0x1CUL
0044 #define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE    0x1UL
0045 #define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL
0046 #define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE  0x1UL
0047 #define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT   0x1EUL
0048 #define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE    0x2UL
0049 #define CC_DSCRPTR_QUEUE_WORD2_REG_OFFSET   0xE88UL
0050 #define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT  0x0UL
0051 #define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE   0x20UL
0052 #define CC_DSCRPTR_QUEUE_WORD3_REG_OFFSET   0xE8CUL
0053 #define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT  0x0UL
0054 #define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE   0x2UL
0055 #define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT  0x2UL
0056 #define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE   0x18UL
0057 #define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL
0058 #define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE  0x1UL
0059 #define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT  0x1BUL
0060 #define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE   0x1UL
0061 #define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT   0x1DUL
0062 #define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE    0x1UL
0063 #define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT   0x1EUL
0064 #define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE    0x1UL
0065 #define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL
0066 #define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE  0x1UL
0067 #define CC_DSCRPTR_QUEUE_WORD4_REG_OFFSET   0xE90UL
0068 #define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL
0069 #define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE  0x6UL
0070 #define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL
0071 #define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE  0x1UL
0072 #define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL
0073 #define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE  0x1UL
0074 #define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL
0075 #define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE  0x2UL
0076 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT    0xAUL
0077 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL
0078 #define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL
0079 #define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE  0x1UL
0080 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT  0xFUL
0081 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE   0x2UL
0082 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT   0x11UL
0083 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE    0x2UL
0084 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT   0x13UL
0085 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE    0x1UL
0086 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT   0x14UL
0087 #define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE    0x2UL
0088 #define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT   0x16UL
0089 #define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE    0x2UL
0090 #define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT    0x18UL
0091 #define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL
0092 #define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT    0x1CUL
0093 #define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL
0094 #define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT   0x1DUL
0095 #define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE    0x1UL
0096 #define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT  0x1EUL
0097 #define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE   0x1UL
0098 #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL
0099 #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE  0x1UL
0100 #define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET   0xE94UL
0101 #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT  0x0UL
0102 #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE   0x10UL
0103 #define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL
0104 #define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE  0x10UL
0105 #define CC_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET   0xE98UL
0106 #define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT  0x0UL
0107 #define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE   0xAUL
0108 #define CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL
0109 #define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT    0x0UL
0110 #define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL
0111 // --------------------------------------
0112 // BLOCK: AXI_P
0113 // --------------------------------------
0114 #define CC_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL
0115 #define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT    0x0UL
0116 #define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL
0117 #define CC_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL
0118 #define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT    0x0UL
0119 #define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL
0120 #define CC_AXIM_MON_COMP_REG_OFFSET 0xB80UL
0121 #define CC_AXIM_MON_COMP8_REG_OFFSET    0xBA0UL
0122 #define CC_AXIM_MON_COMP_VALUE_BIT_SHIFT    0x0UL
0123 #define CC_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL
0124 #define CC_AXIM_MON_ERR_REG_OFFSET  0xBC4UL
0125 #define CC_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL
0126 #define CC_AXIM_MON_ERR_BRESP_BIT_SIZE  0x2UL
0127 #define CC_AXIM_MON_ERR_BID_BIT_SHIFT   0x2UL
0128 #define CC_AXIM_MON_ERR_BID_BIT_SIZE    0x4UL
0129 #define CC_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL
0130 #define CC_AXIM_MON_ERR_RRESP_BIT_SIZE  0x2UL
0131 #define CC_AXIM_MON_ERR_RID_BIT_SHIFT   0x12UL
0132 #define CC_AXIM_MON_ERR_RID_BIT_SIZE    0x4UL
0133 #define CC_AXIM_CFG_REG_OFFSET  0xBE8UL
0134 #define CC_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL
0135 #define CC_AXIM_CFG_BRESPMASK_BIT_SIZE  0x1UL
0136 #define CC_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL
0137 #define CC_AXIM_CFG_RRESPMASK_BIT_SIZE  0x1UL
0138 #define CC_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL
0139 #define CC_AXIM_CFG_INFLTMASK_BIT_SIZE  0x1UL
0140 #define CC_AXIM_CFG_COMPMASK_BIT_SHIFT  0x7UL
0141 #define CC_AXIM_CFG_COMPMASK_BIT_SIZE   0x1UL
0142 #define CC_AXIM_ACE_CONST_REG_OFFSET    0xBECUL
0143 #define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT    0x0UL
0144 #define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL
0145 #define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT    0x2UL
0146 #define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL
0147 #define CC_AXIM_ACE_CONST_ARBAR_BIT_SHIFT   0x4UL
0148 #define CC_AXIM_ACE_CONST_ARBAR_BIT_SIZE    0x2UL
0149 #define CC_AXIM_ACE_CONST_AWBAR_BIT_SHIFT   0x6UL
0150 #define CC_AXIM_ACE_CONST_AWBAR_BIT_SIZE    0x2UL
0151 #define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL
0152 #define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE  0x4UL
0153 #define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL
0154 #define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE  0x3UL
0155 #define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL
0156 #define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE  0x3UL
0157 #define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT   0x12UL
0158 #define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE    0x7UL
0159 #define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT   0x19UL
0160 #define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE    0x4UL
0161 #define CC_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL
0162 #define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL
0163 #define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE  0x4UL
0164 #define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT  0x4UL
0165 #define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE   0x4UL
0166 #define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT  0x8UL
0167 #define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE   0x4UL
0168 #endif  // __CC_CRYS_KERNEL_H__
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