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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
0003 
0004 #ifndef __CC_HW_QUEUE_DEFS_H__
0005 #define __CC_HW_QUEUE_DEFS_H__
0006 
0007 #include <linux/types.h>
0008 
0009 #include "cc_kernel_regs.h"
0010 #include <linux/bitfield.h>
0011 
0012 /******************************************************************************
0013  *              DEFINITIONS
0014  ******************************************************************************/
0015 
0016 #define HW_DESC_SIZE_WORDS      6
0017 /* Define max. available slots in HW queue */
0018 #define HW_QUEUE_SLOTS_MAX              15
0019 
0020 #define CC_REG_LOW(name)  (name ## _BIT_SHIFT)
0021 #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
0022 #define CC_GENMASK(name)  GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))
0023 
0024 #define CC_HWQ_GENMASK(word, field) \
0025     CC_GENMASK(CC_DSCRPTR_QUEUE_WORD ## word ## _ ## field)
0026 
0027 #define WORD0_VALUE     CC_HWQ_GENMASK(0, VALUE)
0028 #define WORD0_CPP_CIPHER_MODE   CC_HWQ_GENMASK(0, CPP_CIPHER_MODE)
0029 #define WORD1_DIN_CONST_VALUE   CC_HWQ_GENMASK(1, DIN_CONST_VALUE)
0030 #define WORD1_DIN_DMA_MODE  CC_HWQ_GENMASK(1, DIN_DMA_MODE)
0031 #define WORD1_DIN_SIZE      CC_HWQ_GENMASK(1, DIN_SIZE)
0032 #define WORD1_NOT_LAST      CC_HWQ_GENMASK(1, NOT_LAST)
0033 #define WORD1_NS_BIT        CC_HWQ_GENMASK(1, NS_BIT)
0034 #define WORD1_LOCK_QUEUE    CC_HWQ_GENMASK(1, LOCK_QUEUE)
0035 #define WORD2_VALUE     CC_HWQ_GENMASK(2, VALUE)
0036 #define WORD3_DOUT_DMA_MODE CC_HWQ_GENMASK(3, DOUT_DMA_MODE)
0037 #define WORD3_DOUT_LAST_IND CC_HWQ_GENMASK(3, DOUT_LAST_IND)
0038 #define WORD3_DOUT_SIZE     CC_HWQ_GENMASK(3, DOUT_SIZE)
0039 #define WORD3_HASH_XOR_BIT  CC_HWQ_GENMASK(3, HASH_XOR_BIT)
0040 #define WORD3_NS_BIT        CC_HWQ_GENMASK(3, NS_BIT)
0041 #define WORD3_QUEUE_LAST_IND    CC_HWQ_GENMASK(3, QUEUE_LAST_IND)
0042 #define WORD4_ACK_NEEDED    CC_HWQ_GENMASK(4, ACK_NEEDED)
0043 #define WORD4_AES_SEL_N_HASH    CC_HWQ_GENMASK(4, AES_SEL_N_HASH)
0044 #define WORD4_AES_XOR_CRYPTO_KEY CC_HWQ_GENMASK(4, AES_XOR_CRYPTO_KEY)
0045 #define WORD4_BYTES_SWAP    CC_HWQ_GENMASK(4, BYTES_SWAP)
0046 #define WORD4_CIPHER_CONF0  CC_HWQ_GENMASK(4, CIPHER_CONF0)
0047 #define WORD4_CIPHER_CONF1  CC_HWQ_GENMASK(4, CIPHER_CONF1)
0048 #define WORD4_CIPHER_CONF2  CC_HWQ_GENMASK(4, CIPHER_CONF2)
0049 #define WORD4_CIPHER_DO     CC_HWQ_GENMASK(4, CIPHER_DO)
0050 #define WORD4_CIPHER_MODE   CC_HWQ_GENMASK(4, CIPHER_MODE)
0051 #define WORD4_CMAC_SIZE0    CC_HWQ_GENMASK(4, CMAC_SIZE0)
0052 #define WORD4_DATA_FLOW_MODE    CC_HWQ_GENMASK(4, DATA_FLOW_MODE)
0053 #define WORD4_KEY_SIZE      CC_HWQ_GENMASK(4, KEY_SIZE)
0054 #define WORD4_SETUP_OPERATION   CC_HWQ_GENMASK(4, SETUP_OPERATION)
0055 #define WORD5_DIN_ADDR_HIGH CC_HWQ_GENMASK(5, DIN_ADDR_HIGH)
0056 #define WORD5_DOUT_ADDR_HIGH    CC_HWQ_GENMASK(5, DOUT_ADDR_HIGH)
0057 
0058 /******************************************************************************
0059  *              TYPE DEFINITIONS
0060  ******************************************************************************/
0061 
0062 struct cc_hw_desc {
0063     union {
0064         u32 word[HW_DESC_SIZE_WORDS];
0065         u16 hword[HW_DESC_SIZE_WORDS * 2];
0066     };
0067 };
0068 
0069 enum cc_axi_sec {
0070     AXI_SECURE = 0,
0071     AXI_NOT_SECURE = 1
0072 };
0073 
0074 enum cc_desc_direction {
0075     DESC_DIRECTION_ILLEGAL = -1,
0076     DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
0077     DESC_DIRECTION_DECRYPT_DECRYPT = 1,
0078     DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
0079     DESC_DIRECTION_END = S32_MAX,
0080 };
0081 
0082 enum cc_dma_mode {
0083     DMA_MODE_NULL       = -1,
0084     NO_DMA          = 0,
0085     DMA_SRAM        = 1,
0086     DMA_DLLI        = 2,
0087     DMA_MLLI        = 3,
0088     DMA_MODE_END        = S32_MAX,
0089 };
0090 
0091 enum cc_flow_mode {
0092     FLOW_MODE_NULL      = -1,
0093     /* data flows */
0094     BYPASS          = 0,
0095     DIN_AES_DOUT        = 1,
0096     AES_to_HASH     = 2,
0097     AES_and_HASH        = 3,
0098     DIN_DES_DOUT        = 4,
0099     DES_to_HASH     = 5,
0100     DES_and_HASH        = 6,
0101     DIN_HASH        = 7,
0102     DIN_HASH_and_BYPASS = 8,
0103     AESMAC_and_BYPASS   = 9,
0104     AES_to_HASH_and_DOUT    = 10,
0105     DIN_RC4_DOUT        = 11,
0106     DES_to_HASH_and_DOUT    = 12,
0107     AES_to_AES_to_HASH_and_DOUT = 13,
0108     AES_to_AES_to_HASH  = 14,
0109     AES_to_HASH_and_AES = 15,
0110     DIN_SM4_DOUT        = 16,
0111     DIN_AES_AESMAC      = 17,
0112     HASH_to_DOUT        = 18,
0113     /* setup flows */
0114     S_DIN_to_AES        = 32,
0115     S_DIN_to_AES2       = 33,
0116     S_DIN_to_DES        = 34,
0117     S_DIN_to_RC4        = 35,
0118     S_DIN_to_SM4        = 36,
0119     S_DIN_to_HASH       = 37,
0120     S_AES_to_DOUT       = 38,
0121     S_AES2_to_DOUT      = 39,
0122     S_SM4_to_DOUT       = 40,
0123     S_RC4_to_DOUT       = 41,
0124     S_DES_to_DOUT       = 42,
0125     S_HASH_to_DOUT      = 43,
0126     SET_FLOW_ID     = 44,
0127     FLOW_MODE_END = S32_MAX,
0128 };
0129 
0130 enum cc_setup_op {
0131     SETUP_LOAD_NOP      = 0,
0132     SETUP_LOAD_STATE0   = 1,
0133     SETUP_LOAD_STATE1   = 2,
0134     SETUP_LOAD_STATE2   = 3,
0135     SETUP_LOAD_KEY0     = 4,
0136     SETUP_LOAD_XEX_KEY  = 5,
0137     SETUP_WRITE_STATE0  = 8,
0138     SETUP_WRITE_STATE1  = 9,
0139     SETUP_WRITE_STATE2  = 10,
0140     SETUP_WRITE_STATE3  = 11,
0141     SETUP_OP_END = S32_MAX,
0142 };
0143 
0144 enum cc_hash_conf_pad {
0145     HASH_PADDING_DISABLED = 0,
0146     HASH_PADDING_ENABLED = 1,
0147     HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2,
0148     HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX,
0149 };
0150 
0151 enum cc_aes_mac_selector {
0152     AES_SK = 1,
0153     AES_CMAC_INIT = 2,
0154     AES_CMAC_SIZE0 = 3,
0155     AES_MAC_END = S32_MAX,
0156 };
0157 
0158 #define HW_KEY_MASK_CIPHER_DO     0x3
0159 #define HW_KEY_SHIFT_CIPHER_CFG2  2
0160 
0161 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
0162 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
0163 enum cc_hw_crypto_key {
0164     USER_KEY = 0,           /* 0x0000 */
0165     ROOT_KEY = 1,           /* 0x0001 */
0166     PROVISIONING_KEY = 2,       /* 0x0010 */ /* ==KCP */
0167     SESSION_KEY = 3,        /* 0x0011 */
0168     RESERVED_KEY = 4,       /* NA */
0169     PLATFORM_KEY = 5,       /* 0x0101 */
0170     CUSTOMER_KEY = 6,       /* 0x0110 */
0171     KFDE0_KEY = 7,          /* 0x0111 */
0172     KFDE1_KEY = 9,          /* 0x1001 */
0173     KFDE2_KEY = 10,         /* 0x1010 */
0174     KFDE3_KEY = 11,         /* 0x1011 */
0175     END_OF_KEYS = S32_MAX,
0176 };
0177 
0178 #define CC_NUM_HW_KEY_SLOTS 4
0179 #define CC_FIRST_HW_KEY_SLOT    0
0180 #define CC_LAST_HW_KEY_SLOT (CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1)
0181 
0182 #define CC_NUM_CPP_KEY_SLOTS    8
0183 #define CC_FIRST_CPP_KEY_SLOT   16
0184 #define CC_LAST_CPP_KEY_SLOT    (CC_FIRST_CPP_KEY_SLOT + \
0185                     CC_NUM_CPP_KEY_SLOTS - 1)
0186 
0187 enum cc_hw_aes_key_size {
0188     AES_128_KEY = 0,
0189     AES_192_KEY = 1,
0190     AES_256_KEY = 2,
0191     END_OF_AES_KEYS = S32_MAX,
0192 };
0193 
0194 enum cc_hash_cipher_pad {
0195     DO_NOT_PAD = 0,
0196     DO_PAD = 1,
0197     HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
0198 };
0199 
0200 #define CC_CPP_DIN_ADDR 0xFF00FF00UL
0201 #define CC_CPP_DIN_SIZE 0xFF00FFUL
0202 
0203 /*****************************/
0204 /* Descriptor packing macros */
0205 /*****************************/
0206 
0207 /**
0208  * hw_desc_init() - Init a HW descriptor struct
0209  * @pdesc: pointer to HW descriptor struct
0210  */
0211 static inline void hw_desc_init(struct cc_hw_desc *pdesc)
0212 {
0213     memset(pdesc, 0, sizeof(struct cc_hw_desc));
0214 }
0215 
0216 /**
0217  * set_queue_last_ind_bit() - Indicate the end of current HW descriptors flow
0218  * and release the HW engines.
0219  *
0220  * @pdesc: Pointer to HW descriptor struct
0221  */
0222 static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc)
0223 {
0224     pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
0225 }
0226 
0227 /**
0228  * set_din_type() - Set the DIN field of a HW descriptor
0229  *
0230  * @pdesc: Pointer to HW descriptor struct
0231  * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
0232  * @addr: DIN address
0233  * @size: Data size in bytes
0234  * @axi_sec: AXI secure bit
0235  */
0236 static inline void set_din_type(struct cc_hw_desc *pdesc,
0237                 enum cc_dma_mode dma_mode, dma_addr_t addr,
0238                 u32 size, enum cc_axi_sec axi_sec)
0239 {
0240     pdesc->word[0] = lower_32_bits(addr);
0241 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0242     pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr));
0243 #endif
0244     pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) |
0245                 FIELD_PREP(WORD1_DIN_SIZE, size) |
0246                 FIELD_PREP(WORD1_NS_BIT, axi_sec);
0247 }
0248 
0249 /**
0250  * set_din_no_dma() - Set the DIN field of a HW descriptor to NO DMA mode.
0251  * Used for NOP descriptor, register patches and other special modes.
0252  *
0253  * @pdesc: Pointer to HW descriptor struct
0254  * @addr: DIN address
0255  * @size: Data size in bytes
0256  */
0257 static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size)
0258 {
0259     pdesc->word[0] = addr;
0260     pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size);
0261 }
0262 
0263 /**
0264  * set_cpp_crypto_key() - Setup the special CPP descriptor
0265  *
0266  * @pdesc: Pointer to HW descriptor struct
0267  * @slot: Slot number
0268  */
0269 static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot)
0270 {
0271     pdesc->word[0] |= CC_CPP_DIN_ADDR;
0272 
0273     pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE);
0274     pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1);
0275 
0276     pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot);
0277 }
0278 
0279 /**
0280  * set_din_sram() - Set the DIN field of a HW descriptor to SRAM mode.
0281  * Note: No need to check SRAM alignment since host requests do not use SRAM and
0282  * the adaptor will enforce alignment checks.
0283  *
0284  * @pdesc: Pointer to HW descriptor struct
0285  * @addr: DIN address
0286  * @size: Data size in bytes
0287  */
0288 static inline void set_din_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
0289 {
0290     pdesc->word[0] = addr;
0291     pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) |
0292                 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM);
0293 }
0294 
0295 /**
0296  * set_din_const() - Set the DIN field of a HW descriptor to CONST mode
0297  *
0298  * @pdesc: Pointer to HW descriptor struct
0299  * @val: DIN const value
0300  * @size: Data size in bytes
0301  */
0302 static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size)
0303 {
0304     pdesc->word[0] = val;
0305     pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) |
0306             FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) |
0307             FIELD_PREP(WORD1_DIN_SIZE, size);
0308 }
0309 
0310 /**
0311  * set_din_not_last_indication() - Set the DIN not last input data indicator
0312  *
0313  * @pdesc: Pointer to HW descriptor struct
0314  */
0315 static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc)
0316 {
0317     pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1);
0318 }
0319 
0320 /**
0321  * set_dout_type() - Set the DOUT field of a HW descriptor
0322  *
0323  * @pdesc: Pointer to HW descriptor struct
0324  * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
0325  * @addr: DOUT address
0326  * @size: Data size in bytes
0327  * @axi_sec: AXI secure bit
0328  */
0329 static inline void set_dout_type(struct cc_hw_desc *pdesc,
0330                  enum cc_dma_mode dma_mode, dma_addr_t addr,
0331                  u32 size, enum cc_axi_sec axi_sec)
0332 {
0333     pdesc->word[2] = lower_32_bits(addr);
0334 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
0335     pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, upper_32_bits(addr));
0336 #endif
0337     pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) |
0338                 FIELD_PREP(WORD3_DOUT_SIZE, size) |
0339                 FIELD_PREP(WORD3_NS_BIT, axi_sec);
0340 }
0341 
0342 /**
0343  * set_dout_dlli() - Set the DOUT field of a HW descriptor to DLLI type
0344  * The LAST INDICATION is provided by the user
0345  *
0346  * @pdesc: Pointer to HW descriptor struct
0347  * @addr: DOUT address
0348  * @size: Data size in bytes
0349  * @axi_sec: AXI secure bit
0350  * @last_ind: The last indication bit
0351  */
0352 static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
0353                  u32 size, enum cc_axi_sec axi_sec,
0354                  u32 last_ind)
0355 {
0356     set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec);
0357     pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
0358 }
0359 
0360 /**
0361  * set_dout_mlli() - Set the DOUT field of a HW descriptor to MLLI type
0362  * The LAST INDICATION is provided by the user
0363  *
0364  * @pdesc: Pointer to HW descriptor struct
0365  * @addr: DOUT address
0366  * @size: Data size in bytes
0367  * @axi_sec: AXI secure bit
0368  * @last_ind: The last indication bit
0369  */
0370 static inline void set_dout_mlli(struct cc_hw_desc *pdesc, u32 addr, u32 size,
0371                  enum cc_axi_sec axi_sec, bool last_ind)
0372 {
0373     set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec);
0374     pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
0375 }
0376 
0377 /**
0378  * set_dout_no_dma() - Set the DOUT field of a HW descriptor to NO DMA mode.
0379  * Used for NOP descriptor, register patches and other special modes.
0380  *
0381  * @pdesc: pointer to HW descriptor struct
0382  * @addr: DOUT address
0383  * @size: Data size in bytes
0384  * @write_enable: Enables a write operation to a register
0385  */
0386 static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr,
0387                    u32 size, bool write_enable)
0388 {
0389     pdesc->word[2] = addr;
0390     pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) |
0391             FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable);
0392 }
0393 
0394 /**
0395  * set_xor_val() - Set the word for the XOR operation.
0396  *
0397  * @pdesc: Pointer to HW descriptor struct
0398  * @val: XOR data value
0399  */
0400 static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val)
0401 {
0402     pdesc->word[2] = val;
0403 }
0404 
0405 /**
0406  * set_xor_active() - Set the XOR indicator bit in the descriptor
0407  *
0408  * @pdesc: Pointer to HW descriptor struct
0409  */
0410 static inline void set_xor_active(struct cc_hw_desc *pdesc)
0411 {
0412     pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1);
0413 }
0414 
0415 /**
0416  * set_aes_not_hash_mode() - Select the AES engine instead of HASH engine when
0417  * setting up combined mode with AES XCBC MAC
0418  *
0419  * @pdesc: Pointer to HW descriptor struct
0420  */
0421 static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc)
0422 {
0423     pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1);
0424 }
0425 
0426 /**
0427  * set_aes_xor_crypto_key() - Set aes xor crypto key, which in some scenarios
0428  * selects the SM3 engine
0429  *
0430  * @pdesc: Pointer to HW descriptor struct
0431  */
0432 static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc)
0433 {
0434     pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1);
0435 }
0436 
0437 /**
0438  * set_dout_sram() - Set the DOUT field of a HW descriptor to SRAM mode
0439  * Note: No need to check SRAM alignment since host requests do not use SRAM and
0440  * the adaptor will enforce alignment checks.
0441  *
0442  * @pdesc: Pointer to HW descriptor struct
0443  * @addr: DOUT address
0444  * @size: Data size in bytes
0445  */
0446 static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
0447 {
0448     pdesc->word[2] = addr;
0449     pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) |
0450             FIELD_PREP(WORD3_DOUT_SIZE, size);
0451 }
0452 
0453 /**
0454  * set_xex_data_unit_size() - Set the data unit size for XEX mode in
0455  * data_out_addr[15:0]
0456  *
0457  * @pdesc: Pointer to HW descriptor struct
0458  * @size: Data unit size for XEX mode
0459  */
0460 static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size)
0461 {
0462     pdesc->word[2] = size;
0463 }
0464 
0465 /**
0466  * set_multi2_num_rounds() - Set the number of rounds for Multi2 in
0467  * data_out_addr[15:0]
0468  *
0469  * @pdesc: Pointer to HW descriptor struct
0470  * @num: Number of rounds for Multi2
0471  */
0472 static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num)
0473 {
0474     pdesc->word[2] = num;
0475 }
0476 
0477 /**
0478  * set_flow_mode() - Set the flow mode.
0479  *
0480  * @pdesc: Pointer to HW descriptor struct
0481  * @mode: Any one of the modes defined in [CC7x-DESC]
0482  */
0483 static inline void set_flow_mode(struct cc_hw_desc *pdesc,
0484                  enum cc_flow_mode mode)
0485 {
0486     pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode);
0487 }
0488 
0489 /**
0490  * set_cipher_mode() - Set the cipher mode.
0491  *
0492  * @pdesc: Pointer to HW descriptor struct
0493  * @mode: Any one of the modes defined in [CC7x-DESC]
0494  */
0495 static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode)
0496 {
0497     pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode);
0498 }
0499 
0500 /**
0501  * set_hash_cipher_mode() - Set the cipher mode for hash algorithms.
0502  *
0503  * @pdesc: Pointer to HW descriptor struct
0504  * @cipher_mode: Any one of the modes defined in [CC7x-DESC]
0505  * @hash_mode: specifies which hash is being handled
0506  */
0507 static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc,
0508                     enum drv_cipher_mode cipher_mode,
0509                     enum drv_hash_mode hash_mode)
0510 {
0511     set_cipher_mode(pdesc, cipher_mode);
0512     if (hash_mode == DRV_HASH_SM3)
0513         set_aes_xor_crypto_key(pdesc);
0514 }
0515 
0516 /**
0517  * set_cipher_config0() - Set the cipher configuration fields.
0518  *
0519  * @pdesc: Pointer to HW descriptor struct
0520  * @mode: Any one of the modes defined in [CC7x-DESC]
0521  */
0522 static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode)
0523 {
0524     pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode);
0525 }
0526 
0527 /**
0528  * set_cipher_config1() - Set the cipher configuration fields.
0529  *
0530  * @pdesc: Pointer to HW descriptor struct
0531  * @config: Padding mode
0532  */
0533 static inline void set_cipher_config1(struct cc_hw_desc *pdesc,
0534                       enum cc_hash_conf_pad config)
0535 {
0536     pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config);
0537 }
0538 
0539 /**
0540  * set_hw_crypto_key() - Set HW key configuration fields.
0541  *
0542  * @pdesc: Pointer to HW descriptor struct
0543  * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key
0544  */
0545 static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc,
0546                      enum cc_hw_crypto_key hw_key)
0547 {
0548     pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
0549                      (hw_key & HW_KEY_MASK_CIPHER_DO)) |
0550             FIELD_PREP(WORD4_CIPHER_CONF2,
0551                    (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2));
0552 }
0553 
0554 /**
0555  * set_bytes_swap() - Set byte order of all setup-finalize descriptors.
0556  *
0557  * @pdesc: Pointer to HW descriptor struct
0558  * @config: True to enable byte swapping
0559  */
0560 static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config)
0561 {
0562     pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config);
0563 }
0564 
0565 /**
0566  * set_cmac_size0_mode() - Set CMAC_SIZE0 mode.
0567  *
0568  * @pdesc: Pointer to HW descriptor struct
0569  */
0570 static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc)
0571 {
0572     pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1);
0573 }
0574 
0575 /**
0576  * set_key_size() - Set key size descriptor field.
0577  *
0578  * @pdesc: Pointer to HW descriptor struct
0579  * @size: Key size in bytes (NOT size code)
0580  */
0581 static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size)
0582 {
0583     pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size);
0584 }
0585 
0586 /**
0587  * set_key_size_aes() - Set AES key size.
0588  *
0589  * @pdesc: Pointer to HW descriptor struct
0590  * @size: Key size in bytes (NOT size code)
0591  */
0592 static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size)
0593 {
0594     set_key_size(pdesc, ((size >> 3) - 2));
0595 }
0596 
0597 /**
0598  * set_key_size_des() - Set DES key size.
0599  *
0600  * @pdesc: Pointer to HW descriptor struct
0601  * @size: Key size in bytes (NOT size code)
0602  */
0603 static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size)
0604 {
0605     set_key_size(pdesc, ((size >> 3) - 1));
0606 }
0607 
0608 /**
0609  * set_setup_mode() - Set the descriptor setup mode
0610  *
0611  * @pdesc: Pointer to HW descriptor struct
0612  * @mode: Any one of the setup modes defined in [CC7x-DESC]
0613  */
0614 static inline void set_setup_mode(struct cc_hw_desc *pdesc,
0615                   enum cc_setup_op mode)
0616 {
0617     pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode);
0618 }
0619 
0620 /**
0621  * set_cipher_do() - Set the descriptor cipher DO
0622  *
0623  * @pdesc: Pointer to HW descriptor struct
0624  * @config: Any one of the cipher do defined in [CC7x-DESC]
0625  */
0626 static inline void set_cipher_do(struct cc_hw_desc *pdesc,
0627                  enum cc_hash_cipher_pad config)
0628 {
0629     pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
0630                 (config & HW_KEY_MASK_CIPHER_DO));
0631 }
0632 
0633 #endif /*__CC_HW_QUEUE_DEFS_H__*/
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